1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_rst: phy reset control. 153 * @phy_cfg: phy register configuration, assigned by driver data. 154 */ 155 struct rockchip_usb2phy { 156 u8 dcd_retries; 157 u8 primary_retries; 158 struct regmap *grf_base; 159 struct regmap *usbgrf_base; 160 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 161 struct reset_ctl phy_rst; 162 const struct rockchip_usb2phy_cfg *phy_cfg; 163 }; 164 165 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 166 { 167 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 168 } 169 170 static inline int property_enable(struct regmap *base, 171 const struct usb2phy_reg *reg, bool en) 172 { 173 u32 val, mask, tmp; 174 175 tmp = en ? reg->enable : reg->disable; 176 mask = GENMASK(reg->bitend, reg->bitstart); 177 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 178 179 return regmap_write(base, reg->offset, val); 180 } 181 182 static inline bool property_enabled(struct regmap *base, 183 const struct usb2phy_reg *reg) 184 { 185 u32 tmp, orig; 186 u32 mask = GENMASK(reg->bitend, reg->bitstart); 187 188 regmap_read(base, reg->offset, &orig); 189 190 tmp = (orig & mask) >> reg->bitstart; 191 192 return tmp == reg->enable; 193 } 194 195 static const char *chg_to_string(enum power_supply_type chg_type) 196 { 197 switch (chg_type) { 198 case POWER_SUPPLY_TYPE_USB: 199 return "USB_SDP_CHARGER"; 200 case POWER_SUPPLY_TYPE_USB_DCP: 201 return "USB_DCP_CHARGER"; 202 case POWER_SUPPLY_TYPE_USB_CDP: 203 return "USB_CDP_CHARGER"; 204 case POWER_SUPPLY_TYPE_USB_FLOATING: 205 return "USB_FLOATING_CHARGER"; 206 default: 207 return "INVALID_CHARGER"; 208 } 209 } 210 211 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 212 bool en) 213 { 214 struct regmap *base = get_reg_base(rphy); 215 216 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 217 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 218 } 219 220 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 221 bool en) 222 { 223 struct regmap *base = get_reg_base(rphy); 224 225 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 226 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 227 } 228 229 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 230 bool en) 231 { 232 struct regmap *base = get_reg_base(rphy); 233 234 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 235 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 236 } 237 238 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 239 { 240 bool vout = false; 241 struct regmap *base = get_reg_base(rphy); 242 243 while (rphy->primary_retries--) { 244 /* voltage source on DP, probe on DM */ 245 rockchip_chg_enable_primary_det(rphy, true); 246 mdelay(CHG_PRIMARY_DET_TIME); 247 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 248 if (vout) 249 break; 250 } 251 252 rockchip_chg_enable_primary_det(rphy, false); 253 return vout; 254 } 255 256 int rockchip_chg_get_type(void) 257 { 258 const struct rockchip_usb2phy_port_cfg *port_cfg; 259 enum power_supply_type chg_type; 260 struct rockchip_usb2phy *rphy; 261 struct udevice *udev; 262 struct regmap *base; 263 bool is_dcd, vout; 264 int ret; 265 266 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 267 if (ret == -ENODEV) { 268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 269 if (ret) { 270 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 271 return ret; 272 } 273 } 274 275 rphy = dev_get_priv(udev); 276 base = get_reg_base(rphy); 277 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 278 279 /* Check USB-Vbus status first */ 280 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 281 pr_info("%s: no charger found\n", __func__); 282 return POWER_SUPPLY_TYPE_UNKNOWN; 283 } 284 285 /* Suspend USB-PHY and put the controller in non-driving mode */ 286 property_enable(base, &port_cfg->phy_sus, true); 287 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 288 289 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 290 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 291 292 /* stage 1, start DCD processing stage */ 293 rockchip_chg_enable_dcd(rphy, true); 294 295 while (rphy->dcd_retries--) { 296 mdelay(CHG_DCD_POLL_TIME); 297 298 /* get data contact detection status */ 299 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 300 301 if (is_dcd || !rphy->dcd_retries) { 302 /* 303 * stage 2, turn off DCD circuitry, then 304 * voltage source on DP, probe on DM. 305 */ 306 rockchip_chg_enable_dcd(rphy, false); 307 rockchip_chg_enable_primary_det(rphy, true); 308 break; 309 } 310 } 311 312 mdelay(CHG_PRIMARY_DET_TIME); 313 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 314 rockchip_chg_enable_primary_det(rphy, false); 315 if (vout) { 316 /* stage 3, voltage source on DM, probe on DP */ 317 rockchip_chg_enable_secondary_det(rphy, true); 318 } else { 319 if (!rphy->dcd_retries) { 320 /* floating charger found */ 321 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 322 goto out; 323 } else { 324 /* 325 * Retry some times to make sure that it's 326 * really a USB SDP charger. 327 */ 328 vout = rockchip_chg_primary_det_retry(rphy); 329 if (vout) { 330 /* stage 3, voltage source on DM, probe on DP */ 331 rockchip_chg_enable_secondary_det(rphy, true); 332 } else { 333 /* USB SDP charger found */ 334 chg_type = POWER_SUPPLY_TYPE_USB; 335 goto out; 336 } 337 } 338 } 339 340 mdelay(CHG_SECONDARY_DET_TIME); 341 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 342 /* stage 4, turn off voltage source */ 343 rockchip_chg_enable_secondary_det(rphy, false); 344 if (vout) 345 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 346 else 347 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 348 349 out: 350 /* Resume USB-PHY and put the controller in normal mode */ 351 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 352 property_enable(base, &port_cfg->phy_sus, false); 353 354 debug("charger is %s\n", chg_to_string(chg_type)); 355 356 return chg_type; 357 } 358 359 int rockchip_u2phy_vbus_detect(void) 360 { 361 int chg_type; 362 363 chg_type = rockchip_chg_get_type(); 364 365 return (chg_type == POWER_SUPPLY_TYPE_USB || 366 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 367 } 368 369 void otg_phy_init(struct dwc2_udc *dev) 370 { 371 const struct rockchip_usb2phy_port_cfg *port_cfg; 372 struct rockchip_usb2phy *rphy; 373 struct udevice *udev; 374 struct regmap *base; 375 int ret; 376 377 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 378 if (ret == -ENODEV) { 379 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 380 if (ret) { 381 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 382 return; 383 } 384 } 385 386 rphy = dev_get_priv(udev); 387 base = get_reg_base(rphy); 388 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 389 390 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 391 if(rphy->phy_cfg->clkout_ctl.disable) 392 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 393 394 /* Reset USB-PHY */ 395 property_enable(base, &port_cfg->phy_sus, true); 396 udelay(20); 397 property_enable(base, &port_cfg->phy_sus, false); 398 mdelay(2); 399 } 400 401 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 402 { 403 int ret; 404 405 if (rphy->phy_rst.dev) { 406 ret = reset_assert(&rphy->phy_rst); 407 if (ret < 0) { 408 pr_err("u2phy assert reset failed: %d", ret); 409 return ret; 410 } 411 412 udelay(20); 413 414 ret = reset_deassert(&rphy->phy_rst); 415 if (ret < 0) { 416 pr_err("u2phy deassert reset failed: %d", ret); 417 return ret; 418 } 419 420 udelay(100); 421 } 422 423 return 0; 424 } 425 426 static int rockchip_usb2phy_init(struct phy *phy) 427 { 428 struct udevice *parent = phy->dev->parent; 429 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 430 const struct rockchip_usb2phy_port_cfg *port_cfg; 431 struct regmap *base = get_reg_base(rphy); 432 433 if (phy->id == USB2PHY_PORT_OTG) { 434 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 435 } else if (phy->id == USB2PHY_PORT_HOST) { 436 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 437 } else { 438 dev_err(phy->dev, "phy id %lu not support", phy->id); 439 return -EINVAL; 440 } 441 442 property_enable(base, &port_cfg->phy_sus, false); 443 444 /* waiting for the utmi_clk to become stable */ 445 udelay(2000); 446 447 return 0; 448 } 449 450 static int rockchip_usb2phy_exit(struct phy *phy) 451 { 452 struct udevice *parent = phy->dev->parent; 453 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 454 const struct rockchip_usb2phy_port_cfg *port_cfg; 455 struct regmap *base = get_reg_base(rphy); 456 457 if (phy->id == USB2PHY_PORT_OTG) { 458 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 459 } else if (phy->id == USB2PHY_PORT_HOST) { 460 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 461 } else { 462 dev_err(phy->dev, "phy id %lu not support", phy->id); 463 return -EINVAL; 464 } 465 466 property_enable(base, &port_cfg->phy_sus, true); 467 468 return 0; 469 } 470 471 static int rockchip_usb2phy_power_on(struct phy *phy) 472 { 473 struct udevice *parent = phy->dev->parent; 474 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 475 struct udevice *vbus = rphy->vbus_supply[phy->id]; 476 int ret; 477 478 if (vbus) { 479 ret = regulator_set_enable(vbus, true); 480 if (ret) { 481 pr_err("%s: Failed to set VBus supply\n", __func__); 482 return ret; 483 } 484 } 485 486 return 0; 487 } 488 489 static int rockchip_usb2phy_power_off(struct phy *phy) 490 { 491 struct udevice *parent = phy->dev->parent; 492 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 493 struct udevice *vbus = rphy->vbus_supply[phy->id]; 494 int ret; 495 496 if (vbus) { 497 ret = regulator_set_enable(vbus, false); 498 if (ret) { 499 pr_err("%s: Failed to set VBus supply\n", __func__); 500 return ret; 501 } 502 } 503 504 return 0; 505 } 506 507 static int rockchip_usb2phy_of_xlate(struct phy *phy, 508 struct ofnode_phandle_args *args) 509 { 510 const char *dev_name = phy->dev->name; 511 struct udevice *parent = phy->dev->parent; 512 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 513 514 if (!strcasecmp(dev_name, "host-port")) { 515 phy->id = USB2PHY_PORT_HOST; 516 device_get_supply_regulator(phy->dev, "phy-supply", 517 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 518 } else if (!strcasecmp(dev_name, "otg-port")) { 519 phy->id = USB2PHY_PORT_OTG; 520 device_get_supply_regulator(phy->dev, "phy-supply", 521 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 522 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 523 device_get_supply_regulator(phy->dev, "vbus-supply", 524 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 525 } else { 526 pr_err("%s: invalid dev name\n", __func__); 527 return -EINVAL; 528 } 529 530 return 0; 531 } 532 533 static int rockchip_usb2phy_bind(struct udevice *dev) 534 { 535 struct udevice *child; 536 ofnode subnode; 537 const char *node_name; 538 int ret; 539 540 dev_for_each_subnode(subnode, dev) { 541 if (!ofnode_valid(subnode)) { 542 debug("%s: %s subnode not found", __func__, dev->name); 543 return -ENXIO; 544 } 545 546 node_name = ofnode_get_name(subnode); 547 debug("%s: subnode %s\n", __func__, node_name); 548 549 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 550 node_name, subnode, &child); 551 if (ret) { 552 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 553 __func__, node_name); 554 return ret; 555 } 556 } 557 558 return 0; 559 } 560 561 static int rockchip_usb2phy_probe(struct udevice *dev) 562 { 563 const struct rockchip_usb2phy_cfg *phy_cfgs; 564 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 565 struct udevice *parent = dev->parent; 566 struct udevice *syscon; 567 struct resource res; 568 u32 reg, index; 569 int ret; 570 571 if (!strncmp(parent->name, "root_driver", 11) && 572 dev_read_bool(dev, "rockchip,grf")) { 573 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 574 "rockchip,grf", &syscon); 575 if (ret) { 576 dev_err(dev, "get syscon grf failed\n"); 577 return ret; 578 } 579 580 rphy->grf_base = syscon_get_regmap(syscon); 581 } else { 582 rphy->grf_base = syscon_get_regmap(parent); 583 } 584 585 if (rphy->grf_base <= 0) { 586 dev_err(dev, "get syscon grf regmap failed\n"); 587 return -EINVAL; 588 } 589 590 if (dev_read_bool(dev, "rockchip,usbgrf")) { 591 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 592 "rockchip,usbgrf", &syscon); 593 if (ret) { 594 dev_err(dev, "get syscon usbgrf failed\n"); 595 return ret; 596 } 597 598 rphy->usbgrf_base = syscon_get_regmap(syscon); 599 if (rphy->usbgrf_base <= 0) { 600 dev_err(dev, "get syscon usbgrf regmap failed\n"); 601 return -EINVAL; 602 } 603 } else { 604 rphy->usbgrf_base = NULL; 605 } 606 607 if (!strncmp(parent->name, "root_driver", 11)) { 608 ret = dev_read_resource(dev, 0, &res); 609 reg = res.start; 610 } else { 611 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 612 } 613 614 if (ret) { 615 dev_err(dev, "could not read reg\n"); 616 return -EINVAL; 617 } 618 619 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 620 if (ret) 621 dev_dbg(dev, "no u2phy reset control specified\n"); 622 623 phy_cfgs = 624 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 625 if (!phy_cfgs) { 626 dev_err(dev, "unable to get phy_cfgs\n"); 627 return -EINVAL; 628 } 629 630 /* find out a proper config which can be matched with dt. */ 631 index = 0; 632 do { 633 if (phy_cfgs[index].reg == reg) { 634 rphy->phy_cfg = &phy_cfgs[index]; 635 break; 636 } 637 ++index; 638 } while (phy_cfgs[index].reg); 639 640 if (!rphy->phy_cfg) { 641 dev_err(dev, "no phy-config can be matched\n"); 642 return -EINVAL; 643 } 644 645 if (rphy->phy_cfg->phy_tuning) 646 rphy->phy_cfg->phy_tuning(rphy); 647 648 return 0; 649 } 650 651 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 652 { 653 struct regmap *base = get_reg_base(rphy); 654 int ret = 0; 655 656 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 657 if (rphy->phy_cfg->reg == 0x760) 658 ret = regmap_write(base, 0x76c, 0x00070004); 659 660 return ret; 661 } 662 663 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 664 { 665 struct regmap *base = get_reg_base(rphy); 666 unsigned int tmp, orig; 667 int ret; 668 669 if (soc_is_rk3308bs()) { 670 /* Enable otg/host port pre-emphasis during non-chirp phase */ 671 ret = regmap_read(base, 0, &orig); 672 if (ret) 673 return ret; 674 tmp = orig & ~GENMASK(2, 0); 675 tmp |= BIT(2) & GENMASK(2, 0); 676 ret = regmap_write(base, 0, tmp); 677 if (ret) 678 return ret; 679 680 /* Set otg port squelch trigger point configure to 100mv */ 681 ret = regmap_read(base, 0x004, &orig); 682 if (ret) 683 return ret; 684 tmp = orig & ~GENMASK(7, 5); 685 tmp |= 0x40 & GENMASK(7, 5); 686 ret = regmap_write(base, 0x004, tmp); 687 if (ret) 688 return ret; 689 690 ret = regmap_read(base, 0x008, &orig); 691 if (ret) 692 return ret; 693 tmp = orig & ~BIT(0); 694 tmp |= 0x1 & BIT(0); 695 ret = regmap_write(base, 0x008, tmp); 696 if (ret) 697 return ret; 698 699 /* Enable host port pre-emphasis during non-chirp phase */ 700 ret = regmap_read(base, 0x400, &orig); 701 if (ret) 702 return ret; 703 tmp = orig & ~GENMASK(2, 0); 704 tmp |= BIT(2) & GENMASK(2, 0); 705 ret = regmap_write(base, 0x400, tmp); 706 if (ret) 707 return ret; 708 709 /* Set host port squelch trigger point configure to 100mv */ 710 ret = regmap_read(base, 0x404, &orig); 711 if (ret) 712 return ret; 713 tmp = orig & ~GENMASK(7, 5); 714 tmp |= 0x40 & GENMASK(7, 5); 715 ret = regmap_write(base, 0x404, tmp); 716 if (ret) 717 return ret; 718 719 ret = regmap_read(base, 0x408, &orig); 720 if (ret) 721 return ret; 722 tmp = orig & ~BIT(0); 723 tmp |= 0x1 & BIT(0); 724 ret = regmap_write(base, 0x408, tmp); 725 if (ret) 726 return ret; 727 } 728 729 return 0; 730 } 731 732 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 733 { 734 struct regmap *base = get_reg_base(rphy); 735 unsigned int tmp, orig; 736 int ret; 737 738 if (soc_is_px30s()) { 739 /* Enable otg/host port pre-emphasis during non-chirp phase */ 740 ret = regmap_read(base, 0x8000, &orig); 741 if (ret) 742 return ret; 743 tmp = orig & ~GENMASK(2, 0); 744 tmp |= BIT(2) & GENMASK(2, 0); 745 ret = regmap_write(base, 0x8000, tmp); 746 if (ret) 747 return ret; 748 749 /* Set otg port squelch trigger point configure to 100mv */ 750 ret = regmap_read(base, 0x8004, &orig); 751 if (ret) 752 return ret; 753 tmp = orig & ~GENMASK(7, 5); 754 tmp |= 0x40 & GENMASK(7, 5); 755 ret = regmap_write(base, 0x8004, tmp); 756 if (ret) 757 return ret; 758 759 ret = regmap_read(base, 0x8008, &orig); 760 if (ret) 761 return ret; 762 tmp = orig & ~BIT(0); 763 tmp |= 0x1 & BIT(0); 764 ret = regmap_write(base, 0x8008, tmp); 765 if (ret) 766 return ret; 767 768 /* Enable host port pre-emphasis during non-chirp phase */ 769 ret = regmap_read(base, 0x8400, &orig); 770 if (ret) 771 return ret; 772 tmp = orig & ~GENMASK(2, 0); 773 tmp |= BIT(2) & GENMASK(2, 0); 774 ret = regmap_write(base, 0x8400, tmp); 775 if (ret) 776 return ret; 777 778 /* Set host port squelch trigger point configure to 100mv */ 779 ret = regmap_read(base, 0x8404, &orig); 780 if (ret) 781 return ret; 782 tmp = orig & ~GENMASK(7, 5); 783 tmp |= 0x40 & GENMASK(7, 5); 784 ret = regmap_write(base, 0x8404, tmp); 785 if (ret) 786 return ret; 787 788 ret = regmap_read(base, 0x8408, &orig); 789 if (ret) 790 return ret; 791 tmp = orig & ~BIT(0); 792 tmp |= 0x1 & BIT(0); 793 ret = regmap_write(base, 0x8408, tmp); 794 if (ret) 795 return ret; 796 } 797 798 return 0; 799 } 800 801 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 802 { 803 struct regmap *base = get_reg_base(rphy); 804 int ret; 805 806 /* Deassert SIDDQ to power on analog block */ 807 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 808 if (ret) 809 return ret; 810 811 /* Do reset after exit IDDQ mode */ 812 ret = rockchip_usb2phy_reset(rphy); 813 if (ret) 814 return ret; 815 816 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 817 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 818 if (ret) 819 return ret; 820 821 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 822 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 823 if (ret) 824 return ret; 825 826 return 0; 827 } 828 829 static struct phy_ops rockchip_usb2phy_ops = { 830 .init = rockchip_usb2phy_init, 831 .exit = rockchip_usb2phy_exit, 832 .power_on = rockchip_usb2phy_power_on, 833 .power_off = rockchip_usb2phy_power_off, 834 .of_xlate = rockchip_usb2phy_of_xlate, 835 }; 836 837 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 838 { 839 .reg = 0x100, 840 .num_ports = 2, 841 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 842 .port_cfgs = { 843 [USB2PHY_PORT_OTG] = { 844 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 845 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 846 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 847 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 848 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 849 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 850 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 851 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 852 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 853 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 854 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 855 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 856 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 857 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 858 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 859 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 860 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 861 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 862 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 863 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 864 }, 865 [USB2PHY_PORT_HOST] = { 866 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 867 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 868 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 869 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 870 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 871 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 872 } 873 }, 874 .chg_det = { 875 .opmode = { 0x0100, 3, 0, 5, 1 }, 876 .cp_det = { 0x0120, 24, 24, 0, 1 }, 877 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 878 .dp_det = { 0x0120, 25, 25, 0, 1 }, 879 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 880 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 881 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 882 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 883 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 884 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 885 }, 886 }, 887 { /* sentinel */ } 888 }; 889 890 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 891 { 892 .reg = 0x17c, 893 .num_ports = 2, 894 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 895 .port_cfgs = { 896 [USB2PHY_PORT_OTG] = { 897 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 898 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 899 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 900 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 901 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 902 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 903 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 904 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 905 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 906 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 907 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 908 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 909 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 910 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 911 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 912 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 913 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 914 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 915 }, 916 [USB2PHY_PORT_HOST] = { 917 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 918 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 919 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 920 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 921 } 922 }, 923 .chg_det = { 924 .opmode = { 0x017c, 3, 0, 5, 1 }, 925 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 926 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 927 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 928 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 929 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 930 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 931 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 932 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 933 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 934 }, 935 }, 936 { /* sentinel */ } 937 }; 938 939 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 940 { 941 .reg = 0x760, 942 .num_ports = 2, 943 .phy_tuning = rk322x_usb2phy_tuning, 944 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 945 .port_cfgs = { 946 [USB2PHY_PORT_OTG] = { 947 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 948 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 949 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 950 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 951 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 952 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 953 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 954 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 955 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 956 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 957 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 958 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 959 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 960 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 961 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 962 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 963 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 964 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 965 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 966 }, 967 [USB2PHY_PORT_HOST] = { 968 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 969 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 970 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 971 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 972 } 973 }, 974 .chg_det = { 975 .opmode = { 0x0760, 3, 0, 5, 1 }, 976 .cp_det = { 0x0884, 4, 4, 0, 1 }, 977 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 978 .dp_det = { 0x0884, 5, 5, 0, 1 }, 979 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 980 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 981 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 982 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 983 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 984 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 985 }, 986 }, 987 { 988 .reg = 0x800, 989 .num_ports = 2, 990 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 991 .port_cfgs = { 992 [USB2PHY_PORT_OTG] = { 993 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 994 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 995 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 996 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 997 }, 998 [USB2PHY_PORT_HOST] = { 999 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1000 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1001 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1002 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1003 } 1004 }, 1005 }, 1006 { /* sentinel */ } 1007 }; 1008 1009 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1010 { 1011 .reg = 0x100, 1012 .num_ports = 2, 1013 .phy_tuning = rk3308_usb2phy_tuning, 1014 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1015 .port_cfgs = { 1016 [USB2PHY_PORT_OTG] = { 1017 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1018 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1019 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1020 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1021 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1022 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1023 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1024 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1025 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1026 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1027 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1028 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1029 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1030 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1031 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1032 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1033 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1034 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1035 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1036 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1037 }, 1038 [USB2PHY_PORT_HOST] = { 1039 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1040 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1041 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1042 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1043 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1044 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1045 } 1046 }, 1047 .chg_det = { 1048 .opmode = { 0x0100, 3, 0, 5, 1 }, 1049 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1050 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1051 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1052 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1053 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1054 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1055 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1056 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1057 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1058 }, 1059 }, 1060 { /* sentinel */ } 1061 }; 1062 1063 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1064 { 1065 .reg = 0x100, 1066 .num_ports = 2, 1067 .phy_tuning = rk3328_usb2phy_tuning, 1068 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1069 .port_cfgs = { 1070 [USB2PHY_PORT_OTG] = { 1071 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1072 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1073 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1074 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1075 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1076 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1077 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1078 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1079 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1080 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1081 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1082 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1083 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1084 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1085 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1086 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1087 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1088 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1089 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1090 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1091 }, 1092 [USB2PHY_PORT_HOST] = { 1093 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1094 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1095 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1096 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1097 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1098 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1099 } 1100 }, 1101 .chg_det = { 1102 .opmode = { 0x0100, 3, 0, 5, 1 }, 1103 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1104 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1105 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1106 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1107 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1108 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1109 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1110 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1111 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1112 }, 1113 }, 1114 { /* sentinel */ } 1115 }; 1116 1117 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1118 { 1119 .reg = 0x700, 1120 .num_ports = 2, 1121 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1122 .port_cfgs = { 1123 [USB2PHY_PORT_OTG] = { 1124 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1125 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1126 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1127 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1128 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1129 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1130 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1131 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1132 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1133 }, 1134 [USB2PHY_PORT_HOST] = { 1135 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1136 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1137 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1138 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1139 } 1140 }, 1141 .chg_det = { 1142 .opmode = { 0x0700, 3, 0, 5, 1 }, 1143 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1144 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1145 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1146 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1147 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1148 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1149 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1150 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1151 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1152 }, 1153 }, 1154 { /* sentinel */ } 1155 }; 1156 1157 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1158 { 1159 .reg = 0xe450, 1160 .num_ports = 2, 1161 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1162 .port_cfgs = { 1163 [USB2PHY_PORT_OTG] = { 1164 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1165 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1166 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1167 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1168 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1169 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1170 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1171 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1172 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1173 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1174 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1175 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1176 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1177 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1178 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1179 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1180 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1181 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1182 }, 1183 [USB2PHY_PORT_HOST] = { 1184 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1185 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1186 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1187 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1188 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1189 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1190 } 1191 }, 1192 .chg_det = { 1193 .opmode = { 0xe454, 3, 0, 5, 1 }, 1194 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1195 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1196 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1197 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1198 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1199 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1200 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1201 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1202 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1203 }, 1204 }, 1205 { 1206 .reg = 0xe460, 1207 .num_ports = 2, 1208 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1209 .port_cfgs = { 1210 [USB2PHY_PORT_OTG] = { 1211 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1212 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1213 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1214 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1215 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1216 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1217 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1218 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1219 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1220 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1221 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1222 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1223 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1224 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1225 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1226 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1227 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1228 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1229 }, 1230 [USB2PHY_PORT_HOST] = { 1231 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1232 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1233 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1234 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1235 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1236 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1237 } 1238 }, 1239 .chg_det = { 1240 .opmode = { 0xe464, 3, 0, 5, 1 }, 1241 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1242 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1243 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1244 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1245 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1246 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1247 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1248 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1249 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1250 }, 1251 }, 1252 { /* sentinel */ } 1253 }; 1254 1255 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = { 1256 { 1257 .reg = 0xff3e0000, 1258 .num_ports = 1, 1259 .clkout_ctl = { 0x0058, 4, 4, 1, 0 }, 1260 .port_cfgs = { 1261 [USB2PHY_PORT_OTG] = { 1262 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 }, 1263 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 }, 1264 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 }, 1265 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 }, 1266 .iddig_output = { 0x0050, 10, 10, 0, 1 }, 1267 .iddig_en = { 0x0050, 9, 9, 0, 1 }, 1268 .idfall_det_en = { 0x0100, 5, 5, 0, 1 }, 1269 .idfall_det_st = { 0x0104, 5, 5, 0, 1 }, 1270 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 }, 1271 .idrise_det_en = { 0x0100, 4, 4, 0, 1 }, 1272 .idrise_det_st = { 0x0104, 4, 4, 0, 1 }, 1273 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 }, 1274 .ls_det_en = { 0x0100, 0, 0, 0, 1 }, 1275 .ls_det_st = { 0x0104, 0, 0, 0, 1 }, 1276 .ls_det_clr = { 0x0108, 0, 0, 0, 1 }, 1277 .utmi_avalid = { 0x0060, 10, 10, 0, 1 }, 1278 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 }, 1279 .utmi_iddig = { 0x0060, 6, 6, 0, 1 }, 1280 .utmi_ls = { 0x0060, 5, 4, 0, 1 }, 1281 }, 1282 }, 1283 .chg_det = { 1284 .opmode = { 0x0050, 3, 0, 5, 1 }, 1285 .cp_det = { 0x0060, 13, 13, 0, 1 }, 1286 .dcp_det = { 0x0060, 12, 12, 0, 1 }, 1287 .dp_det = { 0x0060, 14, 14, 0, 1 }, 1288 .idm_sink_en = { 0x0058, 8, 8, 0, 1 }, 1289 .idp_sink_en = { 0x0058, 7, 7, 0, 1 }, 1290 .idp_src_en = { 0x0058, 9, 9, 0, 1 }, 1291 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 }, 1292 .vdm_src_en = { 0x0058, 12, 12, 0, 1 }, 1293 .vdp_src_en = { 0x0058, 11, 11, 0, 1 }, 1294 }, 1295 }, 1296 { /* sentinel */ } 1297 }; 1298 1299 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1300 { 1301 .reg = 0x100, 1302 .num_ports = 2, 1303 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1304 .port_cfgs = { 1305 [USB2PHY_PORT_OTG] = { 1306 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1307 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1308 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1309 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1310 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1311 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1312 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1313 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1314 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1315 }, 1316 [USB2PHY_PORT_HOST] = { 1317 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1318 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1319 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1320 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1321 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1322 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1323 } 1324 }, 1325 .chg_det = { 1326 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1327 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1328 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1329 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1330 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1331 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1332 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1333 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1334 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1335 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1336 }, 1337 }, 1338 { /* sentinel */ } 1339 }; 1340 1341 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1342 { 1343 .reg = 0xffdf0000, 1344 .num_ports = 2, 1345 .port_cfgs = { 1346 [USB2PHY_PORT_OTG] = { 1347 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1348 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1349 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1350 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1351 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1352 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1353 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1354 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1355 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1356 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1357 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1358 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1359 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1360 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1361 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1362 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1363 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1364 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1365 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1366 }, 1367 [USB2PHY_PORT_HOST] = { 1368 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1369 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1370 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1371 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1372 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1373 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1374 } 1375 }, 1376 .chg_det = { 1377 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1378 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1379 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1380 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1381 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1382 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1383 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1384 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1385 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1386 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1387 }, 1388 } 1389 }; 1390 1391 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1392 { 1393 .reg = 0xfe8a0000, 1394 .num_ports = 2, 1395 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1396 .port_cfgs = { 1397 [USB2PHY_PORT_OTG] = { 1398 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1399 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1400 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1401 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1402 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1403 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1404 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1405 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1406 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1407 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1408 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1409 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1410 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1411 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1412 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1413 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1414 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1415 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1416 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1417 }, 1418 [USB2PHY_PORT_HOST] = { 1419 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1420 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1421 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1422 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1423 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1424 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1425 } 1426 }, 1427 .chg_det = { 1428 .opmode = { 0x0000, 3, 0, 5, 1 }, 1429 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1430 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1431 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1432 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1433 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1434 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1435 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1436 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1437 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1438 }, 1439 }, 1440 { 1441 .reg = 0xfe8b0000, 1442 .num_ports = 2, 1443 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1444 .port_cfgs = { 1445 [USB2PHY_PORT_OTG] = { 1446 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1447 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1448 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1449 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1450 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1451 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1452 }, 1453 [USB2PHY_PORT_HOST] = { 1454 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1455 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1456 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1457 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1458 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1459 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1460 } 1461 }, 1462 }, 1463 { /* sentinel */ } 1464 }; 1465 1466 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1467 { 1468 .reg = 0x0000, 1469 .num_ports = 1, 1470 .phy_tuning = rk3588_usb2phy_tuning, 1471 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1472 .port_cfgs = { 1473 [USB2PHY_PORT_OTG] = { 1474 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1475 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1476 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1477 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1478 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1479 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1480 } 1481 }, 1482 .chg_det = { 1483 .opmode = { 0x0008, 2, 2, 1, 0 }, 1484 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1485 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1486 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1487 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1488 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1489 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1490 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1491 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1492 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1493 }, 1494 }, 1495 { 1496 .reg = 0x4000, 1497 .num_ports = 1, 1498 .phy_tuning = rk3588_usb2phy_tuning, 1499 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1500 .port_cfgs = { 1501 /* Select suspend control from controller */ 1502 [USB2PHY_PORT_OTG] = { 1503 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1504 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1505 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1506 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1507 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1508 } 1509 }, 1510 }, 1511 { 1512 .reg = 0x8000, 1513 .num_ports = 1, 1514 .phy_tuning = rk3588_usb2phy_tuning, 1515 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1516 .port_cfgs = { 1517 [USB2PHY_PORT_HOST] = { 1518 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1519 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1520 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1521 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1522 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1523 } 1524 }, 1525 }, 1526 { 1527 .reg = 0xc000, 1528 .num_ports = 1, 1529 .phy_tuning = rk3588_usb2phy_tuning, 1530 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1531 .port_cfgs = { 1532 [USB2PHY_PORT_HOST] = { 1533 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1534 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1535 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1536 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1537 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1538 } 1539 }, 1540 }, 1541 { /* sentinel */ } 1542 }; 1543 1544 static const struct udevice_id rockchip_usb2phy_ids[] = { 1545 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1546 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1547 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1548 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1549 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1550 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1551 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1552 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 1553 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1554 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1555 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs }, 1556 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1557 { } 1558 }; 1559 1560 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1561 .name = "rockchip_usb2phy_port", 1562 .id = UCLASS_PHY, 1563 .ops = &rockchip_usb2phy_ops, 1564 }; 1565 1566 U_BOOT_DRIVER(rockchip_usb2phy) = { 1567 .name = "rockchip_usb2phy", 1568 .id = UCLASS_PHY, 1569 .of_match = rockchip_usb2phy_ids, 1570 .probe = rockchip_usb2phy_probe, 1571 .bind = rockchip_usb2phy_bind, 1572 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1573 }; 1574