1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <generic-phy.h> 10 #include <syscon.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 14 #include "../usb/gadget/dwc2_udc_otg_priv.h" 15 16 #define U2PHY_BIT_WRITEABLE_SHIFT 16 17 #define CHG_DCD_MAX_RETRIES 6 18 #define CHG_PRI_MAX_RETRIES 2 19 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 20 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 21 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 22 23 struct rockchip_usb2phy; 24 25 enum power_supply_type { 26 POWER_SUPPLY_TYPE_UNKNOWN = 0, 27 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 28 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 29 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 30 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 31 }; 32 33 enum rockchip_usb2phy_port_id { 34 USB2PHY_PORT_OTG, 35 USB2PHY_PORT_HOST, 36 USB2PHY_NUM_PORTS, 37 }; 38 39 struct usb2phy_reg { 40 u32 offset; 41 u32 bitend; 42 u32 bitstart; 43 u32 disable; 44 u32 enable; 45 }; 46 47 /** 48 * struct rockchip_chg_det_reg: usb charger detect registers 49 * @cp_det: charging port detected successfully. 50 * @dcp_det: dedicated charging port detected successfully. 51 * @dp_det: assert data pin connect successfully. 52 * @idm_sink_en: open dm sink curren. 53 * @idp_sink_en: open dp sink current. 54 * @idp_src_en: open dm source current. 55 * @rdm_pdwn_en: open dm pull down resistor. 56 * @vdm_src_en: open dm voltage source. 57 * @vdp_src_en: open dp voltage source. 58 * @opmode: utmi operational mode. 59 */ 60 struct rockchip_chg_det_reg { 61 struct usb2phy_reg cp_det; 62 struct usb2phy_reg dcp_det; 63 struct usb2phy_reg dp_det; 64 struct usb2phy_reg idm_sink_en; 65 struct usb2phy_reg idp_sink_en; 66 struct usb2phy_reg idp_src_en; 67 struct usb2phy_reg rdm_pdwn_en; 68 struct usb2phy_reg vdm_src_en; 69 struct usb2phy_reg vdp_src_en; 70 struct usb2phy_reg opmode; 71 }; 72 73 /** 74 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 75 * @phy_sus: phy suspend register. 76 * @bvalid_det_en: vbus valid rise detection enable register. 77 * @bvalid_det_st: vbus valid rise detection status register. 78 * @bvalid_det_clr: vbus valid rise detection clear register. 79 * @ls_det_en: linestate detection enable register. 80 * @ls_det_st: linestate detection state register. 81 * @ls_det_clr: linestate detection clear register. 82 * @iddig_output: iddig output from grf. 83 * @iddig_en: utmi iddig select between grf and phy, 84 * 0: from phy; 1: from grf 85 * @idfall_det_en: id fall detection enable register. 86 * @idfall_det_st: id fall detection state register. 87 * @idfall_det_clr: id fall detection clear register. 88 * @idrise_det_en: id rise detection enable register. 89 * @idrise_det_st: id rise detection state register. 90 * @idrise_det_clr: id rise detection clear register. 91 * @utmi_avalid: utmi vbus avalid status register. 92 * @utmi_bvalid: utmi vbus bvalid status register. 93 * @utmi_iddig: otg port id pin status register. 94 * @utmi_ls: utmi linestate state register. 95 * @utmi_hstdet: utmi host disconnect register. 96 * @vbus_det_en: vbus detect function power down register. 97 */ 98 struct rockchip_usb2phy_port_cfg { 99 struct usb2phy_reg phy_sus; 100 struct usb2phy_reg bvalid_det_en; 101 struct usb2phy_reg bvalid_det_st; 102 struct usb2phy_reg bvalid_det_clr; 103 struct usb2phy_reg ls_det_en; 104 struct usb2phy_reg ls_det_st; 105 struct usb2phy_reg ls_det_clr; 106 struct usb2phy_reg iddig_output; 107 struct usb2phy_reg iddig_en; 108 struct usb2phy_reg idfall_det_en; 109 struct usb2phy_reg idfall_det_st; 110 struct usb2phy_reg idfall_det_clr; 111 struct usb2phy_reg idrise_det_en; 112 struct usb2phy_reg idrise_det_st; 113 struct usb2phy_reg idrise_det_clr; 114 struct usb2phy_reg utmi_avalid; 115 struct usb2phy_reg utmi_bvalid; 116 struct usb2phy_reg utmi_iddig; 117 struct usb2phy_reg utmi_ls; 118 struct usb2phy_reg utmi_hstdet; 119 struct usb2phy_reg vbus_det_en; 120 }; 121 122 /** 123 * struct rockchip_usb2phy_cfg: usb-phy configuration. 124 * @reg: the address offset of grf for usb-phy config. 125 * @num_ports: specify how many ports that the phy has. 126 * @phy_tuning: phy default parameters tunning. 127 * @clkout_ctl: keep on/turn off output clk of phy. 128 * @chg_det: charger detection registers. 129 */ 130 struct rockchip_usb2phy_cfg { 131 u32 reg; 132 u32 num_ports; 133 int (*phy_tuning)(struct rockchip_usb2phy *); 134 struct usb2phy_reg clkout_ctl; 135 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 136 const struct rockchip_chg_det_reg chg_det; 137 }; 138 139 /** 140 * @dcd_retries: The retry count used to track Data contact 141 * detection process. 142 * @primary_retries: The retry count used to do usb bc detection 143 * primary stage. 144 * @grf: General Register Files register base. 145 * @usbgrf_base : USB General Register Files register base. 146 * @phy_cfg: phy register configuration, assigned by driver data. 147 */ 148 struct rockchip_usb2phy { 149 u8 dcd_retries; 150 u8 primary_retries; 151 void __iomem *grf_base; 152 void __iomem *usbgrf_base; 153 const struct rockchip_usb2phy_cfg *phy_cfg; 154 }; 155 156 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 157 { 158 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 159 } 160 161 static inline int property_enable(void __iomem *base, 162 const struct usb2phy_reg *reg, bool en) 163 { 164 u32 val, mask, tmp; 165 166 tmp = en ? reg->enable : reg->disable; 167 mask = GENMASK(reg->bitend, reg->bitstart); 168 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 169 170 return writel(val, base + reg->offset); 171 } 172 173 static inline bool property_enabled(void __iomem *base, 174 const struct usb2phy_reg *reg) 175 { 176 u32 tmp, orig; 177 u32 mask = GENMASK(reg->bitend, reg->bitstart); 178 179 orig = readl(base + reg->offset); 180 181 tmp = (orig & mask) >> reg->bitstart; 182 183 return tmp == reg->enable; 184 } 185 186 static int rockchip_usb2phy_parse(struct rockchip_usb2phy *rphy) 187 { 188 const struct rockchip_usb2phy_cfg *phy_cfgs; 189 ofnode u2phy_node = ofnode_null(); 190 ofnode grf_node = ofnode_null(); 191 void __iomem *usbgrf_base = NULL; 192 void __iomem *grf_base = NULL; 193 struct udevice *udev; 194 fdt_size_t size; 195 u32 reg, index; 196 int ret; 197 198 memset((void *)rphy, 0, sizeof(struct rockchip_usb2phy)); 199 200 u2phy_node = ofnode_path("/usb2-phy"); 201 if (ofnode_valid(u2phy_node)) { 202 if (ofnode_read_bool(u2phy_node, "rockchip,grf")) 203 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 204 205 if (ofnode_read_bool(u2phy_node, "rockchip,usbgrf")) 206 usbgrf_base = 207 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 208 else 209 usbgrf_base = NULL; 210 } else { 211 grf_node = ofnode_path("/syscon-usb"); 212 if (ofnode_valid(grf_node)) { 213 grf_base = (void __iomem *) 214 ofnode_get_addr_size(grf_node, "reg", &size); 215 u2phy_node = ofnode_find_subnode(grf_node, "usb2-phy"); 216 } 217 } 218 219 if (!grf_base && !usbgrf_base) { 220 pr_err("%s: get grf/usbgrf node failed\n", __func__); 221 return -EINVAL; 222 } 223 224 if (!ofnode_valid(u2phy_node)) { 225 pr_err("%s: missing u2phy node\n", __func__); 226 return -EINVAL; 227 } 228 229 if (ofnode_read_u32(u2phy_node, "reg", ®)) { 230 pr_err("%s: could not read reg from u2phy node\n", __func__); 231 return -EINVAL; 232 } 233 234 ret = uclass_get_device_by_ofnode(UCLASS_PHY, u2phy_node, &udev); 235 if (ret) { 236 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 237 return -ENODEV; 238 } 239 240 phy_cfgs = 241 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(udev); 242 if (!phy_cfgs) { 243 pr_err("%s: unable to get phy_cfgs\n", __func__); 244 return -EINVAL; 245 } 246 247 /* find out a proper config which can be matched with dt. */ 248 index = 0; 249 while (phy_cfgs[index].reg) { 250 if (phy_cfgs[index].reg == reg) { 251 rphy->phy_cfg = &phy_cfgs[index]; 252 break; 253 } 254 ++index; 255 } 256 257 if (!rphy->phy_cfg) { 258 pr_err("%s: no phy-config can be matched\n", __func__); 259 return -EINVAL; 260 } 261 262 rphy->grf_base = grf_base; 263 rphy->usbgrf_base = usbgrf_base; 264 265 return 0; 266 } 267 268 static const char *chg_to_string(enum power_supply_type chg_type) 269 { 270 switch (chg_type) { 271 case POWER_SUPPLY_TYPE_USB: 272 return "USB_SDP_CHARGER"; 273 case POWER_SUPPLY_TYPE_USB_DCP: 274 return "USB_DCP_CHARGER"; 275 case POWER_SUPPLY_TYPE_USB_CDP: 276 return "USB_CDP_CHARGER"; 277 case POWER_SUPPLY_TYPE_USB_FLOATING: 278 return "USB_FLOATING_CHARGER"; 279 default: 280 return "INVALID_CHARGER"; 281 } 282 } 283 284 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 285 bool en) 286 { 287 void __iomem *base = get_reg_base(rphy); 288 289 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 290 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 291 } 292 293 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 294 bool en) 295 { 296 void __iomem *base = get_reg_base(rphy); 297 298 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 299 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 300 } 301 302 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 303 bool en) 304 { 305 void __iomem *base = get_reg_base(rphy); 306 307 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 308 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 309 } 310 311 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 312 { 313 bool vout = false; 314 315 while (rphy->primary_retries--) { 316 /* voltage source on DP, probe on DM */ 317 rockchip_chg_enable_primary_det(rphy, true); 318 mdelay(CHG_PRIMARY_DET_TIME); 319 vout = property_enabled(rphy->grf_base, 320 &rphy->phy_cfg->chg_det.cp_det); 321 if (vout) 322 break; 323 } 324 325 rockchip_chg_enable_primary_det(rphy, false); 326 return vout; 327 } 328 329 int rockchip_chg_get_type(void) 330 { 331 const struct rockchip_usb2phy_port_cfg *port_cfg; 332 enum power_supply_type chg_type; 333 struct rockchip_usb2phy rphy; 334 void __iomem *base; 335 bool is_dcd, vout; 336 int ret; 337 338 ret = rockchip_usb2phy_parse(&rphy); 339 if (ret) { 340 pr_err("%s: parse usb2phy failed %d\n", __func__, ret); 341 return ret; 342 } 343 344 base = get_reg_base(&rphy); 345 port_cfg = &rphy.phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 346 347 /* Suspend USB-PHY and put the controller in non-driving mode */ 348 property_enable(base, &port_cfg->phy_sus, true); 349 property_enable(base, &rphy.phy_cfg->chg_det.opmode, false); 350 351 rphy.dcd_retries = CHG_DCD_MAX_RETRIES; 352 rphy.primary_retries = CHG_PRI_MAX_RETRIES; 353 354 /* stage 1, start DCD processing stage */ 355 rockchip_chg_enable_dcd(&rphy, true); 356 357 while (rphy.dcd_retries--) { 358 mdelay(CHG_DCD_POLL_TIME); 359 360 /* get data contact detection status */ 361 is_dcd = property_enabled(rphy.grf_base, 362 &rphy.phy_cfg->chg_det.dp_det); 363 364 if (is_dcd || !rphy.dcd_retries) { 365 /* 366 * stage 2, turn off DCD circuitry, then 367 * voltage source on DP, probe on DM. 368 */ 369 rockchip_chg_enable_dcd(&rphy, false); 370 rockchip_chg_enable_primary_det(&rphy, true); 371 break; 372 } 373 } 374 375 mdelay(CHG_PRIMARY_DET_TIME); 376 vout = property_enabled(rphy.grf_base, 377 &rphy.phy_cfg->chg_det.cp_det); 378 rockchip_chg_enable_primary_det(&rphy, false); 379 if (vout) { 380 /* stage 3, voltage source on DM, probe on DP */ 381 rockchip_chg_enable_secondary_det(&rphy, true); 382 } else { 383 if (!rphy.dcd_retries) { 384 /* floating charger found */ 385 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 386 goto out; 387 } else { 388 /* 389 * Retry some times to make sure that it's 390 * really a USB SDP charger. 391 */ 392 vout = rockchip_chg_primary_det_retry(&rphy); 393 if (vout) { 394 /* stage 3, voltage source on DM, probe on DP */ 395 rockchip_chg_enable_secondary_det(&rphy, true); 396 } else { 397 /* USB SDP charger found */ 398 chg_type = POWER_SUPPLY_TYPE_USB; 399 goto out; 400 } 401 } 402 } 403 404 mdelay(CHG_SECONDARY_DET_TIME); 405 vout = property_enabled(rphy.grf_base, 406 &rphy.phy_cfg->chg_det.dcp_det); 407 /* stage 4, turn off voltage source */ 408 rockchip_chg_enable_secondary_det(&rphy, false); 409 if (vout) 410 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 411 else 412 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 413 414 out: 415 /* Resume USB-PHY and put the controller in normal mode */ 416 property_enable(base, &rphy.phy_cfg->chg_det.opmode, true); 417 property_enable(base, &port_cfg->phy_sus, false); 418 419 debug("charger is %s\n", chg_to_string(chg_type)); 420 421 return chg_type; 422 } 423 424 void otg_phy_init(struct dwc2_udc *dev) 425 { 426 const struct rockchip_usb2phy_port_cfg *port_cfg; 427 struct rockchip_usb2phy rphy; 428 void __iomem *base; 429 int ret; 430 431 ret = rockchip_usb2phy_parse(&rphy); 432 if (ret) { 433 pr_err("%s: parse usb2phy failed %d\n", __func__, ret); 434 return; 435 } 436 437 base = get_reg_base(&rphy); 438 port_cfg = &rphy.phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 439 440 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 441 property_enable(base, &rphy.phy_cfg->clkout_ctl, false); 442 443 /* Reset USB-PHY */ 444 property_enable(base, &port_cfg->phy_sus, true); 445 udelay(20); 446 property_enable(base, &port_cfg->phy_sus, false); 447 mdelay(2); 448 } 449 450 static int rockchip_usb2phy_init(struct phy *phy) 451 { 452 struct rockchip_usb2phy *rphy; 453 const struct rockchip_usb2phy_port_cfg *port_cfg; 454 void __iomem *base; 455 456 rphy = dev_get_priv(phy->dev); 457 base = get_reg_base(rphy); 458 459 if (phy->id == USB2PHY_PORT_OTG) { 460 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 461 } else if (phy->id == USB2PHY_PORT_HOST) { 462 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 463 } else { 464 dev_err(phy->dev, "phy id %lu not support", phy->id); 465 return -EINVAL; 466 } 467 468 property_enable(base, &port_cfg->phy_sus, false); 469 470 /* waiting for the utmi_clk to become stable */ 471 udelay(2000); 472 473 return 0; 474 } 475 476 static int rockchip_usb2phy_exit(struct phy *phy) 477 { 478 struct rockchip_usb2phy *rphy; 479 const struct rockchip_usb2phy_port_cfg *port_cfg; 480 void __iomem *base; 481 482 rphy = dev_get_priv(phy->dev); 483 base = get_reg_base(rphy); 484 485 if (phy->id == USB2PHY_PORT_OTG) { 486 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 487 } else if (phy->id == USB2PHY_PORT_HOST) { 488 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 489 } else { 490 dev_err(phy->dev, "phy id %lu not support", phy->id); 491 return -EINVAL; 492 } 493 494 property_enable(base, &port_cfg->phy_sus, true); 495 496 return 0; 497 } 498 499 static int rockchip_usb2phy_probe(struct udevice *dev) 500 { 501 const struct rockchip_usb2phy_cfg *phy_cfgs; 502 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 503 struct udevice *parent = dev->parent; 504 u32 reg, index; 505 506 if (!strncmp(parent->name, "root_driver", 11) && 507 dev_read_bool(dev, "rockchip,grf")) 508 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 509 else 510 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 511 512 if (rphy->grf_base <= 0) { 513 dev_err(dev, "get syscon grf failed\n"); 514 return -EINVAL; 515 } 516 517 if (dev_read_bool(dev, "rockchip,usbgrf")) { 518 rphy->usbgrf_base = 519 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 520 if (rphy->usbgrf_base <= 0) { 521 dev_err(dev, "get syscon usbgrf failed\n"); 522 return -EINVAL; 523 } 524 } else { 525 rphy->usbgrf_base = NULL; 526 } 527 528 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 529 dev_err(dev, "could not read reg\n"); 530 return -EINVAL; 531 } 532 533 phy_cfgs = 534 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 535 if (!phy_cfgs) { 536 dev_err(dev, "unable to get phy_cfgs\n"); 537 return -EINVAL; 538 } 539 540 /* find out a proper config which can be matched with dt. */ 541 index = 0; 542 while (phy_cfgs[index].reg) { 543 if (phy_cfgs[index].reg == reg) { 544 rphy->phy_cfg = &phy_cfgs[index]; 545 break; 546 } 547 ++index; 548 } 549 550 if (!rphy->phy_cfg) { 551 dev_err(dev, "no phy-config can be matched\n"); 552 return -EINVAL; 553 } 554 555 return 0; 556 } 557 558 static struct phy_ops rockchip_usb2phy_ops = { 559 .init = rockchip_usb2phy_init, 560 .exit = rockchip_usb2phy_exit, 561 }; 562 563 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 564 { 565 .reg = 0x17c, 566 .num_ports = 2, 567 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 568 .port_cfgs = { 569 [USB2PHY_PORT_OTG] = { 570 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 571 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 572 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 573 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 574 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 575 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 576 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 577 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 578 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 579 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 580 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 581 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 582 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 583 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 584 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 585 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 586 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 587 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 588 }, 589 [USB2PHY_PORT_HOST] = { 590 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 591 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 592 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 593 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 594 } 595 }, 596 .chg_det = { 597 .opmode = { 0x017c, 3, 0, 5, 1 }, 598 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 599 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 600 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 601 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 602 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 603 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 604 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 605 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 606 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 607 }, 608 }, 609 { /* sentinel */ } 610 }; 611 612 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 613 { 614 .reg = 0x100, 615 .num_ports = 2, 616 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 617 .port_cfgs = { 618 [USB2PHY_PORT_OTG] = { 619 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 620 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 621 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 622 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 623 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 624 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 625 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 626 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 627 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 628 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 629 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 630 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 631 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 632 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 633 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 634 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 635 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 636 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 637 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 638 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 639 }, 640 [USB2PHY_PORT_HOST] = { 641 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 642 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 643 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 644 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 645 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 646 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 647 } 648 }, 649 .chg_det = { 650 .opmode = { 0x0100, 3, 0, 5, 1 }, 651 .cp_det = { 0x0120, 24, 24, 0, 1 }, 652 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 653 .dp_det = { 0x0120, 25, 25, 0, 1 }, 654 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 655 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 656 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 657 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 658 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 659 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 660 }, 661 }, 662 { /* sentinel */ } 663 }; 664 665 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 666 { 667 .reg = 0x100, 668 .num_ports = 2, 669 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 670 .port_cfgs = { 671 [USB2PHY_PORT_OTG] = { 672 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 673 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 674 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 675 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 676 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 677 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 678 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 679 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 680 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 681 }, 682 [USB2PHY_PORT_HOST] = { 683 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 684 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 685 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 686 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 687 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 688 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 689 } 690 }, 691 .chg_det = { 692 .opmode = { 0x0100, 3, 0, 5, 1 }, 693 .cp_det = { 0x0804, 1, 1, 0, 1 }, 694 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 695 .dp_det = { 0x0804, 2, 2, 0, 1 }, 696 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 697 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 698 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 699 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 700 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 701 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 702 }, 703 }, 704 { /* sentinel */ } 705 }; 706 707 static const struct udevice_id rockchip_usb2phy_ids[] = { 708 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 709 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 710 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 711 { } 712 }; 713 714 U_BOOT_DRIVER(rockchip_usb2phy) = { 715 .name = "rockchip_usb2phy", 716 .id = UCLASS_PHY, 717 .of_match = rockchip_usb2phy_ids, 718 .ops = &rockchip_usb2phy_ops, 719 .probe = rockchip_usb2phy_probe, 720 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 721 }; 722