1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/gpio.h> 19 #include <reset-uclass.h> 20 21 #include "../usb/gadget/dwc2_udc_otg_priv.h" 22 23 #define U2PHY_BIT_WRITEABLE_SHIFT 16 24 #define CHG_DCD_MAX_RETRIES 6 25 #define CHG_PRI_MAX_RETRIES 2 26 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 27 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 28 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 29 30 struct rockchip_usb2phy; 31 32 enum power_supply_type { 33 POWER_SUPPLY_TYPE_UNKNOWN = 0, 34 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 35 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 36 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 37 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 38 }; 39 40 enum rockchip_usb2phy_port_id { 41 USB2PHY_PORT_OTG, 42 USB2PHY_PORT_HOST, 43 USB2PHY_NUM_PORTS, 44 }; 45 46 struct usb2phy_reg { 47 u32 offset; 48 u32 bitend; 49 u32 bitstart; 50 u32 disable; 51 u32 enable; 52 }; 53 54 /** 55 * struct rockchip_chg_det_reg: usb charger detect registers 56 * @cp_det: charging port detected successfully. 57 * @dcp_det: dedicated charging port detected successfully. 58 * @dp_det: assert data pin connect successfully. 59 * @idm_sink_en: open dm sink curren. 60 * @idp_sink_en: open dp sink current. 61 * @idp_src_en: open dm source current. 62 * @rdm_pdwn_en: open dm pull down resistor. 63 * @vdm_src_en: open dm voltage source. 64 * @vdp_src_en: open dp voltage source. 65 * @opmode: utmi operational mode. 66 */ 67 struct rockchip_chg_det_reg { 68 struct usb2phy_reg cp_det; 69 struct usb2phy_reg dcp_det; 70 struct usb2phy_reg dp_det; 71 struct usb2phy_reg idm_sink_en; 72 struct usb2phy_reg idp_sink_en; 73 struct usb2phy_reg idp_src_en; 74 struct usb2phy_reg rdm_pdwn_en; 75 struct usb2phy_reg vdm_src_en; 76 struct usb2phy_reg vdp_src_en; 77 struct usb2phy_reg opmode; 78 }; 79 80 /** 81 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 82 * @phy_sus: phy suspend register. 83 * @bvalid_det_en: vbus valid rise detection enable register. 84 * @bvalid_det_st: vbus valid rise detection status register. 85 * @bvalid_det_clr: vbus valid rise detection clear register. 86 * @ls_det_en: linestate detection enable register. 87 * @ls_det_st: linestate detection state register. 88 * @ls_det_clr: linestate detection clear register. 89 * @iddig_output: iddig output from grf. 90 * @iddig_en: utmi iddig select between grf and phy, 91 * 0: from phy; 1: from grf 92 * @idfall_det_en: id fall detection enable register. 93 * @idfall_det_st: id fall detection state register. 94 * @idfall_det_clr: id fall detection clear register. 95 * @idrise_det_en: id rise detection enable register. 96 * @idrise_det_st: id rise detection state register. 97 * @idrise_det_clr: id rise detection clear register. 98 * @utmi_avalid: utmi vbus avalid status register. 99 * @utmi_bvalid: utmi vbus bvalid status register. 100 * @utmi_iddig: otg port id pin status register. 101 * @utmi_ls: utmi linestate state register. 102 * @utmi_hstdet: utmi host disconnect register. 103 * @vbus_det_en: vbus detect function power down register. 104 */ 105 struct rockchip_usb2phy_port_cfg { 106 struct usb2phy_reg phy_sus; 107 struct usb2phy_reg bvalid_det_en; 108 struct usb2phy_reg bvalid_det_st; 109 struct usb2phy_reg bvalid_det_clr; 110 struct usb2phy_reg ls_det_en; 111 struct usb2phy_reg ls_det_st; 112 struct usb2phy_reg ls_det_clr; 113 struct usb2phy_reg iddig_output; 114 struct usb2phy_reg iddig_en; 115 struct usb2phy_reg idfall_det_en; 116 struct usb2phy_reg idfall_det_st; 117 struct usb2phy_reg idfall_det_clr; 118 struct usb2phy_reg idrise_det_en; 119 struct usb2phy_reg idrise_det_st; 120 struct usb2phy_reg idrise_det_clr; 121 struct usb2phy_reg utmi_avalid; 122 struct usb2phy_reg utmi_bvalid; 123 struct usb2phy_reg utmi_iddig; 124 struct usb2phy_reg utmi_ls; 125 struct usb2phy_reg utmi_hstdet; 126 struct usb2phy_reg vbus_det_en; 127 }; 128 129 /** 130 * struct rockchip_usb2phy_cfg: usb-phy configuration. 131 * @reg: the address offset of grf for usb-phy config. 132 * @num_ports: specify how many ports that the phy has. 133 * @phy_tuning: phy default parameters tunning. 134 * @clkout_ctl: keep on/turn off output clk of phy. 135 * @chg_det: charger detection registers. 136 */ 137 struct rockchip_usb2phy_cfg { 138 u32 reg; 139 u32 num_ports; 140 int (*phy_tuning)(struct rockchip_usb2phy *); 141 struct usb2phy_reg clkout_ctl; 142 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 143 const struct rockchip_chg_det_reg chg_det; 144 }; 145 146 /** 147 * @dcd_retries: The retry count used to track Data contact 148 * detection process. 149 * @primary_retries: The retry count used to do usb bc detection 150 * primary stage. 151 * @grf: General Register Files register base. 152 * @usbgrf_base : USB General Register Files register base. 153 * @phy_base: the base address of USB PHY. 154 * @phy_rst: phy reset control. 155 * @vbus_det_gpio: VBUS detection via GPIO. 156 * @phy_cfg: phy register configuration, assigned by driver data. 157 */ 158 struct rockchip_usb2phy { 159 u8 dcd_retries; 160 u8 primary_retries; 161 struct regmap *grf_base; 162 struct regmap *usbgrf_base; 163 void __iomem *phy_base; 164 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 165 struct reset_ctl phy_rst; 166 struct gpio_desc vbus_det_gpio; 167 const struct rockchip_usb2phy_cfg *phy_cfg; 168 }; 169 170 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 171 { 172 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 173 } 174 175 static inline int property_enable(struct regmap *base, 176 const struct usb2phy_reg *reg, bool en) 177 { 178 u32 val, mask, tmp; 179 180 tmp = en ? reg->enable : reg->disable; 181 mask = GENMASK(reg->bitend, reg->bitstart); 182 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 183 184 return regmap_write(base, reg->offset, val); 185 } 186 187 static inline bool property_enabled(struct regmap *base, 188 const struct usb2phy_reg *reg) 189 { 190 u32 tmp, orig; 191 u32 mask = GENMASK(reg->bitend, reg->bitstart); 192 193 regmap_read(base, reg->offset, &orig); 194 195 tmp = (orig & mask) >> reg->bitstart; 196 197 return tmp == reg->enable; 198 } 199 200 static inline void phy_clear_bits(void __iomem *reg, u32 bits) 201 { 202 u32 tmp = readl(reg); 203 204 tmp &= ~bits; 205 writel(tmp, reg); 206 } 207 208 static inline void phy_set_bits(void __iomem *reg, u32 bits) 209 { 210 u32 tmp = readl(reg); 211 212 tmp |= bits; 213 writel(tmp, reg); 214 } 215 216 static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val) 217 { 218 u32 tmp = readl(reg); 219 220 tmp &= ~mask; 221 tmp |= val & mask; 222 writel(tmp, reg); 223 } 224 225 static const char *chg_to_string(enum power_supply_type chg_type) 226 { 227 switch (chg_type) { 228 case POWER_SUPPLY_TYPE_USB: 229 return "USB_SDP_CHARGER"; 230 case POWER_SUPPLY_TYPE_USB_DCP: 231 return "USB_DCP_CHARGER"; 232 case POWER_SUPPLY_TYPE_USB_CDP: 233 return "USB_CDP_CHARGER"; 234 case POWER_SUPPLY_TYPE_USB_FLOATING: 235 return "USB_FLOATING_CHARGER"; 236 default: 237 return "INVALID_CHARGER"; 238 } 239 } 240 241 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 242 bool en) 243 { 244 struct regmap *base = get_reg_base(rphy); 245 246 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 247 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 248 } 249 250 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 251 bool en) 252 { 253 struct regmap *base = get_reg_base(rphy); 254 255 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 256 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 257 } 258 259 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 260 bool en) 261 { 262 struct regmap *base = get_reg_base(rphy); 263 264 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 265 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 266 } 267 268 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 269 { 270 bool vout = false; 271 struct regmap *base = get_reg_base(rphy); 272 273 while (rphy->primary_retries--) { 274 /* voltage source on DP, probe on DM */ 275 rockchip_chg_enable_primary_det(rphy, true); 276 mdelay(CHG_PRIMARY_DET_TIME); 277 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 278 if (vout) 279 break; 280 } 281 282 rockchip_chg_enable_primary_det(rphy, false); 283 return vout; 284 } 285 286 #ifdef CONFIG_ROCKCHIP_RK3506 287 static void rockchip_u2phy_get_vbus_gpio(struct udevice *dev) 288 { 289 ofnode otg_node, extcon_usb_node; 290 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 291 292 rphy->vbus_det_gpio.dev = NULL; 293 otg_node = dev_read_subnode(dev, "otg-port"); 294 if (!ofnode_valid(otg_node)) { 295 debug("%s: %s otg subnode not found!\n", __func__, dev->name); 296 return; 297 } 298 299 if (ofnode_read_bool(otg_node, "rockchip,gpio-vbus-det")) { 300 extcon_usb_node = ofnode_path("/extcon-usb"); 301 if (!ofnode_valid(extcon_usb_node)) { 302 debug("%s: extcon-usb node not found\n", __func__); 303 return; 304 } 305 306 gpio_request_by_name_nodev(extcon_usb_node, "vbus-gpio", 0, 307 &rphy->vbus_det_gpio, GPIOD_IS_IN); 308 } 309 } 310 #endif 311 312 int rockchip_chg_get_type(void) 313 { 314 const struct rockchip_usb2phy_port_cfg *port_cfg; 315 enum power_supply_type chg_type; 316 struct rockchip_usb2phy *rphy; 317 struct udevice *udev; 318 struct regmap *base; 319 bool is_dcd, vout; 320 int ret; 321 322 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 323 if (ret == -ENODEV) { 324 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 325 if (ret) { 326 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 327 return ret; 328 } 329 } 330 331 rphy = dev_get_priv(udev); 332 base = get_reg_base(rphy); 333 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 334 335 #ifdef CONFIG_ROCKCHIP_RK3506 336 rockchip_u2phy_get_vbus_gpio(udev); 337 #else 338 rphy->vbus_det_gpio.dev = NULL; 339 #endif 340 341 /* Check USB-Vbus status first */ 342 if (dm_gpio_is_valid(&rphy->vbus_det_gpio)) { 343 if (dm_gpio_get_value(&rphy->vbus_det_gpio)) { 344 pr_info("%s: vbus gpio voltage valid\n", __func__); 345 } else { 346 pr_info("%s: vbus gpio voltage invalid\n", __func__); 347 return POWER_SUPPLY_TYPE_UNKNOWN; 348 } 349 } else if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 350 pr_info("%s: no charger found\n", __func__); 351 return POWER_SUPPLY_TYPE_UNKNOWN; 352 } 353 354 #ifdef CONFIG_ROCKCHIP_RK3036 355 chg_type = POWER_SUPPLY_TYPE_USB; 356 goto out; 357 #endif 358 359 /* Suspend USB-PHY and put the controller in non-driving mode */ 360 property_enable(base, &port_cfg->phy_sus, true); 361 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 362 363 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 364 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 365 366 /* stage 1, start DCD processing stage */ 367 rockchip_chg_enable_dcd(rphy, true); 368 369 while (rphy->dcd_retries--) { 370 mdelay(CHG_DCD_POLL_TIME); 371 372 /* get data contact detection status */ 373 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 374 375 if (is_dcd || !rphy->dcd_retries) { 376 /* 377 * stage 2, turn off DCD circuitry, then 378 * voltage source on DP, probe on DM. 379 */ 380 rockchip_chg_enable_dcd(rphy, false); 381 rockchip_chg_enable_primary_det(rphy, true); 382 break; 383 } 384 } 385 386 mdelay(CHG_PRIMARY_DET_TIME); 387 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 388 rockchip_chg_enable_primary_det(rphy, false); 389 if (vout) { 390 /* stage 3, voltage source on DM, probe on DP */ 391 rockchip_chg_enable_secondary_det(rphy, true); 392 } else { 393 if (!rphy->dcd_retries) { 394 /* floating charger found */ 395 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 396 goto out; 397 } else { 398 /* 399 * Retry some times to make sure that it's 400 * really a USB SDP charger. 401 */ 402 vout = rockchip_chg_primary_det_retry(rphy); 403 if (vout) { 404 /* stage 3, voltage source on DM, probe on DP */ 405 rockchip_chg_enable_secondary_det(rphy, true); 406 } else { 407 /* USB SDP charger found */ 408 chg_type = POWER_SUPPLY_TYPE_USB; 409 goto out; 410 } 411 } 412 } 413 414 mdelay(CHG_SECONDARY_DET_TIME); 415 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 416 /* stage 4, turn off voltage source */ 417 rockchip_chg_enable_secondary_det(rphy, false); 418 if (vout) 419 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 420 else 421 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 422 423 out: 424 /* Resume USB-PHY and put the controller in normal mode */ 425 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 426 property_enable(base, &port_cfg->phy_sus, false); 427 428 debug("charger is %s\n", chg_to_string(chg_type)); 429 430 return chg_type; 431 } 432 433 int rockchip_u2phy_vbus_detect(void) 434 { 435 int chg_type; 436 437 chg_type = rockchip_chg_get_type(); 438 439 return (chg_type == POWER_SUPPLY_TYPE_USB || 440 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 441 } 442 443 void otg_phy_init(struct dwc2_udc *dev) 444 { 445 const struct rockchip_usb2phy_port_cfg *port_cfg; 446 struct rockchip_usb2phy *rphy; 447 struct udevice *udev; 448 struct regmap *base; 449 int ret; 450 451 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 452 if (ret == -ENODEV) { 453 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 454 if (ret) { 455 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 456 return; 457 } 458 } 459 460 rphy = dev_get_priv(udev); 461 base = get_reg_base(rphy); 462 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 463 464 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 465 if(rphy->phy_cfg->clkout_ctl.disable) 466 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 467 468 /* Reset USB-PHY */ 469 property_enable(base, &port_cfg->phy_sus, true); 470 udelay(20); 471 property_enable(base, &port_cfg->phy_sus, false); 472 mdelay(2); 473 } 474 475 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 476 { 477 int ret; 478 479 if (rphy->phy_rst.dev) { 480 ret = reset_assert(&rphy->phy_rst); 481 if (ret < 0) { 482 pr_err("u2phy assert reset failed: %d", ret); 483 return ret; 484 } 485 486 udelay(20); 487 488 ret = reset_deassert(&rphy->phy_rst); 489 if (ret < 0) { 490 pr_err("u2phy deassert reset failed: %d", ret); 491 return ret; 492 } 493 494 udelay(100); 495 } 496 497 return 0; 498 } 499 500 static int rockchip_usb2phy_init(struct phy *phy) 501 { 502 struct udevice *parent = phy->dev->parent; 503 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 504 const struct rockchip_usb2phy_port_cfg *port_cfg; 505 struct regmap *base = get_reg_base(rphy); 506 507 if (phy->id == USB2PHY_PORT_OTG) { 508 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 509 } else if (phy->id == USB2PHY_PORT_HOST) { 510 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 511 } else { 512 dev_err(phy->dev, "phy id %lu not support", phy->id); 513 return -EINVAL; 514 } 515 516 property_enable(base, &port_cfg->phy_sus, false); 517 518 /* waiting for the utmi_clk to become stable */ 519 udelay(2000); 520 521 return 0; 522 } 523 524 static int rockchip_usb2phy_exit(struct phy *phy) 525 { 526 struct udevice *parent = phy->dev->parent; 527 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 528 const struct rockchip_usb2phy_port_cfg *port_cfg; 529 struct regmap *base = get_reg_base(rphy); 530 531 if (phy->id == USB2PHY_PORT_OTG) { 532 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 533 } else if (phy->id == USB2PHY_PORT_HOST) { 534 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 535 } else { 536 dev_err(phy->dev, "phy id %lu not support", phy->id); 537 return -EINVAL; 538 } 539 540 property_enable(base, &port_cfg->phy_sus, true); 541 542 return 0; 543 } 544 545 static int rockchip_usb2phy_power_on(struct phy *phy) 546 { 547 struct udevice *parent = phy->dev->parent; 548 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 549 struct udevice *vbus = rphy->vbus_supply[phy->id]; 550 int ret; 551 552 if (vbus) { 553 ret = regulator_set_enable(vbus, true); 554 if (ret) { 555 pr_err("%s: Failed to set VBus supply\n", __func__); 556 return ret; 557 } 558 } 559 560 return 0; 561 } 562 563 static int rockchip_usb2phy_power_off(struct phy *phy) 564 { 565 struct udevice *parent = phy->dev->parent; 566 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 567 struct udevice *vbus = rphy->vbus_supply[phy->id]; 568 int ret; 569 570 if (vbus) { 571 ret = regulator_set_enable(vbus, false); 572 if (ret) { 573 pr_err("%s: Failed to set VBus supply\n", __func__); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static int rockchip_usb2phy_of_xlate(struct phy *phy, 582 struct ofnode_phandle_args *args) 583 { 584 const char *dev_name = phy->dev->name; 585 struct udevice *parent = phy->dev->parent; 586 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 587 588 if (!strcasecmp(dev_name, "host-port")) { 589 phy->id = USB2PHY_PORT_HOST; 590 device_get_supply_regulator(phy->dev, "phy-supply", 591 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 592 } else if (!strcasecmp(dev_name, "otg-port")) { 593 phy->id = USB2PHY_PORT_OTG; 594 device_get_supply_regulator(phy->dev, "phy-supply", 595 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 596 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 597 device_get_supply_regulator(phy->dev, "vbus-supply", 598 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 599 } else { 600 pr_err("%s: invalid dev name\n", __func__); 601 return -EINVAL; 602 } 603 604 return 0; 605 } 606 607 static int rockchip_usb2phy_bind(struct udevice *dev) 608 { 609 struct udevice *child; 610 ofnode subnode; 611 const char *node_name; 612 int ret; 613 614 dev_for_each_subnode(subnode, dev) { 615 if (!ofnode_valid(subnode)) { 616 debug("%s: %s subnode not found", __func__, dev->name); 617 return -ENXIO; 618 } 619 620 node_name = ofnode_get_name(subnode); 621 debug("%s: subnode %s\n", __func__, node_name); 622 623 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 624 node_name, subnode, &child); 625 if (ret) { 626 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 627 __func__, node_name); 628 return ret; 629 } 630 } 631 632 return 0; 633 } 634 635 static int rockchip_usb2phy_probe(struct udevice *dev) 636 { 637 const struct rockchip_usb2phy_cfg *phy_cfgs; 638 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 639 struct udevice *parent = dev->parent; 640 struct udevice *syscon; 641 struct resource res; 642 u32 reg, index; 643 int ret; 644 645 rphy->phy_base = (void __iomem *)dev_read_addr(dev); 646 if (IS_ERR(rphy->phy_base)) { 647 dev_err(dev, "get the base address of usb phy failed\n"); 648 } 649 650 if (!strncmp(parent->name, "root_driver", 11) && 651 dev_read_bool(dev, "rockchip,grf")) { 652 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 653 "rockchip,grf", &syscon); 654 if (ret) { 655 dev_err(dev, "get syscon grf failed\n"); 656 return ret; 657 } 658 659 rphy->grf_base = syscon_get_regmap(syscon); 660 } else { 661 rphy->grf_base = syscon_get_regmap(parent); 662 } 663 664 if (rphy->grf_base <= 0) { 665 dev_err(dev, "get syscon grf regmap failed\n"); 666 return -EINVAL; 667 } 668 669 if (dev_read_bool(dev, "rockchip,usbgrf")) { 670 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 671 "rockchip,usbgrf", &syscon); 672 if (ret) { 673 dev_err(dev, "get syscon usbgrf failed\n"); 674 return ret; 675 } 676 677 rphy->usbgrf_base = syscon_get_regmap(syscon); 678 if (rphy->usbgrf_base <= 0) { 679 dev_err(dev, "get syscon usbgrf regmap failed\n"); 680 return -EINVAL; 681 } 682 } else { 683 rphy->usbgrf_base = NULL; 684 } 685 686 if (!strncmp(parent->name, "root_driver", 11)) { 687 ret = dev_read_resource(dev, 0, &res); 688 reg = res.start; 689 } else { 690 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 691 } 692 693 if (ret) { 694 dev_err(dev, "could not read reg\n"); 695 return -EINVAL; 696 } 697 698 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 699 if (ret) 700 dev_dbg(dev, "no u2phy reset control specified\n"); 701 702 phy_cfgs = 703 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 704 if (!phy_cfgs) { 705 dev_err(dev, "unable to get phy_cfgs\n"); 706 return -EINVAL; 707 } 708 709 /* find out a proper config which can be matched with dt. */ 710 index = 0; 711 do { 712 if (phy_cfgs[index].reg == reg) { 713 rphy->phy_cfg = &phy_cfgs[index]; 714 break; 715 } 716 ++index; 717 } while (phy_cfgs[index].reg); 718 719 if (!rphy->phy_cfg) { 720 dev_err(dev, "no phy-config can be matched\n"); 721 return -EINVAL; 722 } 723 724 if (rphy->phy_cfg->phy_tuning) 725 rphy->phy_cfg->phy_tuning(rphy); 726 727 return 0; 728 } 729 730 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 731 { 732 struct regmap *base = get_reg_base(rphy); 733 int ret = 0; 734 735 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 736 if (rphy->phy_cfg->reg == 0x760) 737 ret = regmap_write(base, 0x76c, 0x00070004); 738 739 return ret; 740 } 741 742 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 743 { 744 struct regmap *base = get_reg_base(rphy); 745 unsigned int tmp, orig; 746 int ret; 747 748 if (soc_is_rk3308bs()) { 749 /* Enable otg/host port pre-emphasis during non-chirp phase */ 750 ret = regmap_read(base, 0, &orig); 751 if (ret) 752 return ret; 753 tmp = orig & ~GENMASK(2, 0); 754 tmp |= BIT(2) & GENMASK(2, 0); 755 ret = regmap_write(base, 0, tmp); 756 if (ret) 757 return ret; 758 759 /* Set otg port squelch trigger point configure to 100mv */ 760 ret = regmap_read(base, 0x004, &orig); 761 if (ret) 762 return ret; 763 tmp = orig & ~GENMASK(7, 5); 764 tmp |= 0x40 & GENMASK(7, 5); 765 ret = regmap_write(base, 0x004, tmp); 766 if (ret) 767 return ret; 768 769 ret = regmap_read(base, 0x008, &orig); 770 if (ret) 771 return ret; 772 tmp = orig & ~BIT(0); 773 tmp |= 0x1 & BIT(0); 774 ret = regmap_write(base, 0x008, tmp); 775 if (ret) 776 return ret; 777 778 /* Enable host port pre-emphasis during non-chirp phase */ 779 ret = regmap_read(base, 0x400, &orig); 780 if (ret) 781 return ret; 782 tmp = orig & ~GENMASK(2, 0); 783 tmp |= BIT(2) & GENMASK(2, 0); 784 ret = regmap_write(base, 0x400, tmp); 785 if (ret) 786 return ret; 787 788 /* Set host port squelch trigger point configure to 100mv */ 789 ret = regmap_read(base, 0x404, &orig); 790 if (ret) 791 return ret; 792 tmp = orig & ~GENMASK(7, 5); 793 tmp |= 0x40 & GENMASK(7, 5); 794 ret = regmap_write(base, 0x404, tmp); 795 if (ret) 796 return ret; 797 798 ret = regmap_read(base, 0x408, &orig); 799 if (ret) 800 return ret; 801 tmp = orig & ~BIT(0); 802 tmp |= 0x1 & BIT(0); 803 ret = regmap_write(base, 0x408, tmp); 804 if (ret) 805 return ret; 806 } 807 808 return 0; 809 } 810 811 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 812 { 813 struct regmap *base = get_reg_base(rphy); 814 unsigned int tmp, orig; 815 int ret; 816 817 if (soc_is_px30s()) { 818 /* Enable otg/host port pre-emphasis during non-chirp phase */ 819 ret = regmap_read(base, 0x8000, &orig); 820 if (ret) 821 return ret; 822 tmp = orig & ~GENMASK(2, 0); 823 tmp |= BIT(2) & GENMASK(2, 0); 824 ret = regmap_write(base, 0x8000, tmp); 825 if (ret) 826 return ret; 827 828 /* Set otg port squelch trigger point configure to 100mv */ 829 ret = regmap_read(base, 0x8004, &orig); 830 if (ret) 831 return ret; 832 tmp = orig & ~GENMASK(7, 5); 833 tmp |= 0x40 & GENMASK(7, 5); 834 ret = regmap_write(base, 0x8004, tmp); 835 if (ret) 836 return ret; 837 838 ret = regmap_read(base, 0x8008, &orig); 839 if (ret) 840 return ret; 841 tmp = orig & ~BIT(0); 842 tmp |= 0x1 & BIT(0); 843 ret = regmap_write(base, 0x8008, tmp); 844 if (ret) 845 return ret; 846 847 /* Enable host port pre-emphasis during non-chirp phase */ 848 ret = regmap_read(base, 0x8400, &orig); 849 if (ret) 850 return ret; 851 tmp = orig & ~GENMASK(2, 0); 852 tmp |= BIT(2) & GENMASK(2, 0); 853 ret = regmap_write(base, 0x8400, tmp); 854 if (ret) 855 return ret; 856 857 /* Set host port squelch trigger point configure to 100mv */ 858 ret = regmap_read(base, 0x8404, &orig); 859 if (ret) 860 return ret; 861 tmp = orig & ~GENMASK(7, 5); 862 tmp |= 0x40 & GENMASK(7, 5); 863 ret = regmap_write(base, 0x8404, tmp); 864 if (ret) 865 return ret; 866 867 ret = regmap_read(base, 0x8408, &orig); 868 if (ret) 869 return ret; 870 tmp = orig & ~BIT(0); 871 tmp |= 0x1 & BIT(0); 872 ret = regmap_write(base, 0x8408, tmp); 873 if (ret) 874 return ret; 875 } 876 877 return 0; 878 } 879 880 static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) 881 { 882 /* Set HS disconnect detect mode to single ended detect mode */ 883 phy_set_bits(rphy->phy_base + 0x70, BIT(2)); 884 885 return 0; 886 } 887 888 static int rk3506_usb2phy_tuning(struct rockchip_usb2phy *rphy) 889 { 890 /* Turn off otg0 port differential receiver in suspend mode */ 891 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 892 893 /* Turn off otg1 port differential receiver in suspend mode */ 894 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 895 896 /* Set otg0 port HS eye height to 425mv(default is 450mv) */ 897 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x05 << 4)); 898 899 /* Set otg1 port HS eye height to 425mv(default is 450mv) */ 900 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x05 << 4)); 901 902 /* Choose the Tx fs/ls data as linestate from TX driver for otg0 port */ 903 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 904 905 /* Choose the Tx fs/ls data as linestate from TX driver for otg1 port */ 906 phy_update_bits(rphy->phy_base + 0x494, GENMASK(6, 3), (0x03 << 3)); 907 908 return 0; 909 } 910 911 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy) 912 { 913 if (IS_ERR(rphy->phy_base)) { 914 return PTR_ERR(rphy->phy_base); 915 } 916 917 /* Turn off otg port differential receiver in suspend mode */ 918 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 919 920 /* Turn off host port differential receiver in suspend mode */ 921 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 922 923 /* Set otg port HS eye height to 400mv(default is 450mv) */ 924 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4)); 925 926 /* Set host port HS eye height to 400mv(default is 450mv) */ 927 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4)); 928 929 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */ 930 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 931 932 /* Turn on output clk of phy*/ 933 phy_update_bits(rphy->phy_base + 0x41c, GENMASK(7, 2), (0x27 << 2)); 934 935 return 0; 936 } 937 938 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy) 939 { 940 if (IS_ERR(rphy->phy_base)) { 941 return PTR_ERR(rphy->phy_base); 942 } 943 944 /* Turn off differential receiver by default to save power */ 945 phy_clear_bits(rphy->phy_base + 0x0030, BIT(2)); 946 phy_clear_bits(rphy->phy_base + 0x0430, BIT(2)); 947 948 /* Enable pre-emphasis during non-chirp phase */ 949 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); 950 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); 951 952 /* Set HS eye height to 425mv(default is 400mv) */ 953 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); 954 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); 955 956 return 0; 957 } 958 959 static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy) 960 { 961 struct regmap *base = get_reg_base(rphy); 962 int ret; 963 964 if (rphy->phy_cfg->reg == 0x0) { 965 /* Deassert SIDDQ to power on analog block */ 966 ret = regmap_write(base, 0x0010, GENMASK(29, 29) | 0x0000); 967 if (ret) 968 return ret; 969 970 /* Do reset after exit IDDQ mode */ 971 ret = rockchip_usb2phy_reset(rphy); 972 if (ret) 973 return ret; 974 975 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 976 ret = regmap_write(base, 0x000c, GENMASK(27, 24) | 0x0900); 977 if (ret) 978 return ret; 979 980 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 981 ret = regmap_write(base, 0x0010, GENMASK(20, 19) | 0x0010); 982 if (ret) 983 return ret; 984 } else if (rphy->phy_cfg->reg == 0x2000) { 985 /* Deassert SIDDQ to power on analog block */ 986 ret = regmap_write(base, 0x2010, GENMASK(29, 29) | 0x0000); 987 if (ret) 988 return ret; 989 990 /* Do reset after exit IDDQ mode */ 991 ret = rockchip_usb2phy_reset(rphy); 992 if (ret) 993 return ret; 994 995 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 996 ret = regmap_write(base, 0x200c, GENMASK(27, 24) | 0x0900); 997 if (ret) 998 return ret; 999 1000 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1001 ret = regmap_write(base, 0x2010, GENMASK(20, 19) | 0x0010); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 return 0; 1007 } 1008 1009 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 1010 { 1011 struct regmap *base = get_reg_base(rphy); 1012 int ret; 1013 1014 /* Deassert SIDDQ to power on analog block */ 1015 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 1016 if (ret) 1017 return ret; 1018 1019 /* Do reset after exit IDDQ mode */ 1020 ret = rockchip_usb2phy_reset(rphy); 1021 if (ret) 1022 return ret; 1023 1024 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 1025 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 1026 if (ret) 1027 return ret; 1028 1029 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1030 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 1031 if (ret) 1032 return ret; 1033 1034 return 0; 1035 } 1036 1037 static struct phy_ops rockchip_usb2phy_ops = { 1038 .init = rockchip_usb2phy_init, 1039 .exit = rockchip_usb2phy_exit, 1040 .power_on = rockchip_usb2phy_power_on, 1041 .power_off = rockchip_usb2phy_power_off, 1042 .of_xlate = rockchip_usb2phy_of_xlate, 1043 }; 1044 1045 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 1046 { 1047 .reg = 0x100, 1048 .num_ports = 2, 1049 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1050 .port_cfgs = { 1051 [USB2PHY_PORT_OTG] = { 1052 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1053 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1054 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1055 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1056 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1057 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1058 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1059 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1060 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1061 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1062 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1063 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1064 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1065 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1066 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1067 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1068 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1069 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1070 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1071 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1072 }, 1073 [USB2PHY_PORT_HOST] = { 1074 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1075 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1076 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1077 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1078 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1079 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1080 } 1081 }, 1082 .chg_det = { 1083 .opmode = { 0x0100, 3, 0, 5, 1 }, 1084 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1085 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1086 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1087 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1088 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1089 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1090 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1091 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1092 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1093 }, 1094 }, 1095 { /* sentinel */ } 1096 }; 1097 1098 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = { 1099 { 1100 .reg = 0x17c, 1101 .num_ports = 2, 1102 .clkout_ctl = { 0x017c, 11, 11, 1, 0 }, 1103 .port_cfgs = { 1104 [USB2PHY_PORT_OTG] = { 1105 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1106 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1107 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1108 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1109 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1110 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1111 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1112 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1113 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1114 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1115 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1116 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1117 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1118 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1119 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1120 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1121 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1122 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1123 }, 1124 [USB2PHY_PORT_HOST] = { 1125 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1126 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1127 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1128 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1129 } 1130 }, 1131 }, 1132 { /* sentinel */ } 1133 }; 1134 1135 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 1136 { 1137 .reg = 0x17c, 1138 .num_ports = 2, 1139 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 1140 .port_cfgs = { 1141 [USB2PHY_PORT_OTG] = { 1142 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1143 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1144 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1145 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1146 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1147 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1148 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1149 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1150 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1151 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1152 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1153 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1154 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1155 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1156 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1157 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1158 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1159 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1160 }, 1161 [USB2PHY_PORT_HOST] = { 1162 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1163 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1164 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1165 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1166 } 1167 }, 1168 .chg_det = { 1169 .opmode = { 0x017c, 3, 0, 5, 1 }, 1170 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 1171 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 1172 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 1173 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 1174 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 1175 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 1176 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 1177 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 1178 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 1179 }, 1180 }, 1181 { /* sentinel */ } 1182 }; 1183 1184 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 1185 { 1186 .reg = 0x760, 1187 .num_ports = 2, 1188 .phy_tuning = rk322x_usb2phy_tuning, 1189 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1190 .port_cfgs = { 1191 [USB2PHY_PORT_OTG] = { 1192 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 1193 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1194 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1195 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1196 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 1197 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 1198 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 1199 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 1200 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 1201 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 1202 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 1203 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 1204 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1205 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1206 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1207 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1208 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 1209 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1210 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 1211 }, 1212 [USB2PHY_PORT_HOST] = { 1213 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 1214 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1215 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1216 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1217 } 1218 }, 1219 .chg_det = { 1220 .opmode = { 0x0760, 3, 0, 5, 1 }, 1221 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1222 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1223 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1224 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1225 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1226 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1227 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1228 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1229 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1230 }, 1231 }, 1232 { 1233 .reg = 0x800, 1234 .num_ports = 2, 1235 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1236 .port_cfgs = { 1237 [USB2PHY_PORT_OTG] = { 1238 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1239 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1240 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1241 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1242 }, 1243 [USB2PHY_PORT_HOST] = { 1244 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1245 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1246 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1247 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1248 } 1249 }, 1250 }, 1251 { /* sentinel */ } 1252 }; 1253 1254 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1255 { 1256 .reg = 0x100, 1257 .num_ports = 2, 1258 .phy_tuning = rk3308_usb2phy_tuning, 1259 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1260 .port_cfgs = { 1261 [USB2PHY_PORT_OTG] = { 1262 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1263 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1264 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1265 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1266 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1267 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1268 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1269 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1270 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1271 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1272 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1273 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1274 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1275 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1276 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1277 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1278 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1279 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1280 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1281 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1282 }, 1283 [USB2PHY_PORT_HOST] = { 1284 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1285 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1286 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1287 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1288 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1289 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1290 } 1291 }, 1292 .chg_det = { 1293 .opmode = { 0x0100, 3, 0, 5, 1 }, 1294 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1295 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1296 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1297 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1298 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1299 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1300 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1301 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1302 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1303 }, 1304 }, 1305 { /* sentinel */ } 1306 }; 1307 1308 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1309 { 1310 .reg = 0x100, 1311 .num_ports = 2, 1312 .phy_tuning = rk3328_usb2phy_tuning, 1313 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1314 .port_cfgs = { 1315 [USB2PHY_PORT_OTG] = { 1316 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1317 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1318 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1319 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1320 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1321 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1322 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1323 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1324 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1325 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1326 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1327 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1328 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1329 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1330 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1331 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1332 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1333 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1334 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1335 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1336 }, 1337 [USB2PHY_PORT_HOST] = { 1338 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1339 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1340 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1341 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1342 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1343 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1344 } 1345 }, 1346 .chg_det = { 1347 .opmode = { 0x0100, 3, 0, 5, 1 }, 1348 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1349 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1350 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1351 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1352 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1353 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1354 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1355 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1356 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1357 }, 1358 }, 1359 { /* sentinel */ } 1360 }; 1361 1362 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1363 { 1364 .reg = 0x700, 1365 .num_ports = 2, 1366 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1367 .port_cfgs = { 1368 [USB2PHY_PORT_OTG] = { 1369 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1370 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1371 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1372 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1373 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1374 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1375 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1376 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1377 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1378 }, 1379 [USB2PHY_PORT_HOST] = { 1380 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1381 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1382 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1383 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1384 } 1385 }, 1386 .chg_det = { 1387 .opmode = { 0x0700, 3, 0, 5, 1 }, 1388 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1389 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1390 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1391 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1392 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1393 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1394 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1395 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1396 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1397 }, 1398 }, 1399 { /* sentinel */ } 1400 }; 1401 1402 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1403 { 1404 .reg = 0xe450, 1405 .num_ports = 2, 1406 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1407 .port_cfgs = { 1408 [USB2PHY_PORT_OTG] = { 1409 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1410 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1411 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1412 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1413 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1414 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1415 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1416 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1417 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1418 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1419 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1420 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1421 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1422 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1423 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1424 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1425 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1426 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1427 }, 1428 [USB2PHY_PORT_HOST] = { 1429 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1430 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1431 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1432 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1433 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1434 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1435 } 1436 }, 1437 .chg_det = { 1438 .opmode = { 0xe454, 3, 0, 5, 1 }, 1439 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1440 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1441 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1442 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1443 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1444 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1445 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1446 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1447 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1448 }, 1449 }, 1450 { 1451 .reg = 0xe460, 1452 .num_ports = 2, 1453 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1454 .port_cfgs = { 1455 [USB2PHY_PORT_OTG] = { 1456 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1457 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1458 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1459 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1460 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1461 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1462 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1463 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1464 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1465 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1466 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1467 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1468 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1469 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1470 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1471 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1472 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1473 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1474 }, 1475 [USB2PHY_PORT_HOST] = { 1476 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1477 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1478 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1479 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1480 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1481 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1482 } 1483 }, 1484 .chg_det = { 1485 .opmode = { 0xe464, 3, 0, 5, 1 }, 1486 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1487 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1488 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1489 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1490 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1491 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1492 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1493 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1494 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1495 }, 1496 }, 1497 { /* sentinel */ } 1498 }; 1499 1500 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = { 1501 { 1502 .reg = 0xff3e0000, 1503 .num_ports = 1, 1504 .phy_tuning = rv1106_usb2phy_tuning, 1505 .clkout_ctl = { 0x0058, 4, 4, 1, 0 }, 1506 .port_cfgs = { 1507 [USB2PHY_PORT_OTG] = { 1508 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 }, 1509 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 }, 1510 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 }, 1511 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 }, 1512 .iddig_output = { 0x0050, 10, 10, 0, 1 }, 1513 .iddig_en = { 0x0050, 9, 9, 0, 1 }, 1514 .idfall_det_en = { 0x0100, 5, 5, 0, 1 }, 1515 .idfall_det_st = { 0x0104, 5, 5, 0, 1 }, 1516 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 }, 1517 .idrise_det_en = { 0x0100, 4, 4, 0, 1 }, 1518 .idrise_det_st = { 0x0104, 4, 4, 0, 1 }, 1519 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 }, 1520 .ls_det_en = { 0x0100, 0, 0, 0, 1 }, 1521 .ls_det_st = { 0x0104, 0, 0, 0, 1 }, 1522 .ls_det_clr = { 0x0108, 0, 0, 0, 1 }, 1523 .utmi_avalid = { 0x0060, 10, 10, 0, 1 }, 1524 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 }, 1525 .utmi_iddig = { 0x0060, 6, 6, 0, 1 }, 1526 .utmi_ls = { 0x0060, 5, 4, 0, 1 }, 1527 }, 1528 }, 1529 .chg_det = { 1530 .opmode = { 0x0050, 3, 0, 5, 1 }, 1531 .cp_det = { 0x0060, 13, 13, 0, 1 }, 1532 .dcp_det = { 0x0060, 12, 12, 0, 1 }, 1533 .dp_det = { 0x0060, 14, 14, 0, 1 }, 1534 .idm_sink_en = { 0x0058, 8, 8, 0, 1 }, 1535 .idp_sink_en = { 0x0058, 7, 7, 0, 1 }, 1536 .idp_src_en = { 0x0058, 9, 9, 0, 1 }, 1537 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 }, 1538 .vdm_src_en = { 0x0058, 12, 12, 0, 1 }, 1539 .vdp_src_en = { 0x0058, 11, 11, 0, 1 }, 1540 }, 1541 }, 1542 { /* sentinel */ } 1543 }; 1544 1545 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1546 { 1547 .reg = 0x100, 1548 .num_ports = 2, 1549 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1550 .port_cfgs = { 1551 [USB2PHY_PORT_OTG] = { 1552 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1553 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1554 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1555 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1556 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1557 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1558 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1559 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1560 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1561 }, 1562 [USB2PHY_PORT_HOST] = { 1563 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1564 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1565 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1566 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1567 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1568 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1569 } 1570 }, 1571 .chg_det = { 1572 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1573 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1574 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1575 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1576 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1577 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1578 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1579 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1580 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1581 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1582 }, 1583 }, 1584 { /* sentinel */ } 1585 }; 1586 1587 static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { 1588 { 1589 .reg = 0xff2b0000, 1590 .num_ports = 2, 1591 .phy_tuning = rk3506_usb2phy_tuning, 1592 .port_cfgs = { 1593 [USB2PHY_PORT_OTG] = { 1594 .phy_sus = { 0x0060, 8, 0, 0, 0x1d1 }, 1595 .bvalid_det_en = { 0x0150, 2, 2, 0, 1 }, 1596 .bvalid_det_st = { 0x0154, 2, 2, 0, 1 }, 1597 .bvalid_det_clr = { 0x0158, 2, 2, 0, 1 }, 1598 .iddig_output = { 0x0060, 10, 10, 0, 1 }, 1599 .iddig_en = { 0x0060, 9, 9, 0, 1 }, 1600 .idfall_det_en = { 0x0150, 5, 5, 0, 1 }, 1601 .idfall_det_st = { 0x0154, 5, 5, 0, 1 }, 1602 .idfall_det_clr = { 0x0158, 5, 5, 0, 1 }, 1603 .idrise_det_en = { 0x0150, 4, 4, 0, 1 }, 1604 .idrise_det_st = { 0x0154, 4, 4, 0, 1 }, 1605 .idrise_det_clr = { 0x0158, 4, 4, 0, 1 }, 1606 .ls_det_en = { 0x0150, 0, 0, 0, 1 }, 1607 .ls_det_st = { 0x0154, 0, 0, 0, 1 }, 1608 .ls_det_clr = { 0x0158, 0, 0, 0, 1 }, 1609 .utmi_avalid = { 0x0118, 1, 1, 0, 1 }, 1610 .utmi_bvalid = { 0x0118, 0, 0, 0, 1 }, 1611 .utmi_iddig = { 0x0118, 6, 6, 0, 1 }, 1612 .utmi_ls = { 0x0118, 5, 4, 0, 1 }, 1613 }, 1614 [USB2PHY_PORT_HOST] = { 1615 .phy_sus = { 0x0070, 8, 0, 0x1d2, 0x1d1 }, 1616 .ls_det_en = { 0x0170, 0, 0, 0, 1 }, 1617 .ls_det_st = { 0x0174, 0, 0, 0, 1 }, 1618 .ls_det_clr = { 0x0178, 0, 0, 0, 1 }, 1619 .utmi_ls = { 0x0118, 13, 12, 0, 1 }, 1620 .utmi_hstdet = { 0x0118, 15, 15, 0, 1 } 1621 } 1622 }, 1623 .chg_det = { 1624 .opmode = { 0x0060, 3, 0, 5, 1 }, 1625 .cp_det = { 0x0118, 19, 19, 0, 1 }, 1626 .dcp_det = { 0x0118, 18, 18, 0, 1 }, 1627 .dp_det = { 0x0118, 20, 20, 0, 1 }, 1628 .idm_sink_en = { 0x006c, 1, 1, 0, 1 }, 1629 .idp_sink_en = { 0x006c, 0, 0, 0, 1 }, 1630 .idp_src_en = { 0x006c, 2, 2, 0, 1 }, 1631 .rdm_pdwn_en = { 0x006c, 3, 3, 0, 1 }, 1632 .vdm_src_en = { 0x006c, 5, 5, 0, 1 }, 1633 .vdp_src_en = { 0x006c, 4, 4, 0, 1 }, 1634 }, 1635 } 1636 }; 1637 1638 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1639 { 1640 .reg = 0xffdf0000, 1641 .num_ports = 2, 1642 .phy_tuning = rk3528_usb2phy_tuning, 1643 .port_cfgs = { 1644 [USB2PHY_PORT_OTG] = { 1645 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1646 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1647 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1648 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1649 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1650 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1651 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1652 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1653 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1654 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1655 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1656 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1657 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1658 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1659 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1660 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1661 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1662 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1663 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1664 }, 1665 [USB2PHY_PORT_HOST] = { 1666 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1667 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1668 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1669 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1670 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1671 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1672 } 1673 }, 1674 .chg_det = { 1675 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1676 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1677 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1678 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1679 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1680 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1681 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1682 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1683 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1684 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1685 }, 1686 } 1687 }; 1688 1689 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { 1690 { 1691 .reg = 0xff740000, 1692 .num_ports = 2, 1693 .phy_tuning = rk3562_usb2phy_tuning, 1694 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1695 .port_cfgs = { 1696 [USB2PHY_PORT_OTG] = { 1697 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1698 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1699 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1700 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1701 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1702 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1703 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1704 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1705 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1706 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1707 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1708 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1709 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1710 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1711 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1712 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1713 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1714 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1715 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1716 }, 1717 [USB2PHY_PORT_HOST] = { 1718 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, 1719 .ls_det_en = { 0x0110, 1, 1, 0, 1 }, 1720 .ls_det_st = { 0x0114, 1, 1, 0, 1 }, 1721 .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, 1722 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1723 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1724 } 1725 }, 1726 .chg_det = { 1727 .opmode = { 0x0100, 3, 0, 5, 1 }, 1728 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1729 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1730 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1731 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1732 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1733 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1734 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1735 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1736 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1737 }, 1738 }, 1739 { /* sentinel */ } 1740 }; 1741 1742 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1743 { 1744 .reg = 0xfe8a0000, 1745 .num_ports = 2, 1746 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1747 .port_cfgs = { 1748 [USB2PHY_PORT_OTG] = { 1749 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1750 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1751 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1752 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1753 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1754 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1755 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1756 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1757 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1758 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1759 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1760 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1761 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1762 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1763 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1764 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1765 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1766 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1767 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1768 }, 1769 [USB2PHY_PORT_HOST] = { 1770 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1771 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1772 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1773 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1774 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1775 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1776 } 1777 }, 1778 .chg_det = { 1779 .opmode = { 0x0000, 3, 0, 5, 1 }, 1780 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1781 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1782 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1783 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1784 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1785 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1786 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1787 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1788 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1789 }, 1790 }, 1791 { 1792 .reg = 0xfe8b0000, 1793 .num_ports = 2, 1794 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1795 .port_cfgs = { 1796 [USB2PHY_PORT_OTG] = { 1797 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1798 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1799 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1800 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1801 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1802 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1803 }, 1804 [USB2PHY_PORT_HOST] = { 1805 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1806 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1807 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1808 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1809 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1810 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1811 } 1812 }, 1813 }, 1814 { /* sentinel */ } 1815 }; 1816 1817 static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { 1818 { 1819 .reg = 0x0000, 1820 .num_ports = 1, 1821 .phy_tuning = rk3576_usb2phy_tuning, 1822 .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, 1823 .port_cfgs = { 1824 [USB2PHY_PORT_OTG] = { 1825 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, 1826 .ls_det_en = { 0x00c0, 0, 0, 0, 1 }, 1827 .ls_det_st = { 0x00c4, 0, 0, 0, 1 }, 1828 .ls_det_clr = { 0x00c8, 0, 0, 0, 1 }, 1829 .utmi_avalid = { 0x0080, 1, 1, 0, 1 }, 1830 .utmi_bvalid = { 0x0080, 0, 0, 0, 1 }, 1831 .utmi_iddig = { 0x0080, 6, 6, 0, 1 }, 1832 .utmi_ls = { 0x0080, 5, 4, 0, 1 }, 1833 } 1834 }, 1835 .chg_det = { 1836 .opmode = { 0x0000, 8, 0, 0x055, 0x001 }, 1837 .cp_det = { 0x0080, 8, 8, 0, 1 }, 1838 .dcp_det = { 0x0080, 8, 8, 0, 1 }, 1839 .dp_det = { 0x0080, 9, 9, 1, 0 }, 1840 .idm_sink_en = { 0x0010, 5, 5, 1, 0 }, 1841 .idp_sink_en = { 0x0010, 5, 5, 0, 1 }, 1842 .idp_src_en = { 0x0010, 14, 14, 0, 1 }, 1843 .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 }, 1844 .vdm_src_en = { 0x0010, 7, 6, 0, 3 }, 1845 .vdp_src_en = { 0x0010, 7, 6, 0, 3 }, 1846 }, 1847 }, 1848 { 1849 .reg = 0x2000, 1850 .num_ports = 1, 1851 .phy_tuning = rk3576_usb2phy_tuning, 1852 .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, 1853 .port_cfgs = { 1854 [USB2PHY_PORT_OTG] = { 1855 .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 }, 1856 .ls_det_en = { 0x20c0, 0, 0, 0, 1 }, 1857 .ls_det_st = { 0x20c4, 0, 0, 0, 1 }, 1858 .ls_det_clr = { 0x20c8, 0, 0, 0, 1 }, 1859 .utmi_avalid = { 0x2080, 1, 1, 0, 1 }, 1860 .utmi_bvalid = { 0x2080, 0, 0, 0, 1 }, 1861 .utmi_iddig = { 0x2080, 6, 6, 0, 1 }, 1862 .utmi_ls = { 0x2080, 5, 4, 0, 1 }, 1863 } 1864 }, 1865 }, 1866 { /* sentinel */ } 1867 }; 1868 1869 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1870 { 1871 .reg = 0x0000, 1872 .num_ports = 1, 1873 .phy_tuning = rk3588_usb2phy_tuning, 1874 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1875 .port_cfgs = { 1876 [USB2PHY_PORT_OTG] = { 1877 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1878 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1879 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1880 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1881 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, 1882 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, 1883 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1884 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1885 } 1886 }, 1887 .chg_det = { 1888 .opmode = { 0x0008, 2, 2, 1, 0 }, 1889 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1890 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1891 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1892 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1893 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1894 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1895 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1896 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1897 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1898 }, 1899 }, 1900 { 1901 .reg = 0x4000, 1902 .num_ports = 1, 1903 .phy_tuning = rk3588_usb2phy_tuning, 1904 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1905 .port_cfgs = { 1906 /* Select suspend control from controller */ 1907 [USB2PHY_PORT_OTG] = { 1908 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1909 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1910 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1911 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1912 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1913 } 1914 }, 1915 }, 1916 { 1917 .reg = 0x8000, 1918 .num_ports = 1, 1919 .phy_tuning = rk3588_usb2phy_tuning, 1920 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1921 .port_cfgs = { 1922 [USB2PHY_PORT_HOST] = { 1923 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1924 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1925 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1926 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1927 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1928 } 1929 }, 1930 }, 1931 { 1932 .reg = 0xc000, 1933 .num_ports = 1, 1934 .phy_tuning = rk3588_usb2phy_tuning, 1935 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1936 .port_cfgs = { 1937 [USB2PHY_PORT_HOST] = { 1938 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1939 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1940 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1941 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1942 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1943 } 1944 }, 1945 }, 1946 { /* sentinel */ } 1947 }; 1948 1949 static const struct udevice_id rockchip_usb2phy_ids[] = { 1950 #ifdef CONFIG_ROCKCHIP_RK1808 1951 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1952 #endif 1953 #ifdef CONFIG_ROCKCHIP_RK3036 1954 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs }, 1955 #endif 1956 #if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126 1957 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1958 #endif 1959 #ifdef CONFIG_ROCKCHIP_RK322X 1960 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1961 #endif 1962 #ifdef CONFIG_ROCKCHIP_RK3308 1963 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1964 #endif 1965 #if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30 1966 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1967 #endif 1968 #ifdef CONFIG_ROCKCHIP_RK3368 1969 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1970 #endif 1971 #ifdef CONFIG_ROCKCHIP_RK3399 1972 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1973 #endif 1974 #ifdef CONFIG_ROCKCHIP_RK3506 1975 { .compatible = "rockchip,rk3506-usb2phy", .data = (ulong)&rk3506_phy_cfgs }, 1976 #endif 1977 #ifdef CONFIG_ROCKCHIP_RK3528 1978 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 1979 #endif 1980 #ifdef CONFIG_ROCKCHIP_RK3562 1981 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs }, 1982 #endif 1983 #ifdef CONFIG_ROCKCHIP_RK3568 1984 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1985 #endif 1986 #ifdef CONFIG_ROCKCHIP_RK3576 1987 { .compatible = "rockchip,rk3576-usb2phy", .data = (ulong)&rk3576_phy_cfgs }, 1988 #endif 1989 #ifdef CONFIG_ROCKCHIP_RK3588 1990 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1991 #endif 1992 #ifdef CONFIG_ROCKCHIP_RV1106 1993 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs }, 1994 #endif 1995 #ifdef CONFIG_ROCKCHIP_RV1108 1996 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1997 #endif 1998 { } 1999 }; 2000 2001 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 2002 .name = "rockchip_usb2phy_port", 2003 .id = UCLASS_PHY, 2004 .ops = &rockchip_usb2phy_ops, 2005 }; 2006 2007 U_BOOT_DRIVER(rockchip_usb2phy) = { 2008 .name = "rockchip_usb2phy", 2009 .id = UCLASS_PHY, 2010 .of_match = rockchip_usb2phy_ids, 2011 .probe = rockchip_usb2phy_probe, 2012 .bind = rockchip_usb2phy_bind, 2013 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 2014 }; 2015