1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_rst: phy reset control. 153 * @phy_cfg: phy register configuration, assigned by driver data. 154 */ 155 struct rockchip_usb2phy { 156 u8 dcd_retries; 157 u8 primary_retries; 158 struct regmap *grf_base; 159 struct regmap *usbgrf_base; 160 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 161 struct reset_ctl phy_rst; 162 const struct rockchip_usb2phy_cfg *phy_cfg; 163 }; 164 165 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 166 { 167 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 168 } 169 170 static inline int property_enable(struct regmap *base, 171 const struct usb2phy_reg *reg, bool en) 172 { 173 u32 val, mask, tmp; 174 175 tmp = en ? reg->enable : reg->disable; 176 mask = GENMASK(reg->bitend, reg->bitstart); 177 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 178 179 return regmap_write(base, reg->offset, val); 180 } 181 182 static inline bool property_enabled(struct regmap *base, 183 const struct usb2phy_reg *reg) 184 { 185 u32 tmp, orig; 186 u32 mask = GENMASK(reg->bitend, reg->bitstart); 187 188 regmap_read(base, reg->offset, &orig); 189 190 tmp = (orig & mask) >> reg->bitstart; 191 192 return tmp == reg->enable; 193 } 194 195 static const char *chg_to_string(enum power_supply_type chg_type) 196 { 197 switch (chg_type) { 198 case POWER_SUPPLY_TYPE_USB: 199 return "USB_SDP_CHARGER"; 200 case POWER_SUPPLY_TYPE_USB_DCP: 201 return "USB_DCP_CHARGER"; 202 case POWER_SUPPLY_TYPE_USB_CDP: 203 return "USB_CDP_CHARGER"; 204 case POWER_SUPPLY_TYPE_USB_FLOATING: 205 return "USB_FLOATING_CHARGER"; 206 default: 207 return "INVALID_CHARGER"; 208 } 209 } 210 211 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 212 bool en) 213 { 214 struct regmap *base = get_reg_base(rphy); 215 216 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 217 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 218 } 219 220 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 221 bool en) 222 { 223 struct regmap *base = get_reg_base(rphy); 224 225 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 226 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 227 } 228 229 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 230 bool en) 231 { 232 struct regmap *base = get_reg_base(rphy); 233 234 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 235 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 236 } 237 238 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 239 { 240 bool vout = false; 241 struct regmap *base = get_reg_base(rphy); 242 243 while (rphy->primary_retries--) { 244 /* voltage source on DP, probe on DM */ 245 rockchip_chg_enable_primary_det(rphy, true); 246 mdelay(CHG_PRIMARY_DET_TIME); 247 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 248 if (vout) 249 break; 250 } 251 252 rockchip_chg_enable_primary_det(rphy, false); 253 return vout; 254 } 255 256 int rockchip_chg_get_type(void) 257 { 258 const struct rockchip_usb2phy_port_cfg *port_cfg; 259 enum power_supply_type chg_type; 260 struct rockchip_usb2phy *rphy; 261 struct udevice *udev; 262 struct regmap *base; 263 bool is_dcd, vout; 264 int ret; 265 266 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 267 if (ret == -ENODEV) { 268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 269 if (ret) { 270 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 271 return ret; 272 } 273 } 274 275 rphy = dev_get_priv(udev); 276 base = get_reg_base(rphy); 277 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 278 279 /* Check USB-Vbus status first */ 280 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 281 pr_info("%s: no charger found\n", __func__); 282 return POWER_SUPPLY_TYPE_UNKNOWN; 283 } 284 285 /* Suspend USB-PHY and put the controller in non-driving mode */ 286 property_enable(base, &port_cfg->phy_sus, true); 287 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 288 289 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 290 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 291 292 /* stage 1, start DCD processing stage */ 293 rockchip_chg_enable_dcd(rphy, true); 294 295 while (rphy->dcd_retries--) { 296 mdelay(CHG_DCD_POLL_TIME); 297 298 /* get data contact detection status */ 299 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 300 301 if (is_dcd || !rphy->dcd_retries) { 302 /* 303 * stage 2, turn off DCD circuitry, then 304 * voltage source on DP, probe on DM. 305 */ 306 rockchip_chg_enable_dcd(rphy, false); 307 rockchip_chg_enable_primary_det(rphy, true); 308 break; 309 } 310 } 311 312 mdelay(CHG_PRIMARY_DET_TIME); 313 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 314 rockchip_chg_enable_primary_det(rphy, false); 315 if (vout) { 316 /* stage 3, voltage source on DM, probe on DP */ 317 rockchip_chg_enable_secondary_det(rphy, true); 318 } else { 319 if (!rphy->dcd_retries) { 320 /* floating charger found */ 321 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 322 goto out; 323 } else { 324 /* 325 * Retry some times to make sure that it's 326 * really a USB SDP charger. 327 */ 328 vout = rockchip_chg_primary_det_retry(rphy); 329 if (vout) { 330 /* stage 3, voltage source on DM, probe on DP */ 331 rockchip_chg_enable_secondary_det(rphy, true); 332 } else { 333 /* USB SDP charger found */ 334 chg_type = POWER_SUPPLY_TYPE_USB; 335 goto out; 336 } 337 } 338 } 339 340 mdelay(CHG_SECONDARY_DET_TIME); 341 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 342 /* stage 4, turn off voltage source */ 343 rockchip_chg_enable_secondary_det(rphy, false); 344 if (vout) 345 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 346 else 347 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 348 349 out: 350 /* Resume USB-PHY and put the controller in normal mode */ 351 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 352 property_enable(base, &port_cfg->phy_sus, false); 353 354 debug("charger is %s\n", chg_to_string(chg_type)); 355 356 return chg_type; 357 } 358 359 int rockchip_u2phy_vbus_detect(void) 360 { 361 int chg_type; 362 363 chg_type = rockchip_chg_get_type(); 364 365 return (chg_type == POWER_SUPPLY_TYPE_USB || 366 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 367 } 368 369 void otg_phy_init(struct dwc2_udc *dev) 370 { 371 const struct rockchip_usb2phy_port_cfg *port_cfg; 372 struct rockchip_usb2phy *rphy; 373 struct udevice *udev; 374 struct regmap *base; 375 int ret; 376 377 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 378 if (ret == -ENODEV) { 379 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 380 if (ret) { 381 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 382 return; 383 } 384 } 385 386 rphy = dev_get_priv(udev); 387 base = get_reg_base(rphy); 388 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 389 390 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 391 if(rphy->phy_cfg->clkout_ctl.disable) 392 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 393 394 /* Reset USB-PHY */ 395 property_enable(base, &port_cfg->phy_sus, true); 396 udelay(20); 397 property_enable(base, &port_cfg->phy_sus, false); 398 mdelay(2); 399 } 400 401 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 402 { 403 struct udevice *parent = phy->dev->parent; 404 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 405 const struct rockchip_usb2phy_port_cfg *port_cfg; 406 struct regmap *base = get_reg_base(rphy); 407 struct udevice *vbus = NULL; 408 bool iddig = true; 409 410 if (phy->id == USB2PHY_PORT_HOST) { 411 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 412 } else if (phy->id == USB2PHY_PORT_OTG) { 413 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 414 if (port_cfg->utmi_iddig.offset) { 415 iddig = property_enabled(base, &port_cfg->utmi_iddig); 416 if (!iddig) 417 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 418 } 419 } 420 421 return vbus; 422 } 423 424 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 425 { 426 int ret; 427 428 if (rphy->phy_rst.dev) { 429 ret = reset_assert(&rphy->phy_rst); 430 if (ret < 0) { 431 pr_err("u2phy assert reset failed: %d", ret); 432 return ret; 433 } 434 435 udelay(20); 436 437 ret = reset_deassert(&rphy->phy_rst); 438 if (ret < 0) { 439 pr_err("u2phy deassert reset failed: %d", ret); 440 return ret; 441 } 442 443 udelay(100); 444 } 445 446 return 0; 447 } 448 449 static int rockchip_usb2phy_init(struct phy *phy) 450 { 451 struct udevice *parent = phy->dev->parent; 452 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 453 const struct rockchip_usb2phy_port_cfg *port_cfg; 454 struct regmap *base = get_reg_base(rphy); 455 456 if (phy->id == USB2PHY_PORT_OTG) { 457 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 458 } else if (phy->id == USB2PHY_PORT_HOST) { 459 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 460 } else { 461 dev_err(phy->dev, "phy id %lu not support", phy->id); 462 return -EINVAL; 463 } 464 465 property_enable(base, &port_cfg->phy_sus, false); 466 467 /* waiting for the utmi_clk to become stable */ 468 udelay(2000); 469 470 return 0; 471 } 472 473 static int rockchip_usb2phy_exit(struct phy *phy) 474 { 475 struct udevice *parent = phy->dev->parent; 476 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 477 const struct rockchip_usb2phy_port_cfg *port_cfg; 478 struct regmap *base = get_reg_base(rphy); 479 480 if (phy->id == USB2PHY_PORT_OTG) { 481 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 482 } else if (phy->id == USB2PHY_PORT_HOST) { 483 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 484 } else { 485 dev_err(phy->dev, "phy id %lu not support", phy->id); 486 return -EINVAL; 487 } 488 489 property_enable(base, &port_cfg->phy_sus, true); 490 491 return 0; 492 } 493 494 static int rockchip_usb2phy_power_on(struct phy *phy) 495 { 496 struct udevice *vbus = NULL; 497 int ret; 498 499 vbus = rockchip_usb2phy_check_vbus(phy); 500 if (vbus) { 501 ret = regulator_set_enable(vbus, true); 502 if (ret) { 503 pr_err("%s: Failed to set VBus supply\n", __func__); 504 return ret; 505 } 506 } 507 508 return 0; 509 } 510 511 static int rockchip_usb2phy_power_off(struct phy *phy) 512 { 513 struct udevice *vbus = NULL; 514 int ret; 515 516 vbus = rockchip_usb2phy_check_vbus(phy); 517 if (vbus) { 518 ret = regulator_set_enable(vbus, false); 519 if (ret) { 520 pr_err("%s: Failed to set VBus supply\n", __func__); 521 return ret; 522 } 523 } 524 525 return 0; 526 } 527 528 static int rockchip_usb2phy_of_xlate(struct phy *phy, 529 struct ofnode_phandle_args *args) 530 { 531 const char *dev_name = phy->dev->name; 532 struct udevice *parent = phy->dev->parent; 533 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 534 535 if (!strcasecmp(dev_name, "host-port")) { 536 phy->id = USB2PHY_PORT_HOST; 537 device_get_supply_regulator(phy->dev, "phy-supply", 538 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 539 } else if (!strcasecmp(dev_name, "otg-port")) { 540 phy->id = USB2PHY_PORT_OTG; 541 device_get_supply_regulator(phy->dev, "phy-supply", 542 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 543 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 544 device_get_supply_regulator(phy->dev, "vbus-supply", 545 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 546 } else { 547 pr_err("%s: invalid dev name\n", __func__); 548 return -EINVAL; 549 } 550 551 return 0; 552 } 553 554 static int rockchip_usb2phy_bind(struct udevice *dev) 555 { 556 struct udevice *child; 557 ofnode subnode; 558 const char *node_name; 559 int ret; 560 561 dev_for_each_subnode(subnode, dev) { 562 if (!ofnode_valid(subnode)) { 563 debug("%s: %s subnode not found", __func__, dev->name); 564 return -ENXIO; 565 } 566 567 node_name = ofnode_get_name(subnode); 568 debug("%s: subnode %s\n", __func__, node_name); 569 570 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 571 node_name, subnode, &child); 572 if (ret) { 573 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 574 __func__, node_name); 575 return ret; 576 } 577 } 578 579 return 0; 580 } 581 582 static int rockchip_usb2phy_probe(struct udevice *dev) 583 { 584 const struct rockchip_usb2phy_cfg *phy_cfgs; 585 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 586 struct udevice *parent = dev->parent; 587 struct udevice *syscon; 588 struct resource res; 589 u32 reg, index; 590 int ret; 591 592 if (!strncmp(parent->name, "root_driver", 11) && 593 dev_read_bool(dev, "rockchip,grf")) { 594 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 595 "rockchip,grf", &syscon); 596 if (ret) { 597 dev_err(dev, "get syscon grf failed\n"); 598 return ret; 599 } 600 601 rphy->grf_base = syscon_get_regmap(syscon); 602 } else { 603 rphy->grf_base = syscon_get_regmap(parent); 604 } 605 606 if (rphy->grf_base <= 0) { 607 dev_err(dev, "get syscon grf regmap failed\n"); 608 return -EINVAL; 609 } 610 611 if (dev_read_bool(dev, "rockchip,usbgrf")) { 612 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 613 "rockchip,usbgrf", &syscon); 614 if (ret) { 615 dev_err(dev, "get syscon usbgrf failed\n"); 616 return ret; 617 } 618 619 rphy->usbgrf_base = syscon_get_regmap(syscon); 620 if (rphy->usbgrf_base <= 0) { 621 dev_err(dev, "get syscon usbgrf regmap failed\n"); 622 return -EINVAL; 623 } 624 } else { 625 rphy->usbgrf_base = NULL; 626 } 627 628 if (!strncmp(parent->name, "root_driver", 11)) { 629 ret = dev_read_resource(dev, 0, &res); 630 reg = res.start; 631 } else { 632 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 633 } 634 635 if (ret) { 636 dev_err(dev, "could not read reg\n"); 637 return -EINVAL; 638 } 639 640 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 641 if (ret) 642 dev_dbg(dev, "no u2phy reset control specified\n"); 643 644 phy_cfgs = 645 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 646 if (!phy_cfgs) { 647 dev_err(dev, "unable to get phy_cfgs\n"); 648 return -EINVAL; 649 } 650 651 /* find out a proper config which can be matched with dt. */ 652 index = 0; 653 do { 654 if (phy_cfgs[index].reg == reg) { 655 rphy->phy_cfg = &phy_cfgs[index]; 656 break; 657 } 658 ++index; 659 } while (phy_cfgs[index].reg); 660 661 if (!rphy->phy_cfg) { 662 dev_err(dev, "no phy-config can be matched\n"); 663 return -EINVAL; 664 } 665 666 if (rphy->phy_cfg->phy_tuning) 667 rphy->phy_cfg->phy_tuning(rphy); 668 669 return 0; 670 } 671 672 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 673 { 674 struct regmap *base = get_reg_base(rphy); 675 int ret = 0; 676 677 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 678 if (rphy->phy_cfg->reg == 0x760) 679 ret = regmap_write(base, 0x76c, 0x00070004); 680 681 return ret; 682 } 683 684 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 685 { 686 struct regmap *base = get_reg_base(rphy); 687 unsigned int tmp, orig; 688 int ret; 689 690 if (soc_is_rk3308bs()) { 691 /* Enable otg/host port pre-emphasis during non-chirp phase */ 692 ret = regmap_read(base, 0, &orig); 693 if (ret) 694 return ret; 695 tmp = orig & ~GENMASK(2, 0); 696 tmp |= BIT(2) & GENMASK(2, 0); 697 ret = regmap_write(base, 0, tmp); 698 if (ret) 699 return ret; 700 701 /* Set otg port squelch trigger point configure to 100mv */ 702 ret = regmap_read(base, 0x004, &orig); 703 if (ret) 704 return ret; 705 tmp = orig & ~GENMASK(7, 5); 706 tmp |= 0x40 & GENMASK(7, 5); 707 ret = regmap_write(base, 0x004, tmp); 708 if (ret) 709 return ret; 710 711 ret = regmap_read(base, 0x008, &orig); 712 if (ret) 713 return ret; 714 tmp = orig & ~BIT(0); 715 tmp |= 0x1 & BIT(0); 716 ret = regmap_write(base, 0x008, tmp); 717 if (ret) 718 return ret; 719 720 /* Enable host port pre-emphasis during non-chirp phase */ 721 ret = regmap_read(base, 0x400, &orig); 722 if (ret) 723 return ret; 724 tmp = orig & ~GENMASK(2, 0); 725 tmp |= BIT(2) & GENMASK(2, 0); 726 ret = regmap_write(base, 0x400, tmp); 727 if (ret) 728 return ret; 729 730 /* Set host port squelch trigger point configure to 100mv */ 731 ret = regmap_read(base, 0x404, &orig); 732 if (ret) 733 return ret; 734 tmp = orig & ~GENMASK(7, 5); 735 tmp |= 0x40 & GENMASK(7, 5); 736 ret = regmap_write(base, 0x404, tmp); 737 if (ret) 738 return ret; 739 740 ret = regmap_read(base, 0x408, &orig); 741 if (ret) 742 return ret; 743 tmp = orig & ~BIT(0); 744 tmp |= 0x1 & BIT(0); 745 ret = regmap_write(base, 0x408, tmp); 746 if (ret) 747 return ret; 748 } 749 750 return 0; 751 } 752 753 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 754 { 755 struct regmap *base = get_reg_base(rphy); 756 unsigned int tmp, orig; 757 int ret; 758 759 if (soc_is_px30s()) { 760 /* Enable otg/host port pre-emphasis during non-chirp phase */ 761 ret = regmap_read(base, 0x8000, &orig); 762 if (ret) 763 return ret; 764 tmp = orig & ~GENMASK(2, 0); 765 tmp |= BIT(2) & GENMASK(2, 0); 766 ret = regmap_write(base, 0x8000, tmp); 767 if (ret) 768 return ret; 769 770 /* Set otg port squelch trigger point configure to 100mv */ 771 ret = regmap_read(base, 0x8004, &orig); 772 if (ret) 773 return ret; 774 tmp = orig & ~GENMASK(7, 5); 775 tmp |= 0x40 & GENMASK(7, 5); 776 ret = regmap_write(base, 0x8004, tmp); 777 if (ret) 778 return ret; 779 780 ret = regmap_read(base, 0x8008, &orig); 781 if (ret) 782 return ret; 783 tmp = orig & ~BIT(0); 784 tmp |= 0x1 & BIT(0); 785 ret = regmap_write(base, 0x8008, tmp); 786 if (ret) 787 return ret; 788 789 /* Enable host port pre-emphasis during non-chirp phase */ 790 ret = regmap_read(base, 0x8400, &orig); 791 if (ret) 792 return ret; 793 tmp = orig & ~GENMASK(2, 0); 794 tmp |= BIT(2) & GENMASK(2, 0); 795 ret = regmap_write(base, 0x8400, tmp); 796 if (ret) 797 return ret; 798 799 /* Set host port squelch trigger point configure to 100mv */ 800 ret = regmap_read(base, 0x8404, &orig); 801 if (ret) 802 return ret; 803 tmp = orig & ~GENMASK(7, 5); 804 tmp |= 0x40 & GENMASK(7, 5); 805 ret = regmap_write(base, 0x8404, tmp); 806 if (ret) 807 return ret; 808 809 ret = regmap_read(base, 0x8408, &orig); 810 if (ret) 811 return ret; 812 tmp = orig & ~BIT(0); 813 tmp |= 0x1 & BIT(0); 814 ret = regmap_write(base, 0x8408, tmp); 815 if (ret) 816 return ret; 817 } 818 819 return 0; 820 } 821 822 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 823 { 824 struct regmap *base = get_reg_base(rphy); 825 int ret; 826 827 /* Deassert SIDDQ to power on analog block */ 828 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 829 if (ret) 830 return ret; 831 832 /* Do reset after exit IDDQ mode */ 833 ret = rockchip_usb2phy_reset(rphy); 834 if (ret) 835 return ret; 836 837 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 838 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 839 if (ret) 840 return ret; 841 842 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 843 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 844 if (ret) 845 return ret; 846 847 return 0; 848 } 849 850 static struct phy_ops rockchip_usb2phy_ops = { 851 .init = rockchip_usb2phy_init, 852 .exit = rockchip_usb2phy_exit, 853 .power_on = rockchip_usb2phy_power_on, 854 .power_off = rockchip_usb2phy_power_off, 855 .of_xlate = rockchip_usb2phy_of_xlate, 856 }; 857 858 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 859 { 860 .reg = 0x100, 861 .num_ports = 2, 862 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 863 .port_cfgs = { 864 [USB2PHY_PORT_OTG] = { 865 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 866 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 867 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 868 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 869 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 870 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 871 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 872 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 873 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 874 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 875 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 876 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 877 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 878 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 879 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 880 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 881 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 882 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 883 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 884 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 885 }, 886 [USB2PHY_PORT_HOST] = { 887 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 888 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 889 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 890 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 891 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 892 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 893 } 894 }, 895 .chg_det = { 896 .opmode = { 0x0100, 3, 0, 5, 1 }, 897 .cp_det = { 0x0120, 24, 24, 0, 1 }, 898 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 899 .dp_det = { 0x0120, 25, 25, 0, 1 }, 900 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 901 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 902 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 903 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 904 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 905 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 906 }, 907 }, 908 { /* sentinel */ } 909 }; 910 911 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 912 { 913 .reg = 0x17c, 914 .num_ports = 2, 915 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 916 .port_cfgs = { 917 [USB2PHY_PORT_OTG] = { 918 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 919 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 920 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 921 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 922 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 923 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 924 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 925 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 926 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 927 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 928 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 929 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 930 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 931 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 932 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 933 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 934 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 935 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 936 }, 937 [USB2PHY_PORT_HOST] = { 938 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 939 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 940 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 941 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 942 } 943 }, 944 .chg_det = { 945 .opmode = { 0x017c, 3, 0, 5, 1 }, 946 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 947 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 948 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 949 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 950 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 951 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 952 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 953 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 954 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 955 }, 956 }, 957 { /* sentinel */ } 958 }; 959 960 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 961 { 962 .reg = 0x760, 963 .num_ports = 2, 964 .phy_tuning = rk322x_usb2phy_tuning, 965 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 966 .port_cfgs = { 967 [USB2PHY_PORT_OTG] = { 968 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 969 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 970 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 971 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 972 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 973 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 974 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 975 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 976 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 977 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 978 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 979 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 980 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 981 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 982 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 983 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 984 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 985 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 986 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 987 }, 988 [USB2PHY_PORT_HOST] = { 989 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 990 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 991 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 992 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 993 } 994 }, 995 .chg_det = { 996 .opmode = { 0x0760, 3, 0, 5, 1 }, 997 .cp_det = { 0x0884, 4, 4, 0, 1 }, 998 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 999 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1000 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1001 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1002 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1003 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1004 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1005 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1006 }, 1007 }, 1008 { 1009 .reg = 0x800, 1010 .num_ports = 2, 1011 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1012 .port_cfgs = { 1013 [USB2PHY_PORT_OTG] = { 1014 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1015 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1016 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1017 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1018 }, 1019 [USB2PHY_PORT_HOST] = { 1020 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1021 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1022 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1023 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1024 } 1025 }, 1026 }, 1027 { /* sentinel */ } 1028 }; 1029 1030 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1031 { 1032 .reg = 0x100, 1033 .num_ports = 2, 1034 .phy_tuning = rk3308_usb2phy_tuning, 1035 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1036 .port_cfgs = { 1037 [USB2PHY_PORT_OTG] = { 1038 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1039 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1040 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1041 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1042 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1043 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1044 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1045 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1046 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1047 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1048 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1049 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1050 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1051 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1052 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1053 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1054 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1055 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1056 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1057 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1058 }, 1059 [USB2PHY_PORT_HOST] = { 1060 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1061 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1062 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1063 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1064 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1065 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1066 } 1067 }, 1068 .chg_det = { 1069 .opmode = { 0x0100, 3, 0, 5, 1 }, 1070 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1071 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1072 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1073 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1074 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1075 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1076 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1077 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1078 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1079 }, 1080 }, 1081 { /* sentinel */ } 1082 }; 1083 1084 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1085 { 1086 .reg = 0x100, 1087 .num_ports = 2, 1088 .phy_tuning = rk3328_usb2phy_tuning, 1089 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1090 .port_cfgs = { 1091 [USB2PHY_PORT_OTG] = { 1092 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1093 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1094 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1095 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1096 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1097 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1098 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1099 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1100 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1101 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1102 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1103 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1104 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1105 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1106 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1107 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1108 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1109 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1110 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1111 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1112 }, 1113 [USB2PHY_PORT_HOST] = { 1114 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1115 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1116 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1117 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1118 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1119 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1120 } 1121 }, 1122 .chg_det = { 1123 .opmode = { 0x0100, 3, 0, 5, 1 }, 1124 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1125 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1126 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1127 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1128 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1129 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1130 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1131 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1132 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1133 }, 1134 }, 1135 { /* sentinel */ } 1136 }; 1137 1138 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1139 { 1140 .reg = 0x700, 1141 .num_ports = 2, 1142 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1143 .port_cfgs = { 1144 [USB2PHY_PORT_OTG] = { 1145 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1146 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1147 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1148 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1149 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1150 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1151 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1152 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1153 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1154 }, 1155 [USB2PHY_PORT_HOST] = { 1156 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1157 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1158 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1159 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1160 } 1161 }, 1162 .chg_det = { 1163 .opmode = { 0x0700, 3, 0, 5, 1 }, 1164 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1165 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1166 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1167 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1168 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1169 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1170 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1171 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1172 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1173 }, 1174 }, 1175 { /* sentinel */ } 1176 }; 1177 1178 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1179 { 1180 .reg = 0xe450, 1181 .num_ports = 2, 1182 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1183 .port_cfgs = { 1184 [USB2PHY_PORT_OTG] = { 1185 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1186 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1187 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1188 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1189 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1190 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1191 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1192 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1193 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1194 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1195 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1196 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1197 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1198 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1199 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1200 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1201 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1202 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1203 }, 1204 [USB2PHY_PORT_HOST] = { 1205 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1206 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1207 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1208 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1209 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1210 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1211 } 1212 }, 1213 .chg_det = { 1214 .opmode = { 0xe454, 3, 0, 5, 1 }, 1215 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1216 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1217 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1218 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1219 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1220 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1221 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1222 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1223 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1224 }, 1225 }, 1226 { 1227 .reg = 0xe460, 1228 .num_ports = 2, 1229 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1230 .port_cfgs = { 1231 [USB2PHY_PORT_OTG] = { 1232 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1233 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1234 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1235 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1236 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1237 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1238 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1239 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1240 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1241 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1242 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1243 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1244 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1245 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1246 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1247 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1248 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1249 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1250 }, 1251 [USB2PHY_PORT_HOST] = { 1252 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1253 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1254 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1255 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1256 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1257 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1258 } 1259 }, 1260 .chg_det = { 1261 .opmode = { 0xe464, 3, 0, 5, 1 }, 1262 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1263 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1264 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1265 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1266 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1267 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1268 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1269 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1270 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1271 }, 1272 }, 1273 { /* sentinel */ } 1274 }; 1275 1276 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1277 { 1278 .reg = 0x100, 1279 .num_ports = 2, 1280 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1281 .port_cfgs = { 1282 [USB2PHY_PORT_OTG] = { 1283 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1284 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1285 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1286 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1287 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1288 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1289 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1290 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1291 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1292 }, 1293 [USB2PHY_PORT_HOST] = { 1294 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1295 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1296 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1297 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1298 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1299 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1300 } 1301 }, 1302 .chg_det = { 1303 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1304 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1305 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1306 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1307 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1308 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1309 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1310 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1311 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1312 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1313 }, 1314 }, 1315 { /* sentinel */ } 1316 }; 1317 1318 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1319 { 1320 .reg = 0xffdf0000, 1321 .num_ports = 2, 1322 .port_cfgs = { 1323 [USB2PHY_PORT_OTG] = { 1324 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1325 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1326 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1327 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1328 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1329 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1330 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1331 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1332 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1333 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1334 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1335 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1336 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1337 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1338 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1339 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1340 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1341 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1342 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1343 }, 1344 [USB2PHY_PORT_HOST] = { 1345 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1346 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1347 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1348 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1349 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1350 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1351 } 1352 }, 1353 .chg_det = { 1354 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1355 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1356 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1357 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1358 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1359 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1360 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1361 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1362 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1363 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1364 }, 1365 } 1366 }; 1367 1368 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1369 { 1370 .reg = 0xfe8a0000, 1371 .num_ports = 2, 1372 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1373 .port_cfgs = { 1374 [USB2PHY_PORT_OTG] = { 1375 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1376 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1377 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1378 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1379 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1380 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1381 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1382 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1383 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1384 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1385 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1386 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1387 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1388 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1389 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1390 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1391 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1392 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1393 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1394 }, 1395 [USB2PHY_PORT_HOST] = { 1396 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1397 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1398 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1399 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1400 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1401 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1402 } 1403 }, 1404 .chg_det = { 1405 .opmode = { 0x0000, 3, 0, 5, 1 }, 1406 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1407 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1408 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1409 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1410 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1411 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1412 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1413 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1414 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1415 }, 1416 }, 1417 { 1418 .reg = 0xfe8b0000, 1419 .num_ports = 2, 1420 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1421 .port_cfgs = { 1422 [USB2PHY_PORT_OTG] = { 1423 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1424 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1425 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1426 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1427 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1428 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1429 }, 1430 [USB2PHY_PORT_HOST] = { 1431 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1432 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1433 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1434 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1435 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1436 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1437 } 1438 }, 1439 }, 1440 { /* sentinel */ } 1441 }; 1442 1443 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1444 { 1445 .reg = 0x0000, 1446 .num_ports = 1, 1447 .phy_tuning = rk3588_usb2phy_tuning, 1448 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1449 .port_cfgs = { 1450 [USB2PHY_PORT_OTG] = { 1451 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1452 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1453 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1454 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1455 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1456 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1457 } 1458 }, 1459 .chg_det = { 1460 .opmode = { 0x0008, 2, 2, 1, 0 }, 1461 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1462 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1463 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1464 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1465 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1466 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1467 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1468 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1469 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1470 }, 1471 }, 1472 { 1473 .reg = 0x4000, 1474 .num_ports = 1, 1475 .phy_tuning = rk3588_usb2phy_tuning, 1476 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1477 .port_cfgs = { 1478 /* Select suspend control from controller */ 1479 [USB2PHY_PORT_OTG] = { 1480 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1481 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1482 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1483 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1484 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1485 } 1486 }, 1487 }, 1488 { 1489 .reg = 0x8000, 1490 .num_ports = 1, 1491 .phy_tuning = rk3588_usb2phy_tuning, 1492 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1493 .port_cfgs = { 1494 [USB2PHY_PORT_HOST] = { 1495 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1496 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1497 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1498 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1499 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1500 } 1501 }, 1502 }, 1503 { 1504 .reg = 0xc000, 1505 .num_ports = 1, 1506 .phy_tuning = rk3588_usb2phy_tuning, 1507 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1508 .port_cfgs = { 1509 [USB2PHY_PORT_HOST] = { 1510 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1511 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1512 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1513 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1514 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1515 } 1516 }, 1517 }, 1518 { /* sentinel */ } 1519 }; 1520 1521 static const struct udevice_id rockchip_usb2phy_ids[] = { 1522 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1523 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1524 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1525 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1526 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1527 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1528 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1529 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 1530 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1531 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1532 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1533 { } 1534 }; 1535 1536 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1537 .name = "rockchip_usb2phy_port", 1538 .id = UCLASS_PHY, 1539 .ops = &rockchip_usb2phy_ops, 1540 }; 1541 1542 U_BOOT_DRIVER(rockchip_usb2phy) = { 1543 .name = "rockchip_usb2phy", 1544 .id = UCLASS_PHY, 1545 .of_match = rockchip_usb2phy_ids, 1546 .probe = rockchip_usb2phy_probe, 1547 .bind = rockchip_usb2phy_bind, 1548 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1549 }; 1550