1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 18 #include "../usb/gadget/dwc2_udc_otg_priv.h" 19 20 #define U2PHY_BIT_WRITEABLE_SHIFT 16 21 #define CHG_DCD_MAX_RETRIES 6 22 #define CHG_PRI_MAX_RETRIES 2 23 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 24 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 25 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 26 27 struct rockchip_usb2phy; 28 29 enum power_supply_type { 30 POWER_SUPPLY_TYPE_UNKNOWN = 0, 31 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 32 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 33 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 35 }; 36 37 enum rockchip_usb2phy_port_id { 38 USB2PHY_PORT_OTG, 39 USB2PHY_PORT_HOST, 40 USB2PHY_NUM_PORTS, 41 }; 42 43 struct usb2phy_reg { 44 u32 offset; 45 u32 bitend; 46 u32 bitstart; 47 u32 disable; 48 u32 enable; 49 }; 50 51 /** 52 * struct rockchip_chg_det_reg: usb charger detect registers 53 * @cp_det: charging port detected successfully. 54 * @dcp_det: dedicated charging port detected successfully. 55 * @dp_det: assert data pin connect successfully. 56 * @idm_sink_en: open dm sink curren. 57 * @idp_sink_en: open dp sink current. 58 * @idp_src_en: open dm source current. 59 * @rdm_pdwn_en: open dm pull down resistor. 60 * @vdm_src_en: open dm voltage source. 61 * @vdp_src_en: open dp voltage source. 62 * @opmode: utmi operational mode. 63 */ 64 struct rockchip_chg_det_reg { 65 struct usb2phy_reg cp_det; 66 struct usb2phy_reg dcp_det; 67 struct usb2phy_reg dp_det; 68 struct usb2phy_reg idm_sink_en; 69 struct usb2phy_reg idp_sink_en; 70 struct usb2phy_reg idp_src_en; 71 struct usb2phy_reg rdm_pdwn_en; 72 struct usb2phy_reg vdm_src_en; 73 struct usb2phy_reg vdp_src_en; 74 struct usb2phy_reg opmode; 75 }; 76 77 /** 78 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 79 * @phy_sus: phy suspend register. 80 * @bvalid_det_en: vbus valid rise detection enable register. 81 * @bvalid_det_st: vbus valid rise detection status register. 82 * @bvalid_det_clr: vbus valid rise detection clear register. 83 * @ls_det_en: linestate detection enable register. 84 * @ls_det_st: linestate detection state register. 85 * @ls_det_clr: linestate detection clear register. 86 * @iddig_output: iddig output from grf. 87 * @iddig_en: utmi iddig select between grf and phy, 88 * 0: from phy; 1: from grf 89 * @idfall_det_en: id fall detection enable register. 90 * @idfall_det_st: id fall detection state register. 91 * @idfall_det_clr: id fall detection clear register. 92 * @idrise_det_en: id rise detection enable register. 93 * @idrise_det_st: id rise detection state register. 94 * @idrise_det_clr: id rise detection clear register. 95 * @utmi_avalid: utmi vbus avalid status register. 96 * @utmi_bvalid: utmi vbus bvalid status register. 97 * @utmi_iddig: otg port id pin status register. 98 * @utmi_ls: utmi linestate state register. 99 * @utmi_hstdet: utmi host disconnect register. 100 * @vbus_det_en: vbus detect function power down register. 101 */ 102 struct rockchip_usb2phy_port_cfg { 103 struct usb2phy_reg phy_sus; 104 struct usb2phy_reg bvalid_det_en; 105 struct usb2phy_reg bvalid_det_st; 106 struct usb2phy_reg bvalid_det_clr; 107 struct usb2phy_reg ls_det_en; 108 struct usb2phy_reg ls_det_st; 109 struct usb2phy_reg ls_det_clr; 110 struct usb2phy_reg iddig_output; 111 struct usb2phy_reg iddig_en; 112 struct usb2phy_reg idfall_det_en; 113 struct usb2phy_reg idfall_det_st; 114 struct usb2phy_reg idfall_det_clr; 115 struct usb2phy_reg idrise_det_en; 116 struct usb2phy_reg idrise_det_st; 117 struct usb2phy_reg idrise_det_clr; 118 struct usb2phy_reg utmi_avalid; 119 struct usb2phy_reg utmi_bvalid; 120 struct usb2phy_reg utmi_iddig; 121 struct usb2phy_reg utmi_ls; 122 struct usb2phy_reg utmi_hstdet; 123 struct usb2phy_reg vbus_det_en; 124 }; 125 126 /** 127 * struct rockchip_usb2phy_cfg: usb-phy configuration. 128 * @reg: the address offset of grf for usb-phy config. 129 * @num_ports: specify how many ports that the phy has. 130 * @phy_tuning: phy default parameters tunning. 131 * @clkout_ctl: keep on/turn off output clk of phy. 132 * @chg_det: charger detection registers. 133 */ 134 struct rockchip_usb2phy_cfg { 135 u32 reg; 136 u32 num_ports; 137 int (*phy_tuning)(struct rockchip_usb2phy *); 138 struct usb2phy_reg clkout_ctl; 139 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 140 const struct rockchip_chg_det_reg chg_det; 141 }; 142 143 /** 144 * @dcd_retries: The retry count used to track Data contact 145 * detection process. 146 * @primary_retries: The retry count used to do usb bc detection 147 * primary stage. 148 * @grf: General Register Files register base. 149 * @usbgrf_base : USB General Register Files register base. 150 * @phy_cfg: phy register configuration, assigned by driver data. 151 */ 152 struct rockchip_usb2phy { 153 u8 dcd_retries; 154 u8 primary_retries; 155 struct regmap *grf_base; 156 struct regmap *usbgrf_base; 157 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 158 const struct rockchip_usb2phy_cfg *phy_cfg; 159 }; 160 161 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 162 { 163 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 164 } 165 166 static inline int property_enable(struct regmap *base, 167 const struct usb2phy_reg *reg, bool en) 168 { 169 u32 val, mask, tmp; 170 171 tmp = en ? reg->enable : reg->disable; 172 mask = GENMASK(reg->bitend, reg->bitstart); 173 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 174 175 return regmap_write(base, reg->offset, val); 176 } 177 178 static inline bool property_enabled(struct regmap *base, 179 const struct usb2phy_reg *reg) 180 { 181 u32 tmp, orig; 182 u32 mask = GENMASK(reg->bitend, reg->bitstart); 183 184 regmap_read(base, reg->offset, &orig); 185 186 tmp = (orig & mask) >> reg->bitstart; 187 188 return tmp == reg->enable; 189 } 190 191 static const char *chg_to_string(enum power_supply_type chg_type) 192 { 193 switch (chg_type) { 194 case POWER_SUPPLY_TYPE_USB: 195 return "USB_SDP_CHARGER"; 196 case POWER_SUPPLY_TYPE_USB_DCP: 197 return "USB_DCP_CHARGER"; 198 case POWER_SUPPLY_TYPE_USB_CDP: 199 return "USB_CDP_CHARGER"; 200 case POWER_SUPPLY_TYPE_USB_FLOATING: 201 return "USB_FLOATING_CHARGER"; 202 default: 203 return "INVALID_CHARGER"; 204 } 205 } 206 207 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 208 bool en) 209 { 210 struct regmap *base = get_reg_base(rphy); 211 212 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 213 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 214 } 215 216 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 217 bool en) 218 { 219 struct regmap *base = get_reg_base(rphy); 220 221 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 222 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 223 } 224 225 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 226 bool en) 227 { 228 struct regmap *base = get_reg_base(rphy); 229 230 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 231 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 232 } 233 234 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 235 { 236 bool vout = false; 237 struct regmap *base = get_reg_base(rphy); 238 239 while (rphy->primary_retries--) { 240 /* voltage source on DP, probe on DM */ 241 rockchip_chg_enable_primary_det(rphy, true); 242 mdelay(CHG_PRIMARY_DET_TIME); 243 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 244 if (vout) 245 break; 246 } 247 248 rockchip_chg_enable_primary_det(rphy, false); 249 return vout; 250 } 251 252 int rockchip_chg_get_type(void) 253 { 254 const struct rockchip_usb2phy_port_cfg *port_cfg; 255 enum power_supply_type chg_type; 256 struct rockchip_usb2phy *rphy; 257 struct udevice *udev; 258 struct regmap *base; 259 bool is_dcd, vout; 260 int ret; 261 262 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 263 if (ret == -ENODEV) { 264 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 265 return ret; 266 } 267 268 rphy = dev_get_priv(udev); 269 base = get_reg_base(rphy); 270 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 271 272 /* Check USB-Vbus status first */ 273 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 274 pr_info("%s: no charger found\n", __func__); 275 return POWER_SUPPLY_TYPE_UNKNOWN; 276 } 277 278 /* Suspend USB-PHY and put the controller in non-driving mode */ 279 property_enable(base, &port_cfg->phy_sus, true); 280 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 281 282 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 283 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 284 285 /* stage 1, start DCD processing stage */ 286 rockchip_chg_enable_dcd(rphy, true); 287 288 while (rphy->dcd_retries--) { 289 mdelay(CHG_DCD_POLL_TIME); 290 291 /* get data contact detection status */ 292 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 293 294 if (is_dcd || !rphy->dcd_retries) { 295 /* 296 * stage 2, turn off DCD circuitry, then 297 * voltage source on DP, probe on DM. 298 */ 299 rockchip_chg_enable_dcd(rphy, false); 300 rockchip_chg_enable_primary_det(rphy, true); 301 break; 302 } 303 } 304 305 mdelay(CHG_PRIMARY_DET_TIME); 306 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 307 rockchip_chg_enable_primary_det(rphy, false); 308 if (vout) { 309 /* stage 3, voltage source on DM, probe on DP */ 310 rockchip_chg_enable_secondary_det(rphy, true); 311 } else { 312 if (!rphy->dcd_retries) { 313 /* floating charger found */ 314 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 315 goto out; 316 } else { 317 /* 318 * Retry some times to make sure that it's 319 * really a USB SDP charger. 320 */ 321 vout = rockchip_chg_primary_det_retry(rphy); 322 if (vout) { 323 /* stage 3, voltage source on DM, probe on DP */ 324 rockchip_chg_enable_secondary_det(rphy, true); 325 } else { 326 /* USB SDP charger found */ 327 chg_type = POWER_SUPPLY_TYPE_USB; 328 goto out; 329 } 330 } 331 } 332 333 mdelay(CHG_SECONDARY_DET_TIME); 334 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 335 /* stage 4, turn off voltage source */ 336 rockchip_chg_enable_secondary_det(rphy, false); 337 if (vout) 338 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 339 else 340 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 341 342 out: 343 /* Resume USB-PHY and put the controller in normal mode */ 344 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 345 property_enable(base, &port_cfg->phy_sus, false); 346 347 debug("charger is %s\n", chg_to_string(chg_type)); 348 349 return chg_type; 350 } 351 352 int rockchip_u2phy_vbus_detect(void) 353 { 354 int chg_type; 355 356 chg_type = rockchip_chg_get_type(); 357 358 return (chg_type == POWER_SUPPLY_TYPE_USB || 359 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 360 } 361 362 void otg_phy_init(struct dwc2_udc *dev) 363 { 364 const struct rockchip_usb2phy_port_cfg *port_cfg; 365 struct rockchip_usb2phy *rphy; 366 struct udevice *udev; 367 struct regmap *base; 368 int ret; 369 370 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 371 if (ret == -ENODEV) { 372 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 373 return; 374 } 375 376 rphy = dev_get_priv(udev); 377 base = get_reg_base(rphy); 378 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 379 380 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 381 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 382 383 /* Reset USB-PHY */ 384 property_enable(base, &port_cfg->phy_sus, true); 385 udelay(20); 386 property_enable(base, &port_cfg->phy_sus, false); 387 mdelay(2); 388 } 389 390 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 391 { 392 struct udevice *parent = phy->dev->parent; 393 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 394 const struct rockchip_usb2phy_port_cfg *port_cfg; 395 struct regmap *base = get_reg_base(rphy); 396 struct udevice *vbus = NULL; 397 bool iddig = true; 398 399 if (phy->id == USB2PHY_PORT_HOST) { 400 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 401 } else if (phy->id == USB2PHY_PORT_OTG) { 402 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 403 if (port_cfg->utmi_iddig.offset) { 404 iddig = property_enabled(base, &port_cfg->utmi_iddig); 405 if (!iddig) 406 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 407 } 408 } 409 410 return vbus; 411 } 412 413 static int rockchip_usb2phy_init(struct phy *phy) 414 { 415 struct udevice *parent = phy->dev->parent; 416 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 417 const struct rockchip_usb2phy_port_cfg *port_cfg; 418 struct regmap *base = get_reg_base(rphy); 419 420 if (phy->id == USB2PHY_PORT_OTG) { 421 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 422 } else if (phy->id == USB2PHY_PORT_HOST) { 423 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 424 } else { 425 dev_err(phy->dev, "phy id %lu not support", phy->id); 426 return -EINVAL; 427 } 428 429 property_enable(base, &port_cfg->phy_sus, false); 430 431 /* waiting for the utmi_clk to become stable */ 432 udelay(2000); 433 434 return 0; 435 } 436 437 static int rockchip_usb2phy_exit(struct phy *phy) 438 { 439 struct udevice *parent = phy->dev->parent; 440 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 441 const struct rockchip_usb2phy_port_cfg *port_cfg; 442 struct regmap *base = get_reg_base(rphy); 443 444 if (phy->id == USB2PHY_PORT_OTG) { 445 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 446 } else if (phy->id == USB2PHY_PORT_HOST) { 447 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 448 } else { 449 dev_err(phy->dev, "phy id %lu not support", phy->id); 450 return -EINVAL; 451 } 452 453 property_enable(base, &port_cfg->phy_sus, true); 454 455 return 0; 456 } 457 458 static int rockchip_usb2phy_power_on(struct phy *phy) 459 { 460 struct udevice *vbus = NULL; 461 int ret; 462 463 vbus = rockchip_usb2phy_check_vbus(phy); 464 if (vbus) { 465 ret = regulator_set_enable(vbus, true); 466 if (ret) { 467 pr_err("%s: Failed to set VBus supply\n", __func__); 468 return ret; 469 } 470 } 471 472 return 0; 473 } 474 475 static int rockchip_usb2phy_power_off(struct phy *phy) 476 { 477 struct udevice *vbus = NULL; 478 int ret; 479 480 vbus = rockchip_usb2phy_check_vbus(phy); 481 if (vbus) { 482 ret = regulator_set_enable(vbus, false); 483 if (ret) { 484 pr_err("%s: Failed to set VBus supply\n", __func__); 485 return ret; 486 } 487 } 488 489 return 0; 490 } 491 492 static int rockchip_usb2phy_of_xlate(struct phy *phy, 493 struct ofnode_phandle_args *args) 494 { 495 const char *dev_name = phy->dev->name; 496 struct udevice *parent = phy->dev->parent; 497 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 498 499 if (!strcasecmp(dev_name, "host-port")) { 500 phy->id = USB2PHY_PORT_HOST; 501 device_get_supply_regulator(phy->dev, "phy-supply", 502 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 503 } else if (!strcasecmp(dev_name, "otg-port")) { 504 phy->id = USB2PHY_PORT_OTG; 505 device_get_supply_regulator(phy->dev, "phy-supply", 506 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 507 } else { 508 pr_err("%s: invalid dev name\n", __func__); 509 return -EINVAL; 510 } 511 512 return 0; 513 } 514 515 static int rockchip_usb2phy_bind(struct udevice *dev) 516 { 517 struct udevice *child; 518 ofnode subnode; 519 const char *node_name; 520 int ret; 521 522 dev_for_each_subnode(subnode, dev) { 523 if (!ofnode_valid(subnode)) { 524 debug("%s: %s subnode not found", __func__, dev->name); 525 return -ENXIO; 526 } 527 528 node_name = ofnode_get_name(subnode); 529 debug("%s: subnode %s\n", __func__, node_name); 530 531 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 532 node_name, subnode, &child); 533 if (ret) { 534 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 535 __func__, node_name); 536 return ret; 537 } 538 } 539 540 return 0; 541 } 542 543 static int rockchip_usb2phy_probe(struct udevice *dev) 544 { 545 const struct rockchip_usb2phy_cfg *phy_cfgs; 546 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 547 struct udevice *parent = dev->parent; 548 struct udevice *syscon; 549 struct resource res; 550 u32 reg, index; 551 int ret; 552 553 if (!strncmp(parent->name, "root_driver", 11) && 554 dev_read_bool(dev, "rockchip,grf")) { 555 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 556 "rockchip,grf", &syscon); 557 if (ret) { 558 dev_err(dev, "get syscon grf failed\n"); 559 return ret; 560 } 561 562 rphy->grf_base = syscon_get_regmap(syscon); 563 } else { 564 rphy->grf_base = syscon_get_regmap(parent); 565 } 566 567 if (rphy->grf_base <= 0) { 568 dev_err(dev, "get syscon grf regmap failed\n"); 569 return -EINVAL; 570 } 571 572 if (dev_read_bool(dev, "rockchip,usbgrf")) { 573 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 574 "rockchip,usbgrf", &syscon); 575 if (ret) { 576 dev_err(dev, "get syscon usbgrf failed\n"); 577 return ret; 578 } 579 580 rphy->usbgrf_base = syscon_get_regmap(syscon); 581 if (rphy->usbgrf_base <= 0) { 582 dev_err(dev, "get syscon usbgrf regmap failed\n"); 583 return -EINVAL; 584 } 585 } else { 586 rphy->usbgrf_base = NULL; 587 } 588 589 if (!strncmp(parent->name, "root_driver", 11)) { 590 ret = dev_read_resource(dev, 0, &res); 591 reg = res.start; 592 } else { 593 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 594 } 595 596 if (ret) { 597 dev_err(dev, "could not read reg\n"); 598 return -EINVAL; 599 } 600 601 phy_cfgs = 602 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 603 if (!phy_cfgs) { 604 dev_err(dev, "unable to get phy_cfgs\n"); 605 return -EINVAL; 606 } 607 608 /* find out a proper config which can be matched with dt. */ 609 index = 0; 610 while (phy_cfgs[index].reg) { 611 if (phy_cfgs[index].reg == reg) { 612 rphy->phy_cfg = &phy_cfgs[index]; 613 break; 614 } 615 ++index; 616 } 617 618 if (!rphy->phy_cfg) { 619 dev_err(dev, "no phy-config can be matched\n"); 620 return -EINVAL; 621 } 622 623 if (rphy->phy_cfg->phy_tuning) 624 rphy->phy_cfg->phy_tuning(rphy); 625 626 return 0; 627 } 628 629 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 630 { 631 struct regmap *base = get_reg_base(rphy); 632 int ret = 0; 633 634 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 635 if (rphy->phy_cfg->reg == 0x760) 636 ret = regmap_write(base, 0x76c, 0x00070004); 637 638 return ret; 639 } 640 641 static struct phy_ops rockchip_usb2phy_ops = { 642 .init = rockchip_usb2phy_init, 643 .exit = rockchip_usb2phy_exit, 644 .power_on = rockchip_usb2phy_power_on, 645 .power_off = rockchip_usb2phy_power_off, 646 .of_xlate = rockchip_usb2phy_of_xlate, 647 }; 648 649 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 650 { 651 .reg = 0x100, 652 .num_ports = 2, 653 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 654 .port_cfgs = { 655 [USB2PHY_PORT_OTG] = { 656 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 657 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 658 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 659 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 660 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 661 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 662 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 663 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 664 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 665 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 666 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 667 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 668 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 669 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 670 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 671 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 672 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 673 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 674 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 675 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 676 }, 677 [USB2PHY_PORT_HOST] = { 678 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 679 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 680 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 681 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 682 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 683 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 684 } 685 }, 686 .chg_det = { 687 .opmode = { 0x0100, 3, 0, 5, 1 }, 688 .cp_det = { 0x0120, 24, 24, 0, 1 }, 689 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 690 .dp_det = { 0x0120, 25, 25, 0, 1 }, 691 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 692 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 693 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 694 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 695 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 696 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 697 }, 698 }, 699 { /* sentinel */ } 700 }; 701 702 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 703 { 704 .reg = 0x17c, 705 .num_ports = 2, 706 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 707 .port_cfgs = { 708 [USB2PHY_PORT_OTG] = { 709 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 710 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 711 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 712 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 713 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 714 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 715 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 716 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 717 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 718 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 719 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 720 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 721 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 722 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 723 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 724 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 725 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 726 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 727 }, 728 [USB2PHY_PORT_HOST] = { 729 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 730 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 731 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 732 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 733 } 734 }, 735 .chg_det = { 736 .opmode = { 0x017c, 3, 0, 5, 1 }, 737 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 738 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 739 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 740 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 741 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 742 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 743 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 744 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 745 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 746 }, 747 }, 748 { /* sentinel */ } 749 }; 750 751 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 752 { 753 .reg = 0x760, 754 .num_ports = 2, 755 .phy_tuning = rk322x_usb2phy_tuning, 756 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 757 .port_cfgs = { 758 [USB2PHY_PORT_OTG] = { 759 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 760 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 761 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 762 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 763 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 764 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 765 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 766 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 767 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 768 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 769 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 770 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 771 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 772 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 773 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 774 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 775 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 776 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 777 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 778 }, 779 [USB2PHY_PORT_HOST] = { 780 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 781 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 782 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 783 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 784 } 785 }, 786 .chg_det = { 787 .opmode = { 0x0760, 3, 0, 5, 1 }, 788 .cp_det = { 0x0884, 4, 4, 0, 1 }, 789 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 790 .dp_det = { 0x0884, 5, 5, 0, 1 }, 791 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 792 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 793 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 794 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 795 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 796 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 797 }, 798 }, 799 { 800 .reg = 0x800, 801 .num_ports = 2, 802 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 803 .port_cfgs = { 804 [USB2PHY_PORT_OTG] = { 805 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 806 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 807 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 808 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 809 }, 810 [USB2PHY_PORT_HOST] = { 811 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 812 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 813 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 814 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 815 } 816 }, 817 }, 818 { /* sentinel */ } 819 }; 820 821 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 822 { 823 .reg = 0x100, 824 .num_ports = 2, 825 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 826 .port_cfgs = { 827 [USB2PHY_PORT_OTG] = { 828 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 829 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 830 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 831 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 832 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 833 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 834 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 835 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 836 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 837 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 838 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 839 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 840 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 841 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 842 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 843 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 844 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 845 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 846 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 847 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 848 }, 849 [USB2PHY_PORT_HOST] = { 850 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 851 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 852 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 853 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 854 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 855 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 856 } 857 }, 858 .chg_det = { 859 .opmode = { 0x0100, 3, 0, 5, 1 }, 860 .cp_det = { 0x0120, 24, 24, 0, 1 }, 861 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 862 .dp_det = { 0x0120, 25, 25, 0, 1 }, 863 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 864 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 865 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 866 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 867 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 868 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 869 }, 870 }, 871 { /* sentinel */ } 872 }; 873 874 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 875 { 876 .reg = 0x700, 877 .num_ports = 2, 878 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 879 .port_cfgs = { 880 [USB2PHY_PORT_OTG] = { 881 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 882 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 883 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 884 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 885 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 886 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 887 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 888 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 889 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 890 }, 891 [USB2PHY_PORT_HOST] = { 892 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 893 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 894 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 895 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 896 } 897 }, 898 .chg_det = { 899 .opmode = { 0x0700, 3, 0, 5, 1 }, 900 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 901 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 902 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 903 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 904 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 905 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 906 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 907 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 908 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 909 }, 910 }, 911 { /* sentinel */ } 912 }; 913 914 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 915 { 916 .reg = 0xe450, 917 .num_ports = 2, 918 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 919 .port_cfgs = { 920 [USB2PHY_PORT_OTG] = { 921 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 922 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 923 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 924 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 925 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 926 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 927 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 928 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 929 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 930 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 931 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 932 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 933 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 934 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 935 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 936 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 937 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 938 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 939 }, 940 [USB2PHY_PORT_HOST] = { 941 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 942 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 943 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 944 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 945 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 946 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 947 } 948 }, 949 .chg_det = { 950 .opmode = { 0xe454, 3, 0, 5, 1 }, 951 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 952 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 953 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 954 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 955 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 956 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 957 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 958 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 959 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 960 }, 961 }, 962 { 963 .reg = 0xe460, 964 .num_ports = 2, 965 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 966 .port_cfgs = { 967 [USB2PHY_PORT_OTG] = { 968 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 969 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 970 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 971 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 972 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 973 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 974 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 975 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 976 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 977 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 978 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 979 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 980 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 981 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 982 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 983 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 984 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 985 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 986 }, 987 [USB2PHY_PORT_HOST] = { 988 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 989 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 990 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 991 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 992 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 993 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 994 } 995 }, 996 .chg_det = { 997 .opmode = { 0xe464, 3, 0, 5, 1 }, 998 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 999 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1000 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1001 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1002 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1003 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1004 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1005 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1006 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1007 }, 1008 }, 1009 { /* sentinel */ } 1010 }; 1011 1012 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1013 { 1014 .reg = 0x100, 1015 .num_ports = 2, 1016 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1017 .port_cfgs = { 1018 [USB2PHY_PORT_OTG] = { 1019 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1020 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1021 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1022 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1023 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1024 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1025 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1026 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1027 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1028 }, 1029 [USB2PHY_PORT_HOST] = { 1030 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1031 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1032 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1033 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1034 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1035 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1036 } 1037 }, 1038 .chg_det = { 1039 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1040 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1041 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1042 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1043 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1044 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1045 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1046 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1047 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1048 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1049 }, 1050 }, 1051 { /* sentinel */ } 1052 }; 1053 1054 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1055 { 1056 .reg = 0xfe8a0000, 1057 .num_ports = 2, 1058 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1059 .port_cfgs = { 1060 [USB2PHY_PORT_OTG] = { 1061 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1062 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1063 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1064 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1065 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1066 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1067 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1068 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1069 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1070 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1071 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1072 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1073 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1074 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1075 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1076 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1077 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1078 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1079 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1080 }, 1081 [USB2PHY_PORT_HOST] = { 1082 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1083 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1084 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1085 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1086 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1087 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1088 } 1089 }, 1090 .chg_det = { 1091 .opmode = { 0x0000, 3, 0, 5, 1 }, 1092 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1093 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1094 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1095 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1096 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1097 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1098 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1099 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1100 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1101 }, 1102 }, 1103 { 1104 .reg = 0xfe8b0000, 1105 .num_ports = 2, 1106 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1107 .port_cfgs = { 1108 [USB2PHY_PORT_OTG] = { 1109 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1110 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1111 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1112 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1113 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1114 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1115 }, 1116 [USB2PHY_PORT_HOST] = { 1117 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1118 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1119 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1120 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1121 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1122 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1123 } 1124 }, 1125 }, 1126 { /* sentinel */ } 1127 }; 1128 static const struct udevice_id rockchip_usb2phy_ids[] = { 1129 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1130 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1131 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1132 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1133 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1134 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1135 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1136 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1137 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1138 { } 1139 }; 1140 1141 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1142 .name = "rockchip_usb2phy_port", 1143 .id = UCLASS_PHY, 1144 .ops = &rockchip_usb2phy_ops, 1145 }; 1146 1147 U_BOOT_DRIVER(rockchip_usb2phy) = { 1148 .name = "rockchip_usb2phy", 1149 .id = UCLASS_PHY, 1150 .of_match = rockchip_usb2phy_ids, 1151 .probe = rockchip_usb2phy_probe, 1152 .bind = rockchip_usb2phy_bind, 1153 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1154 }; 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