1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_rst: phy reset control. 153 * @phy_cfg: phy register configuration, assigned by driver data. 154 */ 155 struct rockchip_usb2phy { 156 u8 dcd_retries; 157 u8 primary_retries; 158 struct regmap *grf_base; 159 struct regmap *usbgrf_base; 160 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 161 struct reset_ctl phy_rst; 162 const struct rockchip_usb2phy_cfg *phy_cfg; 163 }; 164 165 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 166 { 167 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 168 } 169 170 static inline int property_enable(struct regmap *base, 171 const struct usb2phy_reg *reg, bool en) 172 { 173 u32 val, mask, tmp; 174 175 tmp = en ? reg->enable : reg->disable; 176 mask = GENMASK(reg->bitend, reg->bitstart); 177 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 178 179 return regmap_write(base, reg->offset, val); 180 } 181 182 static inline bool property_enabled(struct regmap *base, 183 const struct usb2phy_reg *reg) 184 { 185 u32 tmp, orig; 186 u32 mask = GENMASK(reg->bitend, reg->bitstart); 187 188 regmap_read(base, reg->offset, &orig); 189 190 tmp = (orig & mask) >> reg->bitstart; 191 192 return tmp == reg->enable; 193 } 194 195 static const char *chg_to_string(enum power_supply_type chg_type) 196 { 197 switch (chg_type) { 198 case POWER_SUPPLY_TYPE_USB: 199 return "USB_SDP_CHARGER"; 200 case POWER_SUPPLY_TYPE_USB_DCP: 201 return "USB_DCP_CHARGER"; 202 case POWER_SUPPLY_TYPE_USB_CDP: 203 return "USB_CDP_CHARGER"; 204 case POWER_SUPPLY_TYPE_USB_FLOATING: 205 return "USB_FLOATING_CHARGER"; 206 default: 207 return "INVALID_CHARGER"; 208 } 209 } 210 211 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 212 bool en) 213 { 214 struct regmap *base = get_reg_base(rphy); 215 216 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 217 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 218 } 219 220 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 221 bool en) 222 { 223 struct regmap *base = get_reg_base(rphy); 224 225 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 226 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 227 } 228 229 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 230 bool en) 231 { 232 struct regmap *base = get_reg_base(rphy); 233 234 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 235 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 236 } 237 238 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 239 { 240 bool vout = false; 241 struct regmap *base = get_reg_base(rphy); 242 243 while (rphy->primary_retries--) { 244 /* voltage source on DP, probe on DM */ 245 rockchip_chg_enable_primary_det(rphy, true); 246 mdelay(CHG_PRIMARY_DET_TIME); 247 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 248 if (vout) 249 break; 250 } 251 252 rockchip_chg_enable_primary_det(rphy, false); 253 return vout; 254 } 255 256 int rockchip_chg_get_type(void) 257 { 258 const struct rockchip_usb2phy_port_cfg *port_cfg; 259 enum power_supply_type chg_type; 260 struct rockchip_usb2phy *rphy; 261 struct udevice *udev; 262 struct regmap *base; 263 bool is_dcd, vout; 264 int ret; 265 266 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 267 if (ret == -ENODEV) { 268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 269 if (ret) { 270 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 271 return ret; 272 } 273 } 274 275 rphy = dev_get_priv(udev); 276 base = get_reg_base(rphy); 277 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 278 279 /* Check USB-Vbus status first */ 280 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 281 pr_info("%s: no charger found\n", __func__); 282 return POWER_SUPPLY_TYPE_UNKNOWN; 283 } 284 285 /* Suspend USB-PHY and put the controller in non-driving mode */ 286 property_enable(base, &port_cfg->phy_sus, true); 287 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 288 289 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 290 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 291 292 /* stage 1, start DCD processing stage */ 293 rockchip_chg_enable_dcd(rphy, true); 294 295 while (rphy->dcd_retries--) { 296 mdelay(CHG_DCD_POLL_TIME); 297 298 /* get data contact detection status */ 299 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 300 301 if (is_dcd || !rphy->dcd_retries) { 302 /* 303 * stage 2, turn off DCD circuitry, then 304 * voltage source on DP, probe on DM. 305 */ 306 rockchip_chg_enable_dcd(rphy, false); 307 rockchip_chg_enable_primary_det(rphy, true); 308 break; 309 } 310 } 311 312 mdelay(CHG_PRIMARY_DET_TIME); 313 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 314 rockchip_chg_enable_primary_det(rphy, false); 315 if (vout) { 316 /* stage 3, voltage source on DM, probe on DP */ 317 rockchip_chg_enable_secondary_det(rphy, true); 318 } else { 319 if (!rphy->dcd_retries) { 320 /* floating charger found */ 321 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 322 goto out; 323 } else { 324 /* 325 * Retry some times to make sure that it's 326 * really a USB SDP charger. 327 */ 328 vout = rockchip_chg_primary_det_retry(rphy); 329 if (vout) { 330 /* stage 3, voltage source on DM, probe on DP */ 331 rockchip_chg_enable_secondary_det(rphy, true); 332 } else { 333 /* USB SDP charger found */ 334 chg_type = POWER_SUPPLY_TYPE_USB; 335 goto out; 336 } 337 } 338 } 339 340 mdelay(CHG_SECONDARY_DET_TIME); 341 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 342 /* stage 4, turn off voltage source */ 343 rockchip_chg_enable_secondary_det(rphy, false); 344 if (vout) 345 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 346 else 347 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 348 349 out: 350 /* Resume USB-PHY and put the controller in normal mode */ 351 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 352 property_enable(base, &port_cfg->phy_sus, false); 353 354 debug("charger is %s\n", chg_to_string(chg_type)); 355 356 return chg_type; 357 } 358 359 int rockchip_u2phy_vbus_detect(void) 360 { 361 int chg_type; 362 363 chg_type = rockchip_chg_get_type(); 364 365 return (chg_type == POWER_SUPPLY_TYPE_USB || 366 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 367 } 368 369 void otg_phy_init(struct dwc2_udc *dev) 370 { 371 const struct rockchip_usb2phy_port_cfg *port_cfg; 372 struct rockchip_usb2phy *rphy; 373 struct udevice *udev; 374 struct regmap *base; 375 int ret; 376 377 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 378 if (ret == -ENODEV) { 379 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 380 if (ret) { 381 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 382 return; 383 } 384 } 385 386 rphy = dev_get_priv(udev); 387 base = get_reg_base(rphy); 388 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 389 390 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 391 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 392 393 /* Reset USB-PHY */ 394 property_enable(base, &port_cfg->phy_sus, true); 395 udelay(20); 396 property_enable(base, &port_cfg->phy_sus, false); 397 mdelay(2); 398 } 399 400 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 401 { 402 struct udevice *parent = phy->dev->parent; 403 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 404 const struct rockchip_usb2phy_port_cfg *port_cfg; 405 struct regmap *base = get_reg_base(rphy); 406 struct udevice *vbus = NULL; 407 bool iddig = true; 408 409 if (phy->id == USB2PHY_PORT_HOST) { 410 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 411 } else if (phy->id == USB2PHY_PORT_OTG) { 412 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 413 if (port_cfg->utmi_iddig.offset) { 414 iddig = property_enabled(base, &port_cfg->utmi_iddig); 415 if (!iddig) 416 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 417 } 418 } 419 420 return vbus; 421 } 422 423 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 424 { 425 int ret; 426 427 if (rphy->phy_rst.dev) { 428 ret = reset_assert(&rphy->phy_rst); 429 if (ret < 0) { 430 pr_err("u2phy assert reset failed: %d", ret); 431 return ret; 432 } 433 434 udelay(20); 435 436 ret = reset_deassert(&rphy->phy_rst); 437 if (ret < 0) { 438 pr_err("u2phy deassert reset failed: %d", ret); 439 return ret; 440 } 441 442 udelay(100); 443 } 444 445 return 0; 446 } 447 448 static int rockchip_usb2phy_init(struct phy *phy) 449 { 450 struct udevice *parent = phy->dev->parent; 451 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 452 const struct rockchip_usb2phy_port_cfg *port_cfg; 453 struct regmap *base = get_reg_base(rphy); 454 455 if (phy->id == USB2PHY_PORT_OTG) { 456 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 457 } else if (phy->id == USB2PHY_PORT_HOST) { 458 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 459 } else { 460 dev_err(phy->dev, "phy id %lu not support", phy->id); 461 return -EINVAL; 462 } 463 464 property_enable(base, &port_cfg->phy_sus, false); 465 466 /* waiting for the utmi_clk to become stable */ 467 udelay(2000); 468 469 return 0; 470 } 471 472 static int rockchip_usb2phy_exit(struct phy *phy) 473 { 474 struct udevice *parent = phy->dev->parent; 475 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 476 const struct rockchip_usb2phy_port_cfg *port_cfg; 477 struct regmap *base = get_reg_base(rphy); 478 479 if (phy->id == USB2PHY_PORT_OTG) { 480 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 481 } else if (phy->id == USB2PHY_PORT_HOST) { 482 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 483 } else { 484 dev_err(phy->dev, "phy id %lu not support", phy->id); 485 return -EINVAL; 486 } 487 488 property_enable(base, &port_cfg->phy_sus, true); 489 490 return 0; 491 } 492 493 static int rockchip_usb2phy_power_on(struct phy *phy) 494 { 495 struct udevice *vbus = NULL; 496 int ret; 497 498 vbus = rockchip_usb2phy_check_vbus(phy); 499 if (vbus) { 500 ret = regulator_set_enable(vbus, true); 501 if (ret) { 502 pr_err("%s: Failed to set VBus supply\n", __func__); 503 return ret; 504 } 505 } 506 507 return 0; 508 } 509 510 static int rockchip_usb2phy_power_off(struct phy *phy) 511 { 512 struct udevice *vbus = NULL; 513 int ret; 514 515 vbus = rockchip_usb2phy_check_vbus(phy); 516 if (vbus) { 517 ret = regulator_set_enable(vbus, false); 518 if (ret) { 519 pr_err("%s: Failed to set VBus supply\n", __func__); 520 return ret; 521 } 522 } 523 524 return 0; 525 } 526 527 static int rockchip_usb2phy_of_xlate(struct phy *phy, 528 struct ofnode_phandle_args *args) 529 { 530 const char *dev_name = phy->dev->name; 531 struct udevice *parent = phy->dev->parent; 532 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 533 534 if (!strcasecmp(dev_name, "host-port")) { 535 phy->id = USB2PHY_PORT_HOST; 536 device_get_supply_regulator(phy->dev, "phy-supply", 537 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 538 } else if (!strcasecmp(dev_name, "otg-port")) { 539 phy->id = USB2PHY_PORT_OTG; 540 device_get_supply_regulator(phy->dev, "phy-supply", 541 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 542 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 543 device_get_supply_regulator(phy->dev, "vbus-supply", 544 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 545 } else { 546 pr_err("%s: invalid dev name\n", __func__); 547 return -EINVAL; 548 } 549 550 return 0; 551 } 552 553 static int rockchip_usb2phy_bind(struct udevice *dev) 554 { 555 struct udevice *child; 556 ofnode subnode; 557 const char *node_name; 558 int ret; 559 560 dev_for_each_subnode(subnode, dev) { 561 if (!ofnode_valid(subnode)) { 562 debug("%s: %s subnode not found", __func__, dev->name); 563 return -ENXIO; 564 } 565 566 node_name = ofnode_get_name(subnode); 567 debug("%s: subnode %s\n", __func__, node_name); 568 569 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 570 node_name, subnode, &child); 571 if (ret) { 572 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 573 __func__, node_name); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static int rockchip_usb2phy_probe(struct udevice *dev) 582 { 583 const struct rockchip_usb2phy_cfg *phy_cfgs; 584 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 585 struct udevice *parent = dev->parent; 586 struct udevice *syscon; 587 struct resource res; 588 u32 reg, index; 589 int ret; 590 591 if (!strncmp(parent->name, "root_driver", 11) && 592 dev_read_bool(dev, "rockchip,grf")) { 593 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 594 "rockchip,grf", &syscon); 595 if (ret) { 596 dev_err(dev, "get syscon grf failed\n"); 597 return ret; 598 } 599 600 rphy->grf_base = syscon_get_regmap(syscon); 601 } else { 602 rphy->grf_base = syscon_get_regmap(parent); 603 } 604 605 if (rphy->grf_base <= 0) { 606 dev_err(dev, "get syscon grf regmap failed\n"); 607 return -EINVAL; 608 } 609 610 if (dev_read_bool(dev, "rockchip,usbgrf")) { 611 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 612 "rockchip,usbgrf", &syscon); 613 if (ret) { 614 dev_err(dev, "get syscon usbgrf failed\n"); 615 return ret; 616 } 617 618 rphy->usbgrf_base = syscon_get_regmap(syscon); 619 if (rphy->usbgrf_base <= 0) { 620 dev_err(dev, "get syscon usbgrf regmap failed\n"); 621 return -EINVAL; 622 } 623 } else { 624 rphy->usbgrf_base = NULL; 625 } 626 627 if (!strncmp(parent->name, "root_driver", 11)) { 628 ret = dev_read_resource(dev, 0, &res); 629 reg = res.start; 630 } else { 631 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 632 } 633 634 if (ret) { 635 dev_err(dev, "could not read reg\n"); 636 return -EINVAL; 637 } 638 639 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 640 if (ret) 641 dev_dbg(dev, "no u2phy reset control specified\n"); 642 643 phy_cfgs = 644 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 645 if (!phy_cfgs) { 646 dev_err(dev, "unable to get phy_cfgs\n"); 647 return -EINVAL; 648 } 649 650 /* find out a proper config which can be matched with dt. */ 651 index = 0; 652 do { 653 if (phy_cfgs[index].reg == reg) { 654 rphy->phy_cfg = &phy_cfgs[index]; 655 break; 656 } 657 ++index; 658 } while (phy_cfgs[index].reg); 659 660 if (!rphy->phy_cfg) { 661 dev_err(dev, "no phy-config can be matched\n"); 662 return -EINVAL; 663 } 664 665 if (rphy->phy_cfg->phy_tuning) 666 rphy->phy_cfg->phy_tuning(rphy); 667 668 return 0; 669 } 670 671 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 672 { 673 struct regmap *base = get_reg_base(rphy); 674 int ret = 0; 675 676 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 677 if (rphy->phy_cfg->reg == 0x760) 678 ret = regmap_write(base, 0x76c, 0x00070004); 679 680 return ret; 681 } 682 683 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 684 { 685 struct regmap *base = get_reg_base(rphy); 686 unsigned int tmp, orig; 687 int ret; 688 689 if (soc_is_rk3308bs()) { 690 /* Enable otg/host port pre-emphasis during non-chirp phase */ 691 ret = regmap_read(base, 0, &orig); 692 if (ret) 693 return ret; 694 tmp = orig & ~GENMASK(2, 0); 695 tmp |= BIT(2) & GENMASK(2, 0); 696 ret = regmap_write(base, 0, tmp); 697 if (ret) 698 return ret; 699 700 /* Set otg port squelch trigger point configure to 100mv */ 701 ret = regmap_read(base, 0x004, &orig); 702 if (ret) 703 return ret; 704 tmp = orig & ~GENMASK(7, 5); 705 tmp |= 0x40 & GENMASK(7, 5); 706 ret = regmap_write(base, 0x004, tmp); 707 if (ret) 708 return ret; 709 710 ret = regmap_read(base, 0x008, &orig); 711 if (ret) 712 return ret; 713 tmp = orig & ~BIT(0); 714 tmp |= 0x1 & BIT(0); 715 ret = regmap_write(base, 0x008, tmp); 716 if (ret) 717 return ret; 718 719 /* Enable host port pre-emphasis during non-chirp phase */ 720 ret = regmap_read(base, 0x400, &orig); 721 if (ret) 722 return ret; 723 tmp = orig & ~GENMASK(2, 0); 724 tmp |= BIT(2) & GENMASK(2, 0); 725 ret = regmap_write(base, 0x400, tmp); 726 if (ret) 727 return ret; 728 729 /* Set host port squelch trigger point configure to 100mv */ 730 ret = regmap_read(base, 0x404, &orig); 731 if (ret) 732 return ret; 733 tmp = orig & ~GENMASK(7, 5); 734 tmp |= 0x40 & GENMASK(7, 5); 735 ret = regmap_write(base, 0x404, tmp); 736 if (ret) 737 return ret; 738 739 ret = regmap_read(base, 0x408, &orig); 740 if (ret) 741 return ret; 742 tmp = orig & ~BIT(0); 743 tmp |= 0x1 & BIT(0); 744 ret = regmap_write(base, 0x408, tmp); 745 if (ret) 746 return ret; 747 } 748 749 return 0; 750 } 751 752 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 753 { 754 struct regmap *base = get_reg_base(rphy); 755 unsigned int tmp, orig; 756 int ret; 757 758 if (soc_is_px30s()) { 759 /* Enable otg/host port pre-emphasis during non-chirp phase */ 760 ret = regmap_read(base, 0x8000, &orig); 761 if (ret) 762 return ret; 763 tmp = orig & ~GENMASK(2, 0); 764 tmp |= BIT(2) & GENMASK(2, 0); 765 ret = regmap_write(base, 0x8000, tmp); 766 if (ret) 767 return ret; 768 769 /* Set otg port squelch trigger point configure to 100mv */ 770 ret = regmap_read(base, 0x8004, &orig); 771 if (ret) 772 return ret; 773 tmp = orig & ~GENMASK(7, 5); 774 tmp |= 0x40 & GENMASK(7, 5); 775 ret = regmap_write(base, 0x8004, tmp); 776 if (ret) 777 return ret; 778 779 ret = regmap_read(base, 0x8008, &orig); 780 if (ret) 781 return ret; 782 tmp = orig & ~BIT(0); 783 tmp |= 0x1 & BIT(0); 784 ret = regmap_write(base, 0x8008, tmp); 785 if (ret) 786 return ret; 787 788 /* Enable host port pre-emphasis during non-chirp phase */ 789 ret = regmap_read(base, 0x8400, &orig); 790 if (ret) 791 return ret; 792 tmp = orig & ~GENMASK(2, 0); 793 tmp |= BIT(2) & GENMASK(2, 0); 794 ret = regmap_write(base, 0x8400, tmp); 795 if (ret) 796 return ret; 797 798 /* Set host port squelch trigger point configure to 100mv */ 799 ret = regmap_read(base, 0x8404, &orig); 800 if (ret) 801 return ret; 802 tmp = orig & ~GENMASK(7, 5); 803 tmp |= 0x40 & GENMASK(7, 5); 804 ret = regmap_write(base, 0x8404, tmp); 805 if (ret) 806 return ret; 807 808 ret = regmap_read(base, 0x8408, &orig); 809 if (ret) 810 return ret; 811 tmp = orig & ~BIT(0); 812 tmp |= 0x1 & BIT(0); 813 ret = regmap_write(base, 0x8408, tmp); 814 if (ret) 815 return ret; 816 } 817 818 return 0; 819 } 820 821 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 822 { 823 struct regmap *base = get_reg_base(rphy); 824 int ret; 825 826 /* Deassert SIDDQ to power on analog block */ 827 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 828 if (ret) 829 return ret; 830 831 /* Do reset after exit IDDQ mode */ 832 ret = rockchip_usb2phy_reset(rphy); 833 if (ret) 834 return ret; 835 836 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 837 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 838 if (ret) 839 return ret; 840 841 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 842 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 843 if (ret) 844 return ret; 845 846 return 0; 847 } 848 849 static struct phy_ops rockchip_usb2phy_ops = { 850 .init = rockchip_usb2phy_init, 851 .exit = rockchip_usb2phy_exit, 852 .power_on = rockchip_usb2phy_power_on, 853 .power_off = rockchip_usb2phy_power_off, 854 .of_xlate = rockchip_usb2phy_of_xlate, 855 }; 856 857 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 858 { 859 .reg = 0x100, 860 .num_ports = 2, 861 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 862 .port_cfgs = { 863 [USB2PHY_PORT_OTG] = { 864 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 865 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 866 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 867 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 868 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 869 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 870 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 871 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 872 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 873 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 874 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 875 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 876 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 877 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 878 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 879 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 880 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 881 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 882 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 883 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 884 }, 885 [USB2PHY_PORT_HOST] = { 886 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 887 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 888 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 889 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 890 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 891 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 892 } 893 }, 894 .chg_det = { 895 .opmode = { 0x0100, 3, 0, 5, 1 }, 896 .cp_det = { 0x0120, 24, 24, 0, 1 }, 897 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 898 .dp_det = { 0x0120, 25, 25, 0, 1 }, 899 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 900 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 901 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 902 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 903 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 904 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 905 }, 906 }, 907 { /* sentinel */ } 908 }; 909 910 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 911 { 912 .reg = 0x17c, 913 .num_ports = 2, 914 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 915 .port_cfgs = { 916 [USB2PHY_PORT_OTG] = { 917 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 918 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 919 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 920 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 921 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 922 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 923 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 924 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 925 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 926 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 927 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 928 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 929 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 930 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 931 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 932 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 933 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 934 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 935 }, 936 [USB2PHY_PORT_HOST] = { 937 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 938 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 939 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 940 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 941 } 942 }, 943 .chg_det = { 944 .opmode = { 0x017c, 3, 0, 5, 1 }, 945 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 946 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 947 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 948 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 949 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 950 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 951 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 952 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 953 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 954 }, 955 }, 956 { /* sentinel */ } 957 }; 958 959 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 960 { 961 .reg = 0x760, 962 .num_ports = 2, 963 .phy_tuning = rk322x_usb2phy_tuning, 964 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 965 .port_cfgs = { 966 [USB2PHY_PORT_OTG] = { 967 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 968 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 969 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 970 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 971 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 972 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 973 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 974 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 975 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 976 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 977 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 978 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 979 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 980 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 981 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 982 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 983 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 984 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 985 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 986 }, 987 [USB2PHY_PORT_HOST] = { 988 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 989 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 990 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 991 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 992 } 993 }, 994 .chg_det = { 995 .opmode = { 0x0760, 3, 0, 5, 1 }, 996 .cp_det = { 0x0884, 4, 4, 0, 1 }, 997 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 998 .dp_det = { 0x0884, 5, 5, 0, 1 }, 999 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1000 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1001 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1002 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1003 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1004 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1005 }, 1006 }, 1007 { 1008 .reg = 0x800, 1009 .num_ports = 2, 1010 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1011 .port_cfgs = { 1012 [USB2PHY_PORT_OTG] = { 1013 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1014 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1015 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1016 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1017 }, 1018 [USB2PHY_PORT_HOST] = { 1019 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1020 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1021 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1022 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1023 } 1024 }, 1025 }, 1026 { /* sentinel */ } 1027 }; 1028 1029 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1030 { 1031 .reg = 0x100, 1032 .num_ports = 2, 1033 .phy_tuning = rk3308_usb2phy_tuning, 1034 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1035 .port_cfgs = { 1036 [USB2PHY_PORT_OTG] = { 1037 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1038 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1039 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1040 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1041 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1042 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1043 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1044 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1045 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1046 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1047 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1048 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1049 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1050 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1051 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1052 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1053 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1054 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1055 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1056 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1057 }, 1058 [USB2PHY_PORT_HOST] = { 1059 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1060 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1061 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1062 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1063 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1064 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1065 } 1066 }, 1067 .chg_det = { 1068 .opmode = { 0x0100, 3, 0, 5, 1 }, 1069 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1070 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1071 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1072 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1073 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1074 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1075 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1076 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1077 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1078 }, 1079 }, 1080 { /* sentinel */ } 1081 }; 1082 1083 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1084 { 1085 .reg = 0x100, 1086 .num_ports = 2, 1087 .phy_tuning = rk3328_usb2phy_tuning, 1088 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1089 .port_cfgs = { 1090 [USB2PHY_PORT_OTG] = { 1091 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1092 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1093 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1094 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1095 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1096 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1097 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1098 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1099 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1100 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1101 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1102 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1103 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1104 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1105 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1106 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1107 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1108 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1109 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1110 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1111 }, 1112 [USB2PHY_PORT_HOST] = { 1113 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1114 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1115 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1116 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1117 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1118 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1119 } 1120 }, 1121 .chg_det = { 1122 .opmode = { 0x0100, 3, 0, 5, 1 }, 1123 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1124 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1125 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1126 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1127 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1128 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1129 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1130 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1131 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1132 }, 1133 }, 1134 { /* sentinel */ } 1135 }; 1136 1137 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1138 { 1139 .reg = 0x700, 1140 .num_ports = 2, 1141 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1142 .port_cfgs = { 1143 [USB2PHY_PORT_OTG] = { 1144 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1145 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1146 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1147 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1148 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1149 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1150 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1151 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1152 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1153 }, 1154 [USB2PHY_PORT_HOST] = { 1155 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1156 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1157 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1158 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1159 } 1160 }, 1161 .chg_det = { 1162 .opmode = { 0x0700, 3, 0, 5, 1 }, 1163 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1164 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1165 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1166 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1167 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1168 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1169 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1170 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1171 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1172 }, 1173 }, 1174 { /* sentinel */ } 1175 }; 1176 1177 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1178 { 1179 .reg = 0xe450, 1180 .num_ports = 2, 1181 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1182 .port_cfgs = { 1183 [USB2PHY_PORT_OTG] = { 1184 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1185 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1186 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1187 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1188 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1189 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1190 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1191 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1192 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1193 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1194 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1195 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1196 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1197 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1198 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1199 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1200 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1201 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1202 }, 1203 [USB2PHY_PORT_HOST] = { 1204 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1205 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1206 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1207 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1208 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1209 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1210 } 1211 }, 1212 .chg_det = { 1213 .opmode = { 0xe454, 3, 0, 5, 1 }, 1214 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1215 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1216 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1217 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1218 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1219 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1220 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1221 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1222 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1223 }, 1224 }, 1225 { 1226 .reg = 0xe460, 1227 .num_ports = 2, 1228 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1229 .port_cfgs = { 1230 [USB2PHY_PORT_OTG] = { 1231 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1232 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1233 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1234 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1235 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1236 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1237 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1238 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1239 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1240 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1241 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1242 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1243 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1244 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1245 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1246 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1247 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1248 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1249 }, 1250 [USB2PHY_PORT_HOST] = { 1251 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1252 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1253 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1254 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1255 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1256 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1257 } 1258 }, 1259 .chg_det = { 1260 .opmode = { 0xe464, 3, 0, 5, 1 }, 1261 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1262 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1263 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1264 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1265 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1266 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1267 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1268 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1269 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1270 }, 1271 }, 1272 { /* sentinel */ } 1273 }; 1274 1275 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1276 { 1277 .reg = 0x100, 1278 .num_ports = 2, 1279 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1280 .port_cfgs = { 1281 [USB2PHY_PORT_OTG] = { 1282 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1283 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1284 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1285 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1286 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1287 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1288 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1289 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1290 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1291 }, 1292 [USB2PHY_PORT_HOST] = { 1293 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1294 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1295 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1296 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1297 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1298 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1299 } 1300 }, 1301 .chg_det = { 1302 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1303 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1304 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1305 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1306 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1307 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1308 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1309 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1310 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1311 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1312 }, 1313 }, 1314 { /* sentinel */ } 1315 }; 1316 1317 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1318 { 1319 .reg = 0xfe8a0000, 1320 .num_ports = 2, 1321 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1322 .port_cfgs = { 1323 [USB2PHY_PORT_OTG] = { 1324 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1325 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1326 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1327 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1328 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1329 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1330 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1331 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1332 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1333 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1334 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1335 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1336 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1337 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1338 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1339 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1340 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1341 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1342 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1343 }, 1344 [USB2PHY_PORT_HOST] = { 1345 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1346 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1347 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1348 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1349 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1350 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1351 } 1352 }, 1353 .chg_det = { 1354 .opmode = { 0x0000, 3, 0, 5, 1 }, 1355 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1356 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1357 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1358 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1359 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1360 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1361 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1362 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1363 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1364 }, 1365 }, 1366 { 1367 .reg = 0xfe8b0000, 1368 .num_ports = 2, 1369 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1370 .port_cfgs = { 1371 [USB2PHY_PORT_OTG] = { 1372 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1373 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1374 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1375 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1376 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1377 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1378 }, 1379 [USB2PHY_PORT_HOST] = { 1380 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1381 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1382 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1383 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1384 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1385 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1386 } 1387 }, 1388 }, 1389 { /* sentinel */ } 1390 }; 1391 1392 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1393 { 1394 .reg = 0x0000, 1395 .num_ports = 1, 1396 .phy_tuning = rk3588_usb2phy_tuning, 1397 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1398 .port_cfgs = { 1399 [USB2PHY_PORT_OTG] = { 1400 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1401 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1402 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1403 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1404 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1405 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1406 } 1407 }, 1408 .chg_det = { 1409 .opmode = { 0x0008, 2, 2, 1, 0 }, 1410 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1411 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1412 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1413 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1414 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1415 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1416 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1417 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1418 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1419 }, 1420 }, 1421 { 1422 .reg = 0x4000, 1423 .num_ports = 1, 1424 .phy_tuning = rk3588_usb2phy_tuning, 1425 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1426 .port_cfgs = { 1427 /* Select suspend control from controller */ 1428 [USB2PHY_PORT_OTG] = { 1429 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1430 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1431 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1432 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1433 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1434 } 1435 }, 1436 }, 1437 { 1438 .reg = 0x8000, 1439 .num_ports = 1, 1440 .phy_tuning = rk3588_usb2phy_tuning, 1441 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1442 .port_cfgs = { 1443 [USB2PHY_PORT_HOST] = { 1444 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1445 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1446 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1447 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1448 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1449 } 1450 }, 1451 }, 1452 { 1453 .reg = 0xc000, 1454 .num_ports = 1, 1455 .phy_tuning = rk3588_usb2phy_tuning, 1456 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1457 .port_cfgs = { 1458 [USB2PHY_PORT_HOST] = { 1459 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1460 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1461 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1462 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1463 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1464 } 1465 }, 1466 }, 1467 { /* sentinel */ } 1468 }; 1469 1470 static const struct udevice_id rockchip_usb2phy_ids[] = { 1471 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1472 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1473 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1474 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1475 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1476 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1477 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1478 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1479 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1480 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1481 { } 1482 }; 1483 1484 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1485 .name = "rockchip_usb2phy_port", 1486 .id = UCLASS_PHY, 1487 .ops = &rockchip_usb2phy_ops, 1488 }; 1489 1490 U_BOOT_DRIVER(rockchip_usb2phy) = { 1491 .name = "rockchip_usb2phy", 1492 .id = UCLASS_PHY, 1493 .of_match = rockchip_usb2phy_ids, 1494 .probe = rockchip_usb2phy_probe, 1495 .bind = rockchip_usb2phy_bind, 1496 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1497 }; 1498