1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/gpio.h> 19 #include <reset-uclass.h> 20 21 #include "../usb/gadget/dwc2_udc_otg_priv.h" 22 23 #define U2PHY_BIT_WRITEABLE_SHIFT 16 24 #define CHG_DCD_MAX_RETRIES 6 25 #define CHG_PRI_MAX_RETRIES 2 26 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 27 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 28 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 29 30 struct rockchip_usb2phy; 31 32 enum power_supply_type { 33 POWER_SUPPLY_TYPE_UNKNOWN = 0, 34 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 35 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 36 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 37 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 38 }; 39 40 enum rockchip_usb2phy_port_id { 41 USB2PHY_PORT_OTG, 42 USB2PHY_PORT_HOST, 43 USB2PHY_NUM_PORTS, 44 }; 45 46 struct usb2phy_reg { 47 u32 offset; 48 u32 bitend; 49 u32 bitstart; 50 u32 disable; 51 u32 enable; 52 }; 53 54 /** 55 * struct rockchip_chg_det_reg: usb charger detect registers 56 * @cp_det: charging port detected successfully. 57 * @dcp_det: dedicated charging port detected successfully. 58 * @dp_det: assert data pin connect successfully. 59 * @idm_sink_en: open dm sink curren. 60 * @idp_sink_en: open dp sink current. 61 * @idp_src_en: open dm source current. 62 * @rdm_pdwn_en: open dm pull down resistor. 63 * @vdm_src_en: open dm voltage source. 64 * @vdp_src_en: open dp voltage source. 65 * @opmode: utmi operational mode. 66 */ 67 struct rockchip_chg_det_reg { 68 struct usb2phy_reg cp_det; 69 struct usb2phy_reg dcp_det; 70 struct usb2phy_reg dp_det; 71 struct usb2phy_reg idm_sink_en; 72 struct usb2phy_reg idp_sink_en; 73 struct usb2phy_reg idp_src_en; 74 struct usb2phy_reg rdm_pdwn_en; 75 struct usb2phy_reg vdm_src_en; 76 struct usb2phy_reg vdp_src_en; 77 struct usb2phy_reg opmode; 78 }; 79 80 /** 81 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 82 * @phy_sus: phy suspend register. 83 * @bvalid_det_en: vbus valid rise detection enable register. 84 * @bvalid_det_st: vbus valid rise detection status register. 85 * @bvalid_det_clr: vbus valid rise detection clear register. 86 * @ls_det_en: linestate detection enable register. 87 * @ls_det_st: linestate detection state register. 88 * @ls_det_clr: linestate detection clear register. 89 * @iddig_output: iddig output from grf. 90 * @iddig_en: utmi iddig select between grf and phy, 91 * 0: from phy; 1: from grf 92 * @idfall_det_en: id fall detection enable register. 93 * @idfall_det_st: id fall detection state register. 94 * @idfall_det_clr: id fall detection clear register. 95 * @idrise_det_en: id rise detection enable register. 96 * @idrise_det_st: id rise detection state register. 97 * @idrise_det_clr: id rise detection clear register. 98 * @utmi_avalid: utmi vbus avalid status register. 99 * @utmi_bvalid: utmi vbus bvalid status register. 100 * @utmi_iddig: otg port id pin status register. 101 * @utmi_ls: utmi linestate state register. 102 * @utmi_hstdet: utmi host disconnect register. 103 * @vbus_det_en: vbus detect function power down register. 104 */ 105 struct rockchip_usb2phy_port_cfg { 106 struct usb2phy_reg phy_sus; 107 struct usb2phy_reg bvalid_det_en; 108 struct usb2phy_reg bvalid_det_st; 109 struct usb2phy_reg bvalid_det_clr; 110 struct usb2phy_reg ls_det_en; 111 struct usb2phy_reg ls_det_st; 112 struct usb2phy_reg ls_det_clr; 113 struct usb2phy_reg iddig_output; 114 struct usb2phy_reg iddig_en; 115 struct usb2phy_reg idfall_det_en; 116 struct usb2phy_reg idfall_det_st; 117 struct usb2phy_reg idfall_det_clr; 118 struct usb2phy_reg idrise_det_en; 119 struct usb2phy_reg idrise_det_st; 120 struct usb2phy_reg idrise_det_clr; 121 struct usb2phy_reg utmi_avalid; 122 struct usb2phy_reg utmi_bvalid; 123 struct usb2phy_reg utmi_iddig; 124 struct usb2phy_reg utmi_ls; 125 struct usb2phy_reg utmi_hstdet; 126 struct usb2phy_reg vbus_det_en; 127 }; 128 129 /** 130 * struct rockchip_usb2phy_cfg: usb-phy configuration. 131 * @reg: the address offset of grf for usb-phy config. 132 * @num_ports: specify how many ports that the phy has. 133 * @phy_tuning: phy default parameters tunning. 134 * @clkout_ctl: keep on/turn off output clk of phy. 135 * @chg_det: charger detection registers. 136 */ 137 struct rockchip_usb2phy_cfg { 138 u32 reg; 139 u32 num_ports; 140 int (*phy_tuning)(struct rockchip_usb2phy *); 141 struct usb2phy_reg clkout_ctl; 142 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 143 const struct rockchip_chg_det_reg chg_det; 144 }; 145 146 /** 147 * @dcd_retries: The retry count used to track Data contact 148 * detection process. 149 * @primary_retries: The retry count used to do usb bc detection 150 * primary stage. 151 * @grf: General Register Files register base. 152 * @usbgrf_base : USB General Register Files register base. 153 * @phy_base: the base address of USB PHY. 154 * @phy_rst: phy reset control. 155 * @vbus_det_gpio: VBUS detection via GPIO. 156 * @phy_cfg: phy register configuration, assigned by driver data. 157 */ 158 struct rockchip_usb2phy { 159 u8 dcd_retries; 160 u8 primary_retries; 161 struct regmap *grf_base; 162 struct regmap *usbgrf_base; 163 void __iomem *phy_base; 164 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 165 struct reset_ctl phy_rst; 166 struct gpio_desc vbus_det_gpio; 167 const struct rockchip_usb2phy_cfg *phy_cfg; 168 }; 169 170 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 171 { 172 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 173 } 174 175 static inline int property_enable(struct regmap *base, 176 const struct usb2phy_reg *reg, bool en) 177 { 178 u32 val, mask, tmp; 179 180 tmp = en ? reg->enable : reg->disable; 181 mask = GENMASK(reg->bitend, reg->bitstart); 182 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 183 184 return regmap_write(base, reg->offset, val); 185 } 186 187 static inline bool property_enabled(struct regmap *base, 188 const struct usb2phy_reg *reg) 189 { 190 u32 tmp, orig; 191 u32 mask = GENMASK(reg->bitend, reg->bitstart); 192 193 regmap_read(base, reg->offset, &orig); 194 195 tmp = (orig & mask) >> reg->bitstart; 196 197 return tmp == reg->enable; 198 } 199 200 static inline void phy_clear_bits(void __iomem *reg, u32 bits) 201 { 202 u32 tmp = readl(reg); 203 204 tmp &= ~bits; 205 writel(tmp, reg); 206 } 207 208 static inline void phy_set_bits(void __iomem *reg, u32 bits) 209 { 210 u32 tmp = readl(reg); 211 212 tmp |= bits; 213 writel(tmp, reg); 214 } 215 216 static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val) 217 { 218 u32 tmp = readl(reg); 219 220 tmp &= ~mask; 221 tmp |= val & mask; 222 writel(tmp, reg); 223 } 224 225 static const char *chg_to_string(enum power_supply_type chg_type) 226 { 227 switch (chg_type) { 228 case POWER_SUPPLY_TYPE_USB: 229 return "USB_SDP_CHARGER"; 230 case POWER_SUPPLY_TYPE_USB_DCP: 231 return "USB_DCP_CHARGER"; 232 case POWER_SUPPLY_TYPE_USB_CDP: 233 return "USB_CDP_CHARGER"; 234 case POWER_SUPPLY_TYPE_USB_FLOATING: 235 return "USB_FLOATING_CHARGER"; 236 default: 237 return "INVALID_CHARGER"; 238 } 239 } 240 241 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 242 bool en) 243 { 244 struct regmap *base = get_reg_base(rphy); 245 246 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 247 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 248 } 249 250 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 251 bool en) 252 { 253 struct regmap *base = get_reg_base(rphy); 254 255 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 256 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 257 } 258 259 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 260 bool en) 261 { 262 struct regmap *base = get_reg_base(rphy); 263 264 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 265 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 266 } 267 268 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 269 { 270 bool vout = false; 271 struct regmap *base = get_reg_base(rphy); 272 273 while (rphy->primary_retries--) { 274 /* voltage source on DP, probe on DM */ 275 rockchip_chg_enable_primary_det(rphy, true); 276 mdelay(CHG_PRIMARY_DET_TIME); 277 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 278 if (vout) 279 break; 280 } 281 282 rockchip_chg_enable_primary_det(rphy, false); 283 return vout; 284 } 285 286 #ifdef CONFIG_ROCKCHIP_RK3506 287 static void rockchip_u2phy_get_vbus_gpio(struct udevice *dev) 288 { 289 ofnode otg_node, extcon_usb_node; 290 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 291 292 rphy->vbus_det_gpio.dev = NULL; 293 otg_node = dev_read_subnode(dev, "otg-port"); 294 if (!ofnode_valid(otg_node)) { 295 debug("%s: %s otg subnode not found!\n", __func__, dev->name); 296 return; 297 } 298 299 if (ofnode_read_bool(otg_node, "rockchip,gpio-vbus-det")) { 300 extcon_usb_node = ofnode_path("/extcon-usb"); 301 if (!ofnode_valid(extcon_usb_node)) { 302 debug("%s: extcon-usb node not found\n", __func__); 303 return; 304 } 305 306 gpio_request_by_name_nodev(extcon_usb_node, "vbus-gpio", 0, 307 &rphy->vbus_det_gpio, GPIOD_IS_IN); 308 } 309 } 310 #endif 311 312 int rockchip_chg_get_type(void) 313 { 314 const struct rockchip_usb2phy_port_cfg *port_cfg; 315 enum power_supply_type chg_type; 316 struct rockchip_usb2phy *rphy; 317 struct udevice *udev; 318 struct regmap *base; 319 bool is_dcd, vout; 320 int ret; 321 322 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 323 if (ret == -ENODEV) { 324 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 325 if (ret) { 326 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 327 return ret; 328 } 329 } 330 331 rphy = dev_get_priv(udev); 332 base = get_reg_base(rphy); 333 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 334 335 #ifdef CONFIG_ROCKCHIP_RK3506 336 rockchip_u2phy_get_vbus_gpio(udev); 337 #else 338 rphy->vbus_det_gpio.dev = NULL; 339 #endif 340 341 /* Check USB-Vbus status first */ 342 if (dm_gpio_is_valid(&rphy->vbus_det_gpio)) { 343 if (dm_gpio_get_value(&rphy->vbus_det_gpio)) { 344 pr_info("%s: vbus gpio voltage valid\n", __func__); 345 } else { 346 pr_info("%s: vbus gpio voltage invalid\n", __func__); 347 return POWER_SUPPLY_TYPE_UNKNOWN; 348 } 349 } else if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 350 pr_info("%s: no charger found\n", __func__); 351 return POWER_SUPPLY_TYPE_UNKNOWN; 352 } 353 354 #ifdef CONFIG_ROCKCHIP_RK3036 355 chg_type = POWER_SUPPLY_TYPE_USB; 356 goto out; 357 #endif 358 359 /* Suspend USB-PHY and put the controller in non-driving mode */ 360 property_enable(base, &port_cfg->phy_sus, true); 361 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 362 363 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 364 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 365 366 /* stage 1, start DCD processing stage */ 367 rockchip_chg_enable_dcd(rphy, true); 368 369 while (rphy->dcd_retries--) { 370 mdelay(CHG_DCD_POLL_TIME); 371 372 /* get data contact detection status */ 373 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 374 375 if (is_dcd || !rphy->dcd_retries) { 376 /* 377 * stage 2, turn off DCD circuitry, then 378 * voltage source on DP, probe on DM. 379 */ 380 rockchip_chg_enable_dcd(rphy, false); 381 rockchip_chg_enable_primary_det(rphy, true); 382 break; 383 } 384 } 385 386 mdelay(CHG_PRIMARY_DET_TIME); 387 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 388 rockchip_chg_enable_primary_det(rphy, false); 389 if (vout) { 390 /* stage 3, voltage source on DM, probe on DP */ 391 rockchip_chg_enable_secondary_det(rphy, true); 392 } else { 393 if (!rphy->dcd_retries) { 394 /* floating charger found */ 395 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 396 goto out; 397 } else { 398 /* 399 * Retry some times to make sure that it's 400 * really a USB SDP charger. 401 */ 402 vout = rockchip_chg_primary_det_retry(rphy); 403 if (vout) { 404 /* stage 3, voltage source on DM, probe on DP */ 405 rockchip_chg_enable_secondary_det(rphy, true); 406 } else { 407 /* USB SDP charger found */ 408 chg_type = POWER_SUPPLY_TYPE_USB; 409 goto out; 410 } 411 } 412 } 413 414 mdelay(CHG_SECONDARY_DET_TIME); 415 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 416 /* stage 4, turn off voltage source */ 417 rockchip_chg_enable_secondary_det(rphy, false); 418 if (vout) 419 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 420 else 421 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 422 423 out: 424 /* Resume USB-PHY and put the controller in normal mode */ 425 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 426 property_enable(base, &port_cfg->phy_sus, false); 427 428 debug("charger is %s\n", chg_to_string(chg_type)); 429 430 return chg_type; 431 } 432 433 int rockchip_u2phy_vbus_detect(void) 434 { 435 int chg_type; 436 437 chg_type = rockchip_chg_get_type(); 438 439 return (chg_type == POWER_SUPPLY_TYPE_USB || 440 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 441 } 442 443 void otg_phy_init(struct dwc2_udc *dev) 444 { 445 const struct rockchip_usb2phy_port_cfg *port_cfg; 446 struct rockchip_usb2phy *rphy; 447 struct udevice *udev; 448 struct regmap *base; 449 int ret; 450 451 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 452 if (ret == -ENODEV) { 453 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 454 if (ret) { 455 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 456 return; 457 } 458 } 459 460 rphy = dev_get_priv(udev); 461 base = get_reg_base(rphy); 462 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 463 464 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 465 if(rphy->phy_cfg->clkout_ctl.disable) 466 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 467 468 /* Reset USB-PHY */ 469 property_enable(base, &port_cfg->phy_sus, true); 470 udelay(20); 471 property_enable(base, &port_cfg->phy_sus, false); 472 mdelay(2); 473 } 474 475 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 476 { 477 int ret; 478 479 if (rphy->phy_rst.dev) { 480 ret = reset_assert(&rphy->phy_rst); 481 if (ret < 0) { 482 pr_err("u2phy assert reset failed: %d", ret); 483 return ret; 484 } 485 486 udelay(20); 487 488 ret = reset_deassert(&rphy->phy_rst); 489 if (ret < 0) { 490 pr_err("u2phy deassert reset failed: %d", ret); 491 return ret; 492 } 493 494 udelay(100); 495 } 496 497 return 0; 498 } 499 500 static int rockchip_usb2phy_init(struct phy *phy) 501 { 502 struct udevice *parent = phy->dev->parent; 503 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 504 const struct rockchip_usb2phy_port_cfg *port_cfg; 505 struct regmap *base = get_reg_base(rphy); 506 507 if (phy->id == USB2PHY_PORT_OTG) { 508 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 509 } else if (phy->id == USB2PHY_PORT_HOST) { 510 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 511 } else { 512 dev_err(phy->dev, "phy id %lu not support", phy->id); 513 return -EINVAL; 514 } 515 516 property_enable(base, &port_cfg->phy_sus, false); 517 518 /* waiting for the utmi_clk to become stable */ 519 udelay(2000); 520 521 return 0; 522 } 523 524 static int rockchip_usb2phy_exit(struct phy *phy) 525 { 526 struct udevice *parent = phy->dev->parent; 527 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 528 const struct rockchip_usb2phy_port_cfg *port_cfg; 529 struct regmap *base = get_reg_base(rphy); 530 531 if (phy->id == USB2PHY_PORT_OTG) { 532 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 533 } else if (phy->id == USB2PHY_PORT_HOST) { 534 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 535 } else { 536 dev_err(phy->dev, "phy id %lu not support", phy->id); 537 return -EINVAL; 538 } 539 540 property_enable(base, &port_cfg->phy_sus, true); 541 542 return 0; 543 } 544 545 static int rockchip_usb2phy_power_on(struct phy *phy) 546 { 547 struct udevice *parent = phy->dev->parent; 548 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 549 struct udevice *vbus = rphy->vbus_supply[phy->id]; 550 int ret; 551 552 if (vbus) { 553 ret = regulator_set_enable(vbus, true); 554 if (ret) { 555 pr_err("%s: Failed to set VBus supply\n", __func__); 556 return ret; 557 } 558 } 559 560 return 0; 561 } 562 563 static int rockchip_usb2phy_power_off(struct phy *phy) 564 { 565 struct udevice *parent = phy->dev->parent; 566 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 567 struct udevice *vbus = rphy->vbus_supply[phy->id]; 568 int ret; 569 570 if (vbus) { 571 ret = regulator_set_enable(vbus, false); 572 if (ret) { 573 pr_err("%s: Failed to set VBus supply\n", __func__); 574 return ret; 575 } 576 } 577 578 return 0; 579 } 580 581 static int rockchip_usb2phy_of_xlate(struct phy *phy, 582 struct ofnode_phandle_args *args) 583 { 584 const char *dev_name = phy->dev->name; 585 struct udevice *parent = phy->dev->parent; 586 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 587 588 if (!strcasecmp(dev_name, "host-port")) { 589 phy->id = USB2PHY_PORT_HOST; 590 device_get_supply_regulator(phy->dev, "phy-supply", 591 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 592 } else if (!strcasecmp(dev_name, "otg-port")) { 593 phy->id = USB2PHY_PORT_OTG; 594 device_get_supply_regulator(phy->dev, "phy-supply", 595 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 596 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 597 device_get_supply_regulator(phy->dev, "vbus-supply", 598 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 599 } else { 600 pr_err("%s: invalid dev name\n", __func__); 601 return -EINVAL; 602 } 603 604 return 0; 605 } 606 607 static int rockchip_usb2phy_bind(struct udevice *dev) 608 { 609 struct udevice *child; 610 ofnode subnode; 611 const char *node_name; 612 int ret; 613 614 dev_for_each_subnode(subnode, dev) { 615 if (!ofnode_valid(subnode)) { 616 debug("%s: %s subnode not found", __func__, dev->name); 617 return -ENXIO; 618 } 619 620 node_name = ofnode_get_name(subnode); 621 debug("%s: subnode %s\n", __func__, node_name); 622 623 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 624 node_name, subnode, &child); 625 if (ret) { 626 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 627 __func__, node_name); 628 return ret; 629 } 630 } 631 632 return 0; 633 } 634 635 static int rockchip_usb2phy_probe(struct udevice *dev) 636 { 637 const struct rockchip_usb2phy_cfg *phy_cfgs; 638 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 639 struct udevice *parent = dev->parent; 640 struct udevice *syscon; 641 struct resource res; 642 u32 reg, index; 643 int ret; 644 645 rphy->phy_base = (void __iomem *)dev_read_addr(dev); 646 if (IS_ERR(rphy->phy_base)) { 647 dev_err(dev, "get the base address of usb phy failed\n"); 648 } 649 650 if (!strncmp(parent->name, "root_driver", 11) && 651 dev_read_bool(dev, "rockchip,grf")) { 652 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 653 "rockchip,grf", &syscon); 654 if (ret) { 655 dev_err(dev, "get syscon grf failed\n"); 656 return ret; 657 } 658 659 rphy->grf_base = syscon_get_regmap(syscon); 660 } else { 661 rphy->grf_base = syscon_get_regmap(parent); 662 } 663 664 if (rphy->grf_base <= 0) { 665 dev_err(dev, "get syscon grf regmap failed\n"); 666 return -EINVAL; 667 } 668 669 if (dev_read_bool(dev, "rockchip,usbgrf")) { 670 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 671 "rockchip,usbgrf", &syscon); 672 if (ret) { 673 dev_err(dev, "get syscon usbgrf failed\n"); 674 return ret; 675 } 676 677 rphy->usbgrf_base = syscon_get_regmap(syscon); 678 if (rphy->usbgrf_base <= 0) { 679 dev_err(dev, "get syscon usbgrf regmap failed\n"); 680 return -EINVAL; 681 } 682 } else { 683 rphy->usbgrf_base = NULL; 684 } 685 686 if (!strncmp(parent->name, "root_driver", 11)) { 687 ret = dev_read_resource(dev, 0, &res); 688 reg = res.start; 689 } else { 690 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 691 } 692 693 if (ret) { 694 dev_err(dev, "could not read reg\n"); 695 return -EINVAL; 696 } 697 698 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 699 if (ret) 700 dev_dbg(dev, "no u2phy reset control specified\n"); 701 702 phy_cfgs = 703 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 704 if (!phy_cfgs) { 705 dev_err(dev, "unable to get phy_cfgs\n"); 706 return -EINVAL; 707 } 708 709 /* find out a proper config which can be matched with dt. */ 710 index = 0; 711 do { 712 if (phy_cfgs[index].reg == reg) { 713 rphy->phy_cfg = &phy_cfgs[index]; 714 break; 715 } 716 ++index; 717 } while (phy_cfgs[index].reg); 718 719 if (!rphy->phy_cfg) { 720 dev_err(dev, "no phy-config can be matched\n"); 721 return -EINVAL; 722 } 723 724 if (rphy->phy_cfg->phy_tuning) 725 rphy->phy_cfg->phy_tuning(rphy); 726 727 return 0; 728 } 729 730 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 731 { 732 struct regmap *base = get_reg_base(rphy); 733 int ret = 0; 734 735 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 736 if (rphy->phy_cfg->reg == 0x760) 737 ret = regmap_write(base, 0x76c, 0x00070004); 738 739 return ret; 740 } 741 742 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 743 { 744 struct regmap *base = get_reg_base(rphy); 745 unsigned int tmp, orig; 746 int ret; 747 748 if (soc_is_rk3308bs()) { 749 /* Enable otg/host port pre-emphasis during non-chirp phase */ 750 ret = regmap_read(base, 0, &orig); 751 if (ret) 752 return ret; 753 tmp = orig & ~GENMASK(2, 0); 754 tmp |= BIT(2) & GENMASK(2, 0); 755 ret = regmap_write(base, 0, tmp); 756 if (ret) 757 return ret; 758 759 /* Set otg port squelch trigger point configure to 100mv */ 760 ret = regmap_read(base, 0x004, &orig); 761 if (ret) 762 return ret; 763 tmp = orig & ~GENMASK(7, 5); 764 tmp |= 0x40 & GENMASK(7, 5); 765 ret = regmap_write(base, 0x004, tmp); 766 if (ret) 767 return ret; 768 769 ret = regmap_read(base, 0x008, &orig); 770 if (ret) 771 return ret; 772 tmp = orig & ~BIT(0); 773 tmp |= 0x1 & BIT(0); 774 ret = regmap_write(base, 0x008, tmp); 775 if (ret) 776 return ret; 777 778 /* Enable host port pre-emphasis during non-chirp phase */ 779 ret = regmap_read(base, 0x400, &orig); 780 if (ret) 781 return ret; 782 tmp = orig & ~GENMASK(2, 0); 783 tmp |= BIT(2) & GENMASK(2, 0); 784 ret = regmap_write(base, 0x400, tmp); 785 if (ret) 786 return ret; 787 788 /* Set host port squelch trigger point configure to 100mv */ 789 ret = regmap_read(base, 0x404, &orig); 790 if (ret) 791 return ret; 792 tmp = orig & ~GENMASK(7, 5); 793 tmp |= 0x40 & GENMASK(7, 5); 794 ret = regmap_write(base, 0x404, tmp); 795 if (ret) 796 return ret; 797 798 ret = regmap_read(base, 0x408, &orig); 799 if (ret) 800 return ret; 801 tmp = orig & ~BIT(0); 802 tmp |= 0x1 & BIT(0); 803 ret = regmap_write(base, 0x408, tmp); 804 if (ret) 805 return ret; 806 } 807 808 return 0; 809 } 810 811 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 812 { 813 struct regmap *base = get_reg_base(rphy); 814 int ret; 815 816 if (soc_is_px30s()) { 817 /* Enable otg/host port pre-emphasis during non-chirp phase */ 818 ret = regmap_update_bits(base, 0x8000, GENMASK(2, 0), BIT(2)); 819 if (ret) 820 return ret; 821 822 /* Set otg port squelch trigger point configure to 100mv */ 823 ret = regmap_update_bits(base, 0x8004, GENMASK(7, 5), 0x40); 824 if (ret) 825 return ret; 826 827 ret = regmap_update_bits(base, 0x8008, BIT(0), 0x1); 828 if (ret) 829 return ret; 830 831 /* Enable host port pre-emphasis during non-chirp phase */ 832 ret = regmap_update_bits(base, 0x8400, GENMASK(2, 0), BIT(2)); 833 if (ret) 834 return ret; 835 836 /* Set host port squelch trigger point configure to 100mv */ 837 ret = regmap_update_bits(base, 0x8404, GENMASK(7, 5), 0x40); 838 if (ret) 839 return ret; 840 841 ret = regmap_update_bits(base, 0x8408, BIT(0), 0x1); 842 if (ret) 843 return ret; 844 } else { 845 /* Open debug mode for tuning */ 846 ret = regmap_write(base, 0x2c, 0xffff0400); 847 if (ret) 848 return ret; 849 850 /* Open pre-emphasize in non-chirp state for otg port */ 851 ret = regmap_write(base, 0x0, 0x00070004); 852 if (ret) 853 return ret; 854 855 /* Open pre-emphasize in non-chirp state for host port */ 856 ret = regmap_write(base, 0x30, 0x00070004); 857 if (ret) 858 return ret; 859 } 860 861 return 0; 862 } 863 864 static int rv1103b_usb2phy_tuning(struct rockchip_usb2phy *rphy) 865 { 866 /* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */ 867 phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07); 868 869 /* Set Tx HS pre_emphasize strength to 3'b001 */ 870 phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3)); 871 872 /* Set RX Squelch trigger point configure to 4'b0000(112.5 mV) */ 873 phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3)); 874 875 /* Turn off differential receiver by default to save power */ 876 phy_clear_bits(rphy->phy_base + 0x100, BIT(6)); 877 878 /* Set 45ohm HS ODT value to 5'b10111 to increase driver strength */ 879 phy_update_bits(rphy->phy_base + 0x11c, GENMASK(4, 0), 0x17); 880 881 /* Set Tx HS eye height tuning to 3'b011(462 mV)*/ 882 phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2)); 883 884 /* Bypass Squelch detector calibration */ 885 phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4)); 886 phy_update_bits(rphy->phy_base + 0x1b4, GENMASK(7, 4), (0x01 << 4)); 887 888 /* Set HS disconnect detect mode to single ended detect mode */ 889 phy_set_bits(rphy->phy_base + 0x70, BIT(2)); 890 891 /* Set Host Disconnect Detection to 675mV */ 892 phy_update_bits(rphy->phy_base + 0x60, GENMASK(1, 0), 0x0); 893 phy_update_bits(rphy->phy_base + 0x64, GENMASK(7, 7), BIT(7)); 894 phy_update_bits(rphy->phy_base + 0x68, GENMASK(0, 0), 0x0); 895 896 return 0; 897 } 898 899 static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) 900 { 901 /* Set HS disconnect detect mode to single ended detect mode */ 902 phy_set_bits(rphy->phy_base + 0x70, BIT(2)); 903 904 return 0; 905 } 906 907 static int rk3506_usb2phy_tuning(struct rockchip_usb2phy *rphy) 908 { 909 /* Turn off otg0 port differential receiver in suspend mode */ 910 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 911 912 /* Turn off otg1 port differential receiver in suspend mode */ 913 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 914 915 /* Set otg0 port HS eye height to 425mv(default is 450mv) */ 916 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x05 << 4)); 917 918 /* Set otg1 port HS eye height to 425mv(default is 450mv) */ 919 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x05 << 4)); 920 921 /* Choose the Tx fs/ls data as linestate from TX driver for otg0 port */ 922 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 923 924 /* Choose the Tx fs/ls data as linestate from TX driver for otg1 port */ 925 phy_update_bits(rphy->phy_base + 0x494, GENMASK(6, 3), (0x03 << 3)); 926 927 return 0; 928 } 929 930 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy) 931 { 932 if (IS_ERR(rphy->phy_base)) { 933 return PTR_ERR(rphy->phy_base); 934 } 935 936 /* Turn off otg port differential receiver in suspend mode */ 937 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 938 939 /* Turn off host port differential receiver in suspend mode */ 940 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 941 942 /* Set otg port HS eye height to 400mv(default is 450mv) */ 943 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4)); 944 945 /* Set host port HS eye height to 400mv(default is 450mv) */ 946 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4)); 947 948 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */ 949 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 950 951 /* Turn on output clk of phy*/ 952 phy_update_bits(rphy->phy_base + 0x41c, GENMASK(7, 2), (0x27 << 2)); 953 954 return 0; 955 } 956 957 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy) 958 { 959 if (IS_ERR(rphy->phy_base)) { 960 return PTR_ERR(rphy->phy_base); 961 } 962 963 /* Turn off differential receiver by default to save power */ 964 phy_clear_bits(rphy->phy_base + 0x0030, BIT(2)); 965 phy_clear_bits(rphy->phy_base + 0x0430, BIT(2)); 966 967 /* Enable pre-emphasis during non-chirp phase */ 968 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); 969 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); 970 971 /* Set HS eye height to 425mv(default is 400mv) */ 972 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); 973 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); 974 975 return 0; 976 } 977 978 static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy) 979 { 980 struct regmap *base = get_reg_base(rphy); 981 int ret; 982 983 if (rphy->phy_cfg->reg == 0x0) { 984 /* Deassert SIDDQ to power on analog block */ 985 ret = regmap_write(base, 0x0010, GENMASK(29, 29) | 0x0000); 986 if (ret) 987 return ret; 988 989 /* Do reset after exit IDDQ mode */ 990 ret = rockchip_usb2phy_reset(rphy); 991 if (ret) 992 return ret; 993 994 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 995 ret = regmap_write(base, 0x000c, GENMASK(27, 24) | 0x0900); 996 if (ret) 997 return ret; 998 999 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1000 ret = regmap_write(base, 0x0010, GENMASK(20, 19) | 0x0010); 1001 if (ret) 1002 return ret; 1003 } else if (rphy->phy_cfg->reg == 0x2000) { 1004 /* Deassert SIDDQ to power on analog block */ 1005 ret = regmap_write(base, 0x2010, GENMASK(29, 29) | 0x0000); 1006 if (ret) 1007 return ret; 1008 1009 /* Do reset after exit IDDQ mode */ 1010 ret = rockchip_usb2phy_reset(rphy); 1011 if (ret) 1012 return ret; 1013 1014 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 1015 ret = regmap_write(base, 0x200c, GENMASK(27, 24) | 0x0900); 1016 if (ret) 1017 return ret; 1018 1019 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1020 ret = regmap_write(base, 0x2010, GENMASK(20, 19) | 0x0010); 1021 if (ret) 1022 return ret; 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 1029 { 1030 struct regmap *base = get_reg_base(rphy); 1031 int ret; 1032 1033 /* Deassert SIDDQ to power on analog block */ 1034 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 1035 if (ret) 1036 return ret; 1037 1038 /* Do reset after exit IDDQ mode */ 1039 ret = rockchip_usb2phy_reset(rphy); 1040 if (ret) 1041 return ret; 1042 1043 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 1044 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 1045 if (ret) 1046 return ret; 1047 1048 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1049 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 1050 if (ret) 1051 return ret; 1052 1053 return 0; 1054 } 1055 1056 static struct phy_ops rockchip_usb2phy_ops = { 1057 .init = rockchip_usb2phy_init, 1058 .exit = rockchip_usb2phy_exit, 1059 .power_on = rockchip_usb2phy_power_on, 1060 .power_off = rockchip_usb2phy_power_off, 1061 .of_xlate = rockchip_usb2phy_of_xlate, 1062 }; 1063 1064 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 1065 { 1066 .reg = 0x100, 1067 .num_ports = 2, 1068 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1069 .port_cfgs = { 1070 [USB2PHY_PORT_OTG] = { 1071 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1072 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1073 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1074 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1075 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1076 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1077 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1078 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1079 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1080 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1081 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1082 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1083 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1084 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1085 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1086 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1087 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1088 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1089 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1090 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1091 }, 1092 [USB2PHY_PORT_HOST] = { 1093 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1094 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1095 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1096 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1097 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1098 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1099 } 1100 }, 1101 .chg_det = { 1102 .opmode = { 0x0100, 3, 0, 5, 1 }, 1103 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1104 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1105 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1106 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1107 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1108 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1109 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1110 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1111 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1112 }, 1113 }, 1114 { /* sentinel */ } 1115 }; 1116 1117 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = { 1118 { 1119 .reg = 0x17c, 1120 .num_ports = 2, 1121 .clkout_ctl = { 0x017c, 11, 11, 1, 0 }, 1122 .port_cfgs = { 1123 [USB2PHY_PORT_OTG] = { 1124 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1125 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1126 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1127 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1128 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1129 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1130 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1131 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1132 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1133 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1134 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1135 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1136 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1137 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1138 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1139 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1140 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1141 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1142 }, 1143 [USB2PHY_PORT_HOST] = { 1144 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1145 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1146 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1147 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1148 } 1149 }, 1150 }, 1151 { /* sentinel */ } 1152 }; 1153 1154 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 1155 { 1156 .reg = 0x17c, 1157 .num_ports = 2, 1158 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 1159 .port_cfgs = { 1160 [USB2PHY_PORT_OTG] = { 1161 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1162 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1163 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1164 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1165 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1166 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1167 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1168 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1169 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1170 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1171 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1172 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1173 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1174 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1175 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1176 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1177 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1178 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1179 }, 1180 [USB2PHY_PORT_HOST] = { 1181 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1182 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1183 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1184 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1185 } 1186 }, 1187 .chg_det = { 1188 .opmode = { 0x017c, 3, 0, 5, 1 }, 1189 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 1190 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 1191 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 1192 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 1193 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 1194 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 1195 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 1196 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 1197 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 1198 }, 1199 }, 1200 { /* sentinel */ } 1201 }; 1202 1203 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 1204 { 1205 .reg = 0x760, 1206 .num_ports = 2, 1207 .phy_tuning = rk322x_usb2phy_tuning, 1208 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1209 .port_cfgs = { 1210 [USB2PHY_PORT_OTG] = { 1211 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 1212 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1213 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1214 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1215 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 1216 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 1217 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 1218 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 1219 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 1220 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 1221 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 1222 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 1223 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1224 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1225 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1226 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1227 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 1228 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1229 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 1230 }, 1231 [USB2PHY_PORT_HOST] = { 1232 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 1233 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1234 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1235 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1236 } 1237 }, 1238 .chg_det = { 1239 .opmode = { 0x0760, 3, 0, 5, 1 }, 1240 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1241 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1242 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1243 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1244 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1245 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1246 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1247 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1248 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1249 }, 1250 }, 1251 { 1252 .reg = 0x800, 1253 .num_ports = 2, 1254 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1255 .port_cfgs = { 1256 [USB2PHY_PORT_OTG] = { 1257 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1258 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1259 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1260 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1261 }, 1262 [USB2PHY_PORT_HOST] = { 1263 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1264 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1265 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1266 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1267 } 1268 }, 1269 }, 1270 { /* sentinel */ } 1271 }; 1272 1273 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1274 { 1275 .reg = 0x100, 1276 .num_ports = 2, 1277 .phy_tuning = rk3308_usb2phy_tuning, 1278 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1279 .port_cfgs = { 1280 [USB2PHY_PORT_OTG] = { 1281 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1282 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1283 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1284 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1285 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1286 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1287 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1288 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1289 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1290 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1291 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1292 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1293 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1294 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1295 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1296 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1297 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1298 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1299 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1300 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1301 }, 1302 [USB2PHY_PORT_HOST] = { 1303 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1304 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1305 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1306 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1307 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1308 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1309 } 1310 }, 1311 .chg_det = { 1312 .opmode = { 0x0100, 3, 0, 5, 1 }, 1313 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1314 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1315 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1316 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1317 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1318 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1319 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1320 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1321 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1322 }, 1323 }, 1324 { /* sentinel */ } 1325 }; 1326 1327 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1328 { 1329 .reg = 0x100, 1330 .num_ports = 2, 1331 .phy_tuning = rk3328_usb2phy_tuning, 1332 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1333 .port_cfgs = { 1334 [USB2PHY_PORT_OTG] = { 1335 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1336 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1337 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1338 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1339 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1340 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1341 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1342 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1343 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1344 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1345 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1346 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1347 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1348 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1349 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1350 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1351 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1352 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1353 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1354 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1355 }, 1356 [USB2PHY_PORT_HOST] = { 1357 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1358 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1359 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1360 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1361 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1362 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1363 } 1364 }, 1365 .chg_det = { 1366 .opmode = { 0x0100, 3, 0, 5, 1 }, 1367 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1368 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1369 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1370 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1371 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1372 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1373 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1374 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1375 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1376 }, 1377 }, 1378 { /* sentinel */ } 1379 }; 1380 1381 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1382 { 1383 .reg = 0x700, 1384 .num_ports = 2, 1385 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1386 .port_cfgs = { 1387 [USB2PHY_PORT_OTG] = { 1388 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1389 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1390 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1391 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1392 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1393 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1394 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1395 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1396 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1397 }, 1398 [USB2PHY_PORT_HOST] = { 1399 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1400 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1401 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1402 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1403 } 1404 }, 1405 .chg_det = { 1406 .opmode = { 0x0700, 3, 0, 5, 1 }, 1407 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1408 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1409 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1410 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1411 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1412 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1413 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1414 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1415 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1416 }, 1417 }, 1418 { /* sentinel */ } 1419 }; 1420 1421 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1422 { 1423 .reg = 0xe450, 1424 .num_ports = 2, 1425 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1426 .port_cfgs = { 1427 [USB2PHY_PORT_OTG] = { 1428 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1429 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1430 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1431 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1432 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1433 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1434 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1435 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1436 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1437 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1438 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1439 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1440 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1441 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1442 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1443 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1444 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1445 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1446 }, 1447 [USB2PHY_PORT_HOST] = { 1448 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1449 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1450 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1451 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1452 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1453 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1454 } 1455 }, 1456 .chg_det = { 1457 .opmode = { 0xe454, 3, 0, 5, 1 }, 1458 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1459 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1460 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1461 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1462 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1463 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1464 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1465 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1466 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1467 }, 1468 }, 1469 { 1470 .reg = 0xe460, 1471 .num_ports = 2, 1472 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1473 .port_cfgs = { 1474 [USB2PHY_PORT_OTG] = { 1475 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1476 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1477 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1478 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1479 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1480 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1481 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1482 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1483 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1484 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1485 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1486 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1487 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1488 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1489 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1490 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1491 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1492 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1493 }, 1494 [USB2PHY_PORT_HOST] = { 1495 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1496 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1497 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1498 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1499 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1500 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1501 } 1502 }, 1503 .chg_det = { 1504 .opmode = { 0xe464, 3, 0, 5, 1 }, 1505 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1506 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1507 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1508 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1509 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1510 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1511 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1512 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1513 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1514 }, 1515 }, 1516 { /* sentinel */ } 1517 }; 1518 1519 static const struct rockchip_usb2phy_cfg rv1103b_phy_cfgs[] = { 1520 { 1521 .reg = 0x20e10000, 1522 .num_ports = 1, 1523 .phy_tuning = rv1103b_usb2phy_tuning, 1524 .clkout_ctl = { 0x50058, 4, 4, 1, 0 }, 1525 .port_cfgs = { 1526 [USB2PHY_PORT_OTG] = { 1527 .phy_sus = { 0x50050, 8, 0, 0, 0x1d1 }, 1528 .bvalid_det_en = { 0x50100, 2, 2, 0, 1 }, 1529 .bvalid_det_st = { 0x50104, 2, 2, 0, 1 }, 1530 .bvalid_det_clr = { 0x50108, 2, 2, 0, 1 }, 1531 .iddig_output = { 0x50050, 10, 10, 0, 1 }, 1532 .iddig_en = { 0x50050, 9, 9, 0, 1 }, 1533 .idfall_det_en = { 0x50100, 5, 5, 0, 1 }, 1534 .idfall_det_st = { 0x50104, 5, 5, 0, 1 }, 1535 .idfall_det_clr = { 0x50108, 5, 5, 0, 1 }, 1536 .idrise_det_en = { 0x50100, 4, 4, 0, 1 }, 1537 .idrise_det_st = { 0x50104, 4, 4, 0, 1 }, 1538 .idrise_det_clr = { 0x50108, 4, 4, 0, 1 }, 1539 .ls_det_en = { 0x50100, 0, 0, 0, 1 }, 1540 .ls_det_st = { 0x50104, 0, 0, 0, 1 }, 1541 .ls_det_clr = { 0x50108, 0, 0, 0, 1 }, 1542 .utmi_avalid = { 0x50060, 10, 10, 0, 1 }, 1543 .utmi_bvalid = { 0x50060, 9, 9, 0, 1 }, 1544 .utmi_iddig = { 0x50060, 6, 6, 0, 1 }, 1545 .utmi_ls = { 0x50060, 5, 4, 0, 1 }, 1546 }, 1547 }, 1548 .chg_det = { 1549 .opmode = { 0x50050, 3, 0, 5, 1 }, 1550 .cp_det = { 0x50060, 13, 13, 0, 1 }, 1551 .dcp_det = { 0x50060, 12, 12, 0, 1 }, 1552 .dp_det = { 0x50060, 14, 14, 0, 1 }, 1553 .idm_sink_en = { 0x50058, 8, 8, 0, 1 }, 1554 .idp_sink_en = { 0x50058, 7, 7, 0, 1 }, 1555 .idp_src_en = { 0x50058, 9, 9, 0, 1 }, 1556 .rdm_pdwn_en = { 0x50058, 10, 10, 0, 1 }, 1557 .vdm_src_en = { 0x50058, 12, 12, 0, 1 }, 1558 .vdp_src_en = { 0x50058, 11, 11, 0, 1 }, 1559 }, 1560 }, 1561 { /* sentinel */ } 1562 }; 1563 1564 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = { 1565 { 1566 .reg = 0xff3e0000, 1567 .num_ports = 1, 1568 .phy_tuning = rv1106_usb2phy_tuning, 1569 .clkout_ctl = { 0x0058, 4, 4, 1, 0 }, 1570 .port_cfgs = { 1571 [USB2PHY_PORT_OTG] = { 1572 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 }, 1573 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 }, 1574 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 }, 1575 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 }, 1576 .iddig_output = { 0x0050, 10, 10, 0, 1 }, 1577 .iddig_en = { 0x0050, 9, 9, 0, 1 }, 1578 .idfall_det_en = { 0x0100, 5, 5, 0, 1 }, 1579 .idfall_det_st = { 0x0104, 5, 5, 0, 1 }, 1580 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 }, 1581 .idrise_det_en = { 0x0100, 4, 4, 0, 1 }, 1582 .idrise_det_st = { 0x0104, 4, 4, 0, 1 }, 1583 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 }, 1584 .ls_det_en = { 0x0100, 0, 0, 0, 1 }, 1585 .ls_det_st = { 0x0104, 0, 0, 0, 1 }, 1586 .ls_det_clr = { 0x0108, 0, 0, 0, 1 }, 1587 .utmi_avalid = { 0x0060, 10, 10, 0, 1 }, 1588 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 }, 1589 .utmi_iddig = { 0x0060, 6, 6, 0, 1 }, 1590 .utmi_ls = { 0x0060, 5, 4, 0, 1 }, 1591 }, 1592 }, 1593 .chg_det = { 1594 .opmode = { 0x0050, 3, 0, 5, 1 }, 1595 .cp_det = { 0x0060, 13, 13, 0, 1 }, 1596 .dcp_det = { 0x0060, 12, 12, 0, 1 }, 1597 .dp_det = { 0x0060, 14, 14, 0, 1 }, 1598 .idm_sink_en = { 0x0058, 8, 8, 0, 1 }, 1599 .idp_sink_en = { 0x0058, 7, 7, 0, 1 }, 1600 .idp_src_en = { 0x0058, 9, 9, 0, 1 }, 1601 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 }, 1602 .vdm_src_en = { 0x0058, 12, 12, 0, 1 }, 1603 .vdp_src_en = { 0x0058, 11, 11, 0, 1 }, 1604 }, 1605 }, 1606 { /* sentinel */ } 1607 }; 1608 1609 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1610 { 1611 .reg = 0x100, 1612 .num_ports = 2, 1613 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1614 .port_cfgs = { 1615 [USB2PHY_PORT_OTG] = { 1616 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1617 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1618 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1619 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1620 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1621 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1622 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1623 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1624 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1625 }, 1626 [USB2PHY_PORT_HOST] = { 1627 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1628 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1629 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1630 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1631 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1632 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1633 } 1634 }, 1635 .chg_det = { 1636 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1637 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1638 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1639 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1640 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1641 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1642 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1643 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1644 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1645 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1646 }, 1647 }, 1648 { /* sentinel */ } 1649 }; 1650 1651 static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { 1652 { 1653 .reg = 0xff2b0000, 1654 .num_ports = 2, 1655 .phy_tuning = rk3506_usb2phy_tuning, 1656 .port_cfgs = { 1657 [USB2PHY_PORT_OTG] = { 1658 .phy_sus = { 0x0060, 8, 0, 0, 0x1d1 }, 1659 .bvalid_det_en = { 0x0150, 2, 2, 0, 1 }, 1660 .bvalid_det_st = { 0x0154, 2, 2, 0, 1 }, 1661 .bvalid_det_clr = { 0x0158, 2, 2, 0, 1 }, 1662 .iddig_output = { 0x0060, 10, 10, 0, 1 }, 1663 .iddig_en = { 0x0060, 9, 9, 0, 1 }, 1664 .idfall_det_en = { 0x0150, 5, 5, 0, 1 }, 1665 .idfall_det_st = { 0x0154, 5, 5, 0, 1 }, 1666 .idfall_det_clr = { 0x0158, 5, 5, 0, 1 }, 1667 .idrise_det_en = { 0x0150, 4, 4, 0, 1 }, 1668 .idrise_det_st = { 0x0154, 4, 4, 0, 1 }, 1669 .idrise_det_clr = { 0x0158, 4, 4, 0, 1 }, 1670 .ls_det_en = { 0x0150, 0, 0, 0, 1 }, 1671 .ls_det_st = { 0x0154, 0, 0, 0, 1 }, 1672 .ls_det_clr = { 0x0158, 0, 0, 0, 1 }, 1673 .utmi_avalid = { 0x0118, 1, 1, 0, 1 }, 1674 .utmi_bvalid = { 0x0118, 0, 0, 0, 1 }, 1675 .utmi_iddig = { 0x0118, 6, 6, 0, 1 }, 1676 .utmi_ls = { 0x0118, 5, 4, 0, 1 }, 1677 }, 1678 [USB2PHY_PORT_HOST] = { 1679 .phy_sus = { 0x0070, 8, 0, 0x1d2, 0x1d1 }, 1680 .ls_det_en = { 0x0170, 0, 0, 0, 1 }, 1681 .ls_det_st = { 0x0174, 0, 0, 0, 1 }, 1682 .ls_det_clr = { 0x0178, 0, 0, 0, 1 }, 1683 .utmi_ls = { 0x0118, 13, 12, 0, 1 }, 1684 .utmi_hstdet = { 0x0118, 15, 15, 0, 1 } 1685 } 1686 }, 1687 .chg_det = { 1688 .opmode = { 0x0060, 3, 0, 5, 1 }, 1689 .cp_det = { 0x0118, 19, 19, 0, 1 }, 1690 .dcp_det = { 0x0118, 18, 18, 0, 1 }, 1691 .dp_det = { 0x0118, 20, 20, 0, 1 }, 1692 .idm_sink_en = { 0x006c, 1, 1, 0, 1 }, 1693 .idp_sink_en = { 0x006c, 0, 0, 0, 1 }, 1694 .idp_src_en = { 0x006c, 2, 2, 0, 1 }, 1695 .rdm_pdwn_en = { 0x006c, 3, 3, 0, 1 }, 1696 .vdm_src_en = { 0x006c, 5, 5, 0, 1 }, 1697 .vdp_src_en = { 0x006c, 4, 4, 0, 1 }, 1698 }, 1699 } 1700 }; 1701 1702 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1703 { 1704 .reg = 0xffdf0000, 1705 .num_ports = 2, 1706 .phy_tuning = rk3528_usb2phy_tuning, 1707 .port_cfgs = { 1708 [USB2PHY_PORT_OTG] = { 1709 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1710 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1711 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1712 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1713 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1714 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1715 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1716 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1717 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1718 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1719 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1720 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1721 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1722 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1723 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1724 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1725 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1726 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1727 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1728 }, 1729 [USB2PHY_PORT_HOST] = { 1730 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1731 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1732 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1733 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1734 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1735 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1736 } 1737 }, 1738 .chg_det = { 1739 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1740 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1741 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1742 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1743 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1744 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1745 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1746 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1747 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1748 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1749 }, 1750 } 1751 }; 1752 1753 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { 1754 { 1755 .reg = 0xff740000, 1756 .num_ports = 2, 1757 .phy_tuning = rk3562_usb2phy_tuning, 1758 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1759 .port_cfgs = { 1760 [USB2PHY_PORT_OTG] = { 1761 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1762 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1763 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1764 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1765 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1766 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1767 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1768 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1769 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1770 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1771 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1772 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1773 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1774 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1775 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1776 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1777 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1778 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1779 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1780 }, 1781 [USB2PHY_PORT_HOST] = { 1782 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, 1783 .ls_det_en = { 0x0110, 1, 1, 0, 1 }, 1784 .ls_det_st = { 0x0114, 1, 1, 0, 1 }, 1785 .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, 1786 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1787 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1788 } 1789 }, 1790 .chg_det = { 1791 .opmode = { 0x0100, 3, 0, 5, 1 }, 1792 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1793 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1794 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1795 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1796 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1797 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1798 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1799 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1800 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1801 }, 1802 }, 1803 { /* sentinel */ } 1804 }; 1805 1806 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1807 { 1808 .reg = 0xfe8a0000, 1809 .num_ports = 2, 1810 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1811 .port_cfgs = { 1812 [USB2PHY_PORT_OTG] = { 1813 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1814 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1815 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1816 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1817 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1818 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1819 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1820 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1821 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1822 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1823 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1824 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1825 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1826 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1827 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1828 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1829 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1830 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1831 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1832 }, 1833 [USB2PHY_PORT_HOST] = { 1834 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1835 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1836 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1837 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1838 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1839 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1840 } 1841 }, 1842 .chg_det = { 1843 .opmode = { 0x0000, 3, 0, 5, 1 }, 1844 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1845 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1846 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1847 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1848 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1849 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1850 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1851 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1852 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1853 }, 1854 }, 1855 { 1856 .reg = 0xfe8b0000, 1857 .num_ports = 2, 1858 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1859 .port_cfgs = { 1860 [USB2PHY_PORT_OTG] = { 1861 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1862 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1863 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1864 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1865 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1866 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1867 }, 1868 [USB2PHY_PORT_HOST] = { 1869 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1870 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1871 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1872 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1873 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1874 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1875 } 1876 }, 1877 }, 1878 { /* sentinel */ } 1879 }; 1880 1881 static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { 1882 { 1883 .reg = 0x0000, 1884 .num_ports = 1, 1885 .phy_tuning = rk3576_usb2phy_tuning, 1886 .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, 1887 .port_cfgs = { 1888 [USB2PHY_PORT_OTG] = { 1889 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, 1890 .ls_det_en = { 0x00c0, 0, 0, 0, 1 }, 1891 .ls_det_st = { 0x00c4, 0, 0, 0, 1 }, 1892 .ls_det_clr = { 0x00c8, 0, 0, 0, 1 }, 1893 .utmi_avalid = { 0x0080, 1, 1, 0, 1 }, 1894 .utmi_bvalid = { 0x0080, 0, 0, 0, 1 }, 1895 .utmi_iddig = { 0x0080, 6, 6, 0, 1 }, 1896 .utmi_ls = { 0x0080, 5, 4, 0, 1 }, 1897 } 1898 }, 1899 .chg_det = { 1900 .opmode = { 0x0000, 8, 0, 0x055, 0x001 }, 1901 .cp_det = { 0x0080, 8, 8, 0, 1 }, 1902 .dcp_det = { 0x0080, 8, 8, 0, 1 }, 1903 .dp_det = { 0x0080, 9, 9, 1, 0 }, 1904 .idm_sink_en = { 0x0010, 5, 5, 1, 0 }, 1905 .idp_sink_en = { 0x0010, 5, 5, 0, 1 }, 1906 .idp_src_en = { 0x0010, 14, 14, 0, 1 }, 1907 .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 }, 1908 .vdm_src_en = { 0x0010, 7, 6, 0, 3 }, 1909 .vdp_src_en = { 0x0010, 7, 6, 0, 3 }, 1910 }, 1911 }, 1912 { 1913 .reg = 0x2000, 1914 .num_ports = 1, 1915 .phy_tuning = rk3576_usb2phy_tuning, 1916 .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, 1917 .port_cfgs = { 1918 [USB2PHY_PORT_OTG] = { 1919 .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 }, 1920 .ls_det_en = { 0x20c0, 0, 0, 0, 1 }, 1921 .ls_det_st = { 0x20c4, 0, 0, 0, 1 }, 1922 .ls_det_clr = { 0x20c8, 0, 0, 0, 1 }, 1923 .utmi_avalid = { 0x2080, 1, 1, 0, 1 }, 1924 .utmi_bvalid = { 0x2080, 0, 0, 0, 1 }, 1925 .utmi_iddig = { 0x2080, 6, 6, 0, 1 }, 1926 .utmi_ls = { 0x2080, 5, 4, 0, 1 }, 1927 } 1928 }, 1929 }, 1930 { /* sentinel */ } 1931 }; 1932 1933 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1934 { 1935 .reg = 0x0000, 1936 .num_ports = 1, 1937 .phy_tuning = rk3588_usb2phy_tuning, 1938 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1939 .port_cfgs = { 1940 [USB2PHY_PORT_OTG] = { 1941 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1942 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1943 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1944 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1945 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, 1946 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, 1947 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1948 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1949 } 1950 }, 1951 .chg_det = { 1952 .opmode = { 0x0008, 2, 2, 1, 0 }, 1953 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1954 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1955 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1956 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1957 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1958 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1959 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1960 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1961 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1962 }, 1963 }, 1964 { 1965 .reg = 0x4000, 1966 .num_ports = 1, 1967 .phy_tuning = rk3588_usb2phy_tuning, 1968 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1969 .port_cfgs = { 1970 /* Select suspend control from controller */ 1971 [USB2PHY_PORT_OTG] = { 1972 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1973 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1974 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1975 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1976 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1977 } 1978 }, 1979 }, 1980 { 1981 .reg = 0x8000, 1982 .num_ports = 1, 1983 .phy_tuning = rk3588_usb2phy_tuning, 1984 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1985 .port_cfgs = { 1986 [USB2PHY_PORT_HOST] = { 1987 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1988 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1989 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1990 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1991 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1992 } 1993 }, 1994 }, 1995 { 1996 .reg = 0xc000, 1997 .num_ports = 1, 1998 .phy_tuning = rk3588_usb2phy_tuning, 1999 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 2000 .port_cfgs = { 2001 [USB2PHY_PORT_HOST] = { 2002 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 2003 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 2004 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 2005 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 2006 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 2007 } 2008 }, 2009 }, 2010 { /* sentinel */ } 2011 }; 2012 2013 static const struct udevice_id rockchip_usb2phy_ids[] = { 2014 #ifdef CONFIG_ROCKCHIP_PX30 2015 { .compatible = "rockchip,px30-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 2016 #endif 2017 #ifdef CONFIG_ROCKCHIP_RK1808 2018 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 2019 #endif 2020 #ifdef CONFIG_ROCKCHIP_RK3036 2021 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs }, 2022 #endif 2023 #if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126 2024 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 2025 #endif 2026 #ifdef CONFIG_ROCKCHIP_RK322X 2027 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 2028 #endif 2029 #ifdef CONFIG_ROCKCHIP_RK3308 2030 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 2031 #endif 2032 #ifdef CONFIG_ROCKCHIP_RK3328 2033 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 2034 #endif 2035 #ifdef CONFIG_ROCKCHIP_RK3368 2036 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 2037 #endif 2038 #ifdef CONFIG_ROCKCHIP_RK3399 2039 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 2040 #endif 2041 #ifdef CONFIG_ROCKCHIP_RK3506 2042 { .compatible = "rockchip,rk3506-usb2phy", .data = (ulong)&rk3506_phy_cfgs }, 2043 #endif 2044 #ifdef CONFIG_ROCKCHIP_RK3528 2045 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 2046 #endif 2047 #ifdef CONFIG_ROCKCHIP_RK3562 2048 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs }, 2049 #endif 2050 #ifdef CONFIG_ROCKCHIP_RK3568 2051 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 2052 #endif 2053 #ifdef CONFIG_ROCKCHIP_RK3576 2054 { .compatible = "rockchip,rk3576-usb2phy", .data = (ulong)&rk3576_phy_cfgs }, 2055 #endif 2056 #ifdef CONFIG_ROCKCHIP_RK3588 2057 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 2058 #endif 2059 #ifdef CONFIG_ROCKCHIP_RV1103B 2060 { .compatible = "rockchip,rv1103b-usb2phy", .data = (ulong)&rv1103b_phy_cfgs }, 2061 #endif 2062 #ifdef CONFIG_ROCKCHIP_RV1106 2063 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs }, 2064 #endif 2065 #ifdef CONFIG_ROCKCHIP_RV1108 2066 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 2067 #endif 2068 { } 2069 }; 2070 2071 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 2072 .name = "rockchip_usb2phy_port", 2073 .id = UCLASS_PHY, 2074 .ops = &rockchip_usb2phy_ops, 2075 }; 2076 2077 U_BOOT_DRIVER(rockchip_usb2phy) = { 2078 .name = "rockchip_usb2phy", 2079 .id = UCLASS_PHY, 2080 .of_match = rockchip_usb2phy_ids, 2081 .probe = rockchip_usb2phy_probe, 2082 .bind = rockchip_usb2phy_bind, 2083 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 2084 }; 2085