1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 19 #include "../usb/gadget/dwc2_udc_otg_priv.h" 20 21 #define U2PHY_BIT_WRITEABLE_SHIFT 16 22 #define CHG_DCD_MAX_RETRIES 6 23 #define CHG_PRI_MAX_RETRIES 2 24 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 25 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 26 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 27 28 struct rockchip_usb2phy; 29 30 enum power_supply_type { 31 POWER_SUPPLY_TYPE_UNKNOWN = 0, 32 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 33 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 34 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 35 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 36 }; 37 38 enum rockchip_usb2phy_port_id { 39 USB2PHY_PORT_OTG, 40 USB2PHY_PORT_HOST, 41 USB2PHY_NUM_PORTS, 42 }; 43 44 struct usb2phy_reg { 45 u32 offset; 46 u32 bitend; 47 u32 bitstart; 48 u32 disable; 49 u32 enable; 50 }; 51 52 /** 53 * struct rockchip_chg_det_reg: usb charger detect registers 54 * @cp_det: charging port detected successfully. 55 * @dcp_det: dedicated charging port detected successfully. 56 * @dp_det: assert data pin connect successfully. 57 * @idm_sink_en: open dm sink curren. 58 * @idp_sink_en: open dp sink current. 59 * @idp_src_en: open dm source current. 60 * @rdm_pdwn_en: open dm pull down resistor. 61 * @vdm_src_en: open dm voltage source. 62 * @vdp_src_en: open dp voltage source. 63 * @opmode: utmi operational mode. 64 */ 65 struct rockchip_chg_det_reg { 66 struct usb2phy_reg cp_det; 67 struct usb2phy_reg dcp_det; 68 struct usb2phy_reg dp_det; 69 struct usb2phy_reg idm_sink_en; 70 struct usb2phy_reg idp_sink_en; 71 struct usb2phy_reg idp_src_en; 72 struct usb2phy_reg rdm_pdwn_en; 73 struct usb2phy_reg vdm_src_en; 74 struct usb2phy_reg vdp_src_en; 75 struct usb2phy_reg opmode; 76 }; 77 78 /** 79 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 80 * @phy_sus: phy suspend register. 81 * @bvalid_det_en: vbus valid rise detection enable register. 82 * @bvalid_det_st: vbus valid rise detection status register. 83 * @bvalid_det_clr: vbus valid rise detection clear register. 84 * @ls_det_en: linestate detection enable register. 85 * @ls_det_st: linestate detection state register. 86 * @ls_det_clr: linestate detection clear register. 87 * @iddig_output: iddig output from grf. 88 * @iddig_en: utmi iddig select between grf and phy, 89 * 0: from phy; 1: from grf 90 * @idfall_det_en: id fall detection enable register. 91 * @idfall_det_st: id fall detection state register. 92 * @idfall_det_clr: id fall detection clear register. 93 * @idrise_det_en: id rise detection enable register. 94 * @idrise_det_st: id rise detection state register. 95 * @idrise_det_clr: id rise detection clear register. 96 * @utmi_avalid: utmi vbus avalid status register. 97 * @utmi_bvalid: utmi vbus bvalid status register. 98 * @utmi_iddig: otg port id pin status register. 99 * @utmi_ls: utmi linestate state register. 100 * @utmi_hstdet: utmi host disconnect register. 101 * @vbus_det_en: vbus detect function power down register. 102 */ 103 struct rockchip_usb2phy_port_cfg { 104 struct usb2phy_reg phy_sus; 105 struct usb2phy_reg bvalid_det_en; 106 struct usb2phy_reg bvalid_det_st; 107 struct usb2phy_reg bvalid_det_clr; 108 struct usb2phy_reg ls_det_en; 109 struct usb2phy_reg ls_det_st; 110 struct usb2phy_reg ls_det_clr; 111 struct usb2phy_reg iddig_output; 112 struct usb2phy_reg iddig_en; 113 struct usb2phy_reg idfall_det_en; 114 struct usb2phy_reg idfall_det_st; 115 struct usb2phy_reg idfall_det_clr; 116 struct usb2phy_reg idrise_det_en; 117 struct usb2phy_reg idrise_det_st; 118 struct usb2phy_reg idrise_det_clr; 119 struct usb2phy_reg utmi_avalid; 120 struct usb2phy_reg utmi_bvalid; 121 struct usb2phy_reg utmi_iddig; 122 struct usb2phy_reg utmi_ls; 123 struct usb2phy_reg utmi_hstdet; 124 struct usb2phy_reg vbus_det_en; 125 }; 126 127 /** 128 * struct rockchip_usb2phy_cfg: usb-phy configuration. 129 * @reg: the address offset of grf for usb-phy config. 130 * @num_ports: specify how many ports that the phy has. 131 * @phy_tuning: phy default parameters tunning. 132 * @clkout_ctl: keep on/turn off output clk of phy. 133 * @chg_det: charger detection registers. 134 */ 135 struct rockchip_usb2phy_cfg { 136 u32 reg; 137 u32 num_ports; 138 int (*phy_tuning)(struct rockchip_usb2phy *); 139 struct usb2phy_reg clkout_ctl; 140 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 141 const struct rockchip_chg_det_reg chg_det; 142 }; 143 144 /** 145 * @dcd_retries: The retry count used to track Data contact 146 * detection process. 147 * @primary_retries: The retry count used to do usb bc detection 148 * primary stage. 149 * @grf: General Register Files register base. 150 * @usbgrf_base : USB General Register Files register base. 151 * @phy_cfg: phy register configuration, assigned by driver data. 152 */ 153 struct rockchip_usb2phy { 154 u8 dcd_retries; 155 u8 primary_retries; 156 struct regmap *grf_base; 157 struct regmap *usbgrf_base; 158 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 159 const struct rockchip_usb2phy_cfg *phy_cfg; 160 }; 161 162 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 163 { 164 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 165 } 166 167 static inline int property_enable(struct regmap *base, 168 const struct usb2phy_reg *reg, bool en) 169 { 170 u32 val, mask, tmp; 171 172 tmp = en ? reg->enable : reg->disable; 173 mask = GENMASK(reg->bitend, reg->bitstart); 174 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 175 176 return regmap_write(base, reg->offset, val); 177 } 178 179 static inline bool property_enabled(struct regmap *base, 180 const struct usb2phy_reg *reg) 181 { 182 u32 tmp, orig; 183 u32 mask = GENMASK(reg->bitend, reg->bitstart); 184 185 regmap_read(base, reg->offset, &orig); 186 187 tmp = (orig & mask) >> reg->bitstart; 188 189 return tmp == reg->enable; 190 } 191 192 static const char *chg_to_string(enum power_supply_type chg_type) 193 { 194 switch (chg_type) { 195 case POWER_SUPPLY_TYPE_USB: 196 return "USB_SDP_CHARGER"; 197 case POWER_SUPPLY_TYPE_USB_DCP: 198 return "USB_DCP_CHARGER"; 199 case POWER_SUPPLY_TYPE_USB_CDP: 200 return "USB_CDP_CHARGER"; 201 case POWER_SUPPLY_TYPE_USB_FLOATING: 202 return "USB_FLOATING_CHARGER"; 203 default: 204 return "INVALID_CHARGER"; 205 } 206 } 207 208 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 209 bool en) 210 { 211 struct regmap *base = get_reg_base(rphy); 212 213 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 214 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 215 } 216 217 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 218 bool en) 219 { 220 struct regmap *base = get_reg_base(rphy); 221 222 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 223 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 224 } 225 226 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 227 bool en) 228 { 229 struct regmap *base = get_reg_base(rphy); 230 231 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 232 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 233 } 234 235 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 236 { 237 bool vout = false; 238 struct regmap *base = get_reg_base(rphy); 239 240 while (rphy->primary_retries--) { 241 /* voltage source on DP, probe on DM */ 242 rockchip_chg_enable_primary_det(rphy, true); 243 mdelay(CHG_PRIMARY_DET_TIME); 244 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 245 if (vout) 246 break; 247 } 248 249 rockchip_chg_enable_primary_det(rphy, false); 250 return vout; 251 } 252 253 int rockchip_chg_get_type(void) 254 { 255 const struct rockchip_usb2phy_port_cfg *port_cfg; 256 enum power_supply_type chg_type; 257 struct rockchip_usb2phy *rphy; 258 struct udevice *udev; 259 struct regmap *base; 260 bool is_dcd, vout; 261 int ret; 262 263 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 264 if (ret == -ENODEV) { 265 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 266 return ret; 267 } 268 269 rphy = dev_get_priv(udev); 270 base = get_reg_base(rphy); 271 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 272 273 /* Check USB-Vbus status first */ 274 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 275 pr_info("%s: no charger found\n", __func__); 276 return POWER_SUPPLY_TYPE_UNKNOWN; 277 } 278 279 /* Suspend USB-PHY and put the controller in non-driving mode */ 280 property_enable(base, &port_cfg->phy_sus, true); 281 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 282 283 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 284 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 285 286 /* stage 1, start DCD processing stage */ 287 rockchip_chg_enable_dcd(rphy, true); 288 289 while (rphy->dcd_retries--) { 290 mdelay(CHG_DCD_POLL_TIME); 291 292 /* get data contact detection status */ 293 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 294 295 if (is_dcd || !rphy->dcd_retries) { 296 /* 297 * stage 2, turn off DCD circuitry, then 298 * voltage source on DP, probe on DM. 299 */ 300 rockchip_chg_enable_dcd(rphy, false); 301 rockchip_chg_enable_primary_det(rphy, true); 302 break; 303 } 304 } 305 306 mdelay(CHG_PRIMARY_DET_TIME); 307 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 308 rockchip_chg_enable_primary_det(rphy, false); 309 if (vout) { 310 /* stage 3, voltage source on DM, probe on DP */ 311 rockchip_chg_enable_secondary_det(rphy, true); 312 } else { 313 if (!rphy->dcd_retries) { 314 /* floating charger found */ 315 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 316 goto out; 317 } else { 318 /* 319 * Retry some times to make sure that it's 320 * really a USB SDP charger. 321 */ 322 vout = rockchip_chg_primary_det_retry(rphy); 323 if (vout) { 324 /* stage 3, voltage source on DM, probe on DP */ 325 rockchip_chg_enable_secondary_det(rphy, true); 326 } else { 327 /* USB SDP charger found */ 328 chg_type = POWER_SUPPLY_TYPE_USB; 329 goto out; 330 } 331 } 332 } 333 334 mdelay(CHG_SECONDARY_DET_TIME); 335 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 336 /* stage 4, turn off voltage source */ 337 rockchip_chg_enable_secondary_det(rphy, false); 338 if (vout) 339 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 340 else 341 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 342 343 out: 344 /* Resume USB-PHY and put the controller in normal mode */ 345 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 346 property_enable(base, &port_cfg->phy_sus, false); 347 348 debug("charger is %s\n", chg_to_string(chg_type)); 349 350 return chg_type; 351 } 352 353 int rockchip_u2phy_vbus_detect(void) 354 { 355 int chg_type; 356 357 chg_type = rockchip_chg_get_type(); 358 359 return (chg_type == POWER_SUPPLY_TYPE_USB || 360 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 361 } 362 363 void otg_phy_init(struct dwc2_udc *dev) 364 { 365 const struct rockchip_usb2phy_port_cfg *port_cfg; 366 struct rockchip_usb2phy *rphy; 367 struct udevice *udev; 368 struct regmap *base; 369 int ret; 370 371 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 372 if (ret == -ENODEV) { 373 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 374 return; 375 } 376 377 rphy = dev_get_priv(udev); 378 base = get_reg_base(rphy); 379 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 380 381 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 382 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 383 384 /* Reset USB-PHY */ 385 property_enable(base, &port_cfg->phy_sus, true); 386 udelay(20); 387 property_enable(base, &port_cfg->phy_sus, false); 388 mdelay(2); 389 } 390 391 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 392 { 393 struct udevice *parent = phy->dev->parent; 394 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 395 const struct rockchip_usb2phy_port_cfg *port_cfg; 396 struct regmap *base = get_reg_base(rphy); 397 struct udevice *vbus = NULL; 398 bool iddig = true; 399 400 if (phy->id == USB2PHY_PORT_HOST) { 401 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 402 } else if (phy->id == USB2PHY_PORT_OTG) { 403 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 404 if (port_cfg->utmi_iddig.offset) { 405 iddig = property_enabled(base, &port_cfg->utmi_iddig); 406 if (!iddig) 407 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 408 } 409 } 410 411 return vbus; 412 } 413 414 static int rockchip_usb2phy_init(struct phy *phy) 415 { 416 struct udevice *parent = phy->dev->parent; 417 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 418 const struct rockchip_usb2phy_port_cfg *port_cfg; 419 struct regmap *base = get_reg_base(rphy); 420 421 if (phy->id == USB2PHY_PORT_OTG) { 422 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 423 } else if (phy->id == USB2PHY_PORT_HOST) { 424 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 425 } else { 426 dev_err(phy->dev, "phy id %lu not support", phy->id); 427 return -EINVAL; 428 } 429 430 property_enable(base, &port_cfg->phy_sus, false); 431 432 /* waiting for the utmi_clk to become stable */ 433 udelay(2000); 434 435 return 0; 436 } 437 438 static int rockchip_usb2phy_exit(struct phy *phy) 439 { 440 struct udevice *parent = phy->dev->parent; 441 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 442 const struct rockchip_usb2phy_port_cfg *port_cfg; 443 struct regmap *base = get_reg_base(rphy); 444 445 if (phy->id == USB2PHY_PORT_OTG) { 446 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 447 } else if (phy->id == USB2PHY_PORT_HOST) { 448 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 449 } else { 450 dev_err(phy->dev, "phy id %lu not support", phy->id); 451 return -EINVAL; 452 } 453 454 property_enable(base, &port_cfg->phy_sus, true); 455 456 return 0; 457 } 458 459 static int rockchip_usb2phy_power_on(struct phy *phy) 460 { 461 struct udevice *vbus = NULL; 462 int ret; 463 464 vbus = rockchip_usb2phy_check_vbus(phy); 465 if (vbus) { 466 ret = regulator_set_enable(vbus, true); 467 if (ret) { 468 pr_err("%s: Failed to set VBus supply\n", __func__); 469 return ret; 470 } 471 } 472 473 return 0; 474 } 475 476 static int rockchip_usb2phy_power_off(struct phy *phy) 477 { 478 struct udevice *vbus = NULL; 479 int ret; 480 481 vbus = rockchip_usb2phy_check_vbus(phy); 482 if (vbus) { 483 ret = regulator_set_enable(vbus, false); 484 if (ret) { 485 pr_err("%s: Failed to set VBus supply\n", __func__); 486 return ret; 487 } 488 } 489 490 return 0; 491 } 492 493 static int rockchip_usb2phy_of_xlate(struct phy *phy, 494 struct ofnode_phandle_args *args) 495 { 496 const char *dev_name = phy->dev->name; 497 struct udevice *parent = phy->dev->parent; 498 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 499 500 if (!strcasecmp(dev_name, "host-port")) { 501 phy->id = USB2PHY_PORT_HOST; 502 device_get_supply_regulator(phy->dev, "phy-supply", 503 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 504 } else if (!strcasecmp(dev_name, "otg-port")) { 505 phy->id = USB2PHY_PORT_OTG; 506 device_get_supply_regulator(phy->dev, "phy-supply", 507 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 508 } else { 509 pr_err("%s: invalid dev name\n", __func__); 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static int rockchip_usb2phy_bind(struct udevice *dev) 517 { 518 struct udevice *child; 519 ofnode subnode; 520 const char *node_name; 521 int ret; 522 523 dev_for_each_subnode(subnode, dev) { 524 if (!ofnode_valid(subnode)) { 525 debug("%s: %s subnode not found", __func__, dev->name); 526 return -ENXIO; 527 } 528 529 node_name = ofnode_get_name(subnode); 530 debug("%s: subnode %s\n", __func__, node_name); 531 532 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 533 node_name, subnode, &child); 534 if (ret) { 535 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 536 __func__, node_name); 537 return ret; 538 } 539 } 540 541 return 0; 542 } 543 544 static int rockchip_usb2phy_probe(struct udevice *dev) 545 { 546 const struct rockchip_usb2phy_cfg *phy_cfgs; 547 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 548 struct udevice *parent = dev->parent; 549 struct udevice *syscon; 550 struct resource res; 551 u32 reg, index; 552 int ret; 553 554 if (!strncmp(parent->name, "root_driver", 11) && 555 dev_read_bool(dev, "rockchip,grf")) { 556 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 557 "rockchip,grf", &syscon); 558 if (ret) { 559 dev_err(dev, "get syscon grf failed\n"); 560 return ret; 561 } 562 563 rphy->grf_base = syscon_get_regmap(syscon); 564 } else { 565 rphy->grf_base = syscon_get_regmap(parent); 566 } 567 568 if (rphy->grf_base <= 0) { 569 dev_err(dev, "get syscon grf regmap failed\n"); 570 return -EINVAL; 571 } 572 573 if (dev_read_bool(dev, "rockchip,usbgrf")) { 574 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 575 "rockchip,usbgrf", &syscon); 576 if (ret) { 577 dev_err(dev, "get syscon usbgrf failed\n"); 578 return ret; 579 } 580 581 rphy->usbgrf_base = syscon_get_regmap(syscon); 582 if (rphy->usbgrf_base <= 0) { 583 dev_err(dev, "get syscon usbgrf regmap failed\n"); 584 return -EINVAL; 585 } 586 } else { 587 rphy->usbgrf_base = NULL; 588 } 589 590 if (!strncmp(parent->name, "root_driver", 11)) { 591 ret = dev_read_resource(dev, 0, &res); 592 reg = res.start; 593 } else { 594 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 595 } 596 597 if (ret) { 598 dev_err(dev, "could not read reg\n"); 599 return -EINVAL; 600 } 601 602 phy_cfgs = 603 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 604 if (!phy_cfgs) { 605 dev_err(dev, "unable to get phy_cfgs\n"); 606 return -EINVAL; 607 } 608 609 /* find out a proper config which can be matched with dt. */ 610 index = 0; 611 while (phy_cfgs[index].reg) { 612 if (phy_cfgs[index].reg == reg) { 613 rphy->phy_cfg = &phy_cfgs[index]; 614 break; 615 } 616 ++index; 617 } 618 619 if (!rphy->phy_cfg) { 620 dev_err(dev, "no phy-config can be matched\n"); 621 return -EINVAL; 622 } 623 624 if (rphy->phy_cfg->phy_tuning) 625 rphy->phy_cfg->phy_tuning(rphy); 626 627 return 0; 628 } 629 630 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 631 { 632 struct regmap *base = get_reg_base(rphy); 633 int ret = 0; 634 635 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 636 if (rphy->phy_cfg->reg == 0x760) 637 ret = regmap_write(base, 0x76c, 0x00070004); 638 639 return ret; 640 } 641 642 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 643 { 644 struct regmap *base = get_reg_base(rphy); 645 unsigned int tmp, orig; 646 int ret; 647 648 if (soc_is_rk3308bs()) { 649 /* Enable otg/host port pre-emphasis during non-chirp phase */ 650 ret = regmap_read(base, 0, &orig); 651 if (ret) 652 return ret; 653 tmp = orig & ~GENMASK(2, 0); 654 tmp |= BIT(2) & GENMASK(2, 0); 655 ret = regmap_write(base, 0, tmp); 656 if (ret) 657 return ret; 658 659 /* Set otg port squelch trigger point configure to 100mv */ 660 ret = regmap_read(base, 0x004, &orig); 661 if (ret) 662 return ret; 663 tmp = orig & ~GENMASK(7, 5); 664 tmp |= 0x40 & GENMASK(7, 5); 665 ret = regmap_write(base, 0x004, tmp); 666 if (ret) 667 return ret; 668 669 ret = regmap_read(base, 0x008, &orig); 670 if (ret) 671 return ret; 672 tmp = orig & ~BIT(0); 673 tmp |= 0x1 & BIT(0); 674 ret = regmap_write(base, 0x008, tmp); 675 if (ret) 676 return ret; 677 678 /* Enable host port pre-emphasis during non-chirp phase */ 679 ret = regmap_read(base, 0x400, &orig); 680 if (ret) 681 return ret; 682 tmp = orig & ~GENMASK(2, 0); 683 tmp |= BIT(2) & GENMASK(2, 0); 684 ret = regmap_write(base, 0x400, tmp); 685 if (ret) 686 return ret; 687 688 /* Set host port squelch trigger point configure to 100mv */ 689 ret = regmap_read(base, 0x404, &orig); 690 if (ret) 691 return ret; 692 tmp = orig & ~GENMASK(7, 5); 693 tmp |= 0x40 & GENMASK(7, 5); 694 ret = regmap_write(base, 0x404, tmp); 695 if (ret) 696 return ret; 697 698 ret = regmap_read(base, 0x408, &orig); 699 if (ret) 700 return ret; 701 tmp = orig & ~BIT(0); 702 tmp |= 0x1 & BIT(0); 703 ret = regmap_write(base, 0x408, tmp); 704 if (ret) 705 return ret; 706 } 707 708 return 0; 709 } 710 711 static struct phy_ops rockchip_usb2phy_ops = { 712 .init = rockchip_usb2phy_init, 713 .exit = rockchip_usb2phy_exit, 714 .power_on = rockchip_usb2phy_power_on, 715 .power_off = rockchip_usb2phy_power_off, 716 .of_xlate = rockchip_usb2phy_of_xlate, 717 }; 718 719 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 720 { 721 .reg = 0x100, 722 .num_ports = 2, 723 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 724 .port_cfgs = { 725 [USB2PHY_PORT_OTG] = { 726 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 727 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 728 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 729 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 730 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 731 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 732 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 733 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 734 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 735 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 736 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 737 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 738 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 739 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 740 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 741 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 742 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 743 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 744 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 745 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 746 }, 747 [USB2PHY_PORT_HOST] = { 748 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 749 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 750 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 751 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 752 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 753 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 754 } 755 }, 756 .chg_det = { 757 .opmode = { 0x0100, 3, 0, 5, 1 }, 758 .cp_det = { 0x0120, 24, 24, 0, 1 }, 759 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 760 .dp_det = { 0x0120, 25, 25, 0, 1 }, 761 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 762 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 763 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 764 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 765 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 766 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 767 }, 768 }, 769 { /* sentinel */ } 770 }; 771 772 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 773 { 774 .reg = 0x17c, 775 .num_ports = 2, 776 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 777 .port_cfgs = { 778 [USB2PHY_PORT_OTG] = { 779 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 780 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 781 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 782 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 783 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 784 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 785 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 786 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 787 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 788 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 789 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 790 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 791 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 792 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 793 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 794 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 795 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 796 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 797 }, 798 [USB2PHY_PORT_HOST] = { 799 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 800 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 801 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 802 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 803 } 804 }, 805 .chg_det = { 806 .opmode = { 0x017c, 3, 0, 5, 1 }, 807 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 808 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 809 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 810 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 811 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 812 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 813 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 814 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 815 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 816 }, 817 }, 818 { /* sentinel */ } 819 }; 820 821 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 822 { 823 .reg = 0x760, 824 .num_ports = 2, 825 .phy_tuning = rk322x_usb2phy_tuning, 826 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 827 .port_cfgs = { 828 [USB2PHY_PORT_OTG] = { 829 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 830 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 831 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 832 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 833 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 834 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 835 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 836 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 837 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 838 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 839 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 840 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 841 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 842 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 843 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 844 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 845 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 846 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 847 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 848 }, 849 [USB2PHY_PORT_HOST] = { 850 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 851 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 852 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 853 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 854 } 855 }, 856 .chg_det = { 857 .opmode = { 0x0760, 3, 0, 5, 1 }, 858 .cp_det = { 0x0884, 4, 4, 0, 1 }, 859 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 860 .dp_det = { 0x0884, 5, 5, 0, 1 }, 861 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 862 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 863 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 864 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 865 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 866 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 867 }, 868 }, 869 { 870 .reg = 0x800, 871 .num_ports = 2, 872 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 873 .port_cfgs = { 874 [USB2PHY_PORT_OTG] = { 875 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 876 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 877 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 878 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 879 }, 880 [USB2PHY_PORT_HOST] = { 881 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 882 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 883 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 884 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 885 } 886 }, 887 }, 888 { /* sentinel */ } 889 }; 890 891 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 892 { 893 .reg = 0x100, 894 .num_ports = 2, 895 .phy_tuning = rk3308_usb2phy_tuning, 896 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 897 .port_cfgs = { 898 [USB2PHY_PORT_OTG] = { 899 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 900 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 901 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 902 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 903 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 904 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 905 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 906 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 907 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 908 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 909 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 910 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 911 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 912 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 913 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 914 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 915 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 916 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 917 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 918 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 919 }, 920 [USB2PHY_PORT_HOST] = { 921 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 922 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 923 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 924 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 925 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 926 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 927 } 928 }, 929 .chg_det = { 930 .opmode = { 0x0100, 3, 0, 5, 1 }, 931 .cp_det = { 0x0120, 24, 24, 0, 1 }, 932 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 933 .dp_det = { 0x0120, 25, 25, 0, 1 }, 934 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 935 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 936 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 937 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 938 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 939 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 940 }, 941 }, 942 { /* sentinel */ } 943 }; 944 945 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 946 { 947 .reg = 0x100, 948 .num_ports = 2, 949 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 950 .port_cfgs = { 951 [USB2PHY_PORT_OTG] = { 952 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 953 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 954 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 955 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 956 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 957 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 958 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 959 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 960 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 961 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 962 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 963 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 964 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 965 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 966 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 967 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 968 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 969 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 970 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 971 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 972 }, 973 [USB2PHY_PORT_HOST] = { 974 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 975 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 976 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 977 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 978 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 979 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 980 } 981 }, 982 .chg_det = { 983 .opmode = { 0x0100, 3, 0, 5, 1 }, 984 .cp_det = { 0x0120, 24, 24, 0, 1 }, 985 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 986 .dp_det = { 0x0120, 25, 25, 0, 1 }, 987 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 988 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 989 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 990 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 991 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 992 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 993 }, 994 }, 995 { /* sentinel */ } 996 }; 997 998 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 999 { 1000 .reg = 0x700, 1001 .num_ports = 2, 1002 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1003 .port_cfgs = { 1004 [USB2PHY_PORT_OTG] = { 1005 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1006 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1007 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1008 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1009 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1010 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1011 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1012 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1013 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1014 }, 1015 [USB2PHY_PORT_HOST] = { 1016 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1017 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1018 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1019 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1020 } 1021 }, 1022 .chg_det = { 1023 .opmode = { 0x0700, 3, 0, 5, 1 }, 1024 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1025 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1026 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1027 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1028 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1029 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1030 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1031 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1032 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1033 }, 1034 }, 1035 { /* sentinel */ } 1036 }; 1037 1038 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1039 { 1040 .reg = 0xe450, 1041 .num_ports = 2, 1042 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1043 .port_cfgs = { 1044 [USB2PHY_PORT_OTG] = { 1045 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1046 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1047 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1048 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1049 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1050 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1051 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1052 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1053 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1054 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1055 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1056 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1057 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1058 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1059 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1060 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1061 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1062 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1063 }, 1064 [USB2PHY_PORT_HOST] = { 1065 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1066 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1067 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1068 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1069 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1070 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1071 } 1072 }, 1073 .chg_det = { 1074 .opmode = { 0xe454, 3, 0, 5, 1 }, 1075 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1076 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1077 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1078 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1079 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1080 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1081 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1082 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1083 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1084 }, 1085 }, 1086 { 1087 .reg = 0xe460, 1088 .num_ports = 2, 1089 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1090 .port_cfgs = { 1091 [USB2PHY_PORT_OTG] = { 1092 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1093 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1094 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1095 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1096 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1097 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1098 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1099 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1100 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1101 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1102 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1103 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1104 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1105 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1106 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1107 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1108 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1109 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1110 }, 1111 [USB2PHY_PORT_HOST] = { 1112 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1113 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1114 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1115 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1116 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1117 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1118 } 1119 }, 1120 .chg_det = { 1121 .opmode = { 0xe464, 3, 0, 5, 1 }, 1122 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1123 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1124 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1125 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1126 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1127 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1128 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1129 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1130 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1131 }, 1132 }, 1133 { /* sentinel */ } 1134 }; 1135 1136 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1137 { 1138 .reg = 0x100, 1139 .num_ports = 2, 1140 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1141 .port_cfgs = { 1142 [USB2PHY_PORT_OTG] = { 1143 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1144 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1145 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1146 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1147 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1148 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1149 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1150 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1151 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1152 }, 1153 [USB2PHY_PORT_HOST] = { 1154 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1155 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1156 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1157 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1158 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1159 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1160 } 1161 }, 1162 .chg_det = { 1163 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1164 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1165 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1166 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1167 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1168 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1169 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1170 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1171 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1172 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1173 }, 1174 }, 1175 { /* sentinel */ } 1176 }; 1177 1178 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1179 { 1180 .reg = 0xfe8a0000, 1181 .num_ports = 2, 1182 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1183 .port_cfgs = { 1184 [USB2PHY_PORT_OTG] = { 1185 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1186 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1187 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1188 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1189 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1190 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1191 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1192 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1193 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1194 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1195 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1196 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1197 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1198 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1199 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1200 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1201 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1202 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1203 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1204 }, 1205 [USB2PHY_PORT_HOST] = { 1206 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1207 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1208 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1209 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1210 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1211 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1212 } 1213 }, 1214 .chg_det = { 1215 .opmode = { 0x0000, 3, 0, 5, 1 }, 1216 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1217 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1218 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1219 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1220 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1221 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1222 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1223 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1224 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1225 }, 1226 }, 1227 { 1228 .reg = 0xfe8b0000, 1229 .num_ports = 2, 1230 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1231 .port_cfgs = { 1232 [USB2PHY_PORT_OTG] = { 1233 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1234 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1235 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1236 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1237 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1238 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1239 }, 1240 [USB2PHY_PORT_HOST] = { 1241 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1242 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1243 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1244 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1245 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1246 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1247 } 1248 }, 1249 }, 1250 { /* sentinel */ } 1251 }; 1252 static const struct udevice_id rockchip_usb2phy_ids[] = { 1253 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1254 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1255 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1256 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1257 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1258 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1259 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1260 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1261 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1262 { } 1263 }; 1264 1265 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1266 .name = "rockchip_usb2phy_port", 1267 .id = UCLASS_PHY, 1268 .ops = &rockchip_usb2phy_ops, 1269 }; 1270 1271 U_BOOT_DRIVER(rockchip_usb2phy) = { 1272 .name = "rockchip_usb2phy", 1273 .id = UCLASS_PHY, 1274 .of_match = rockchip_usb2phy_ids, 1275 .probe = rockchip_usb2phy_probe, 1276 .bind = rockchip_usb2phy_bind, 1277 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1278 }; 1279