1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <generic-phy.h> 10 #include <syscon.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 14 #include "../usb/gadget/dwc2_udc_otg_priv.h" 15 16 #define U2PHY_BIT_WRITEABLE_SHIFT 16 17 #define CHG_DCD_MAX_RETRIES 6 18 #define CHG_PRI_MAX_RETRIES 2 19 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 20 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 21 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 22 23 struct rockchip_usb2phy; 24 25 enum power_supply_type { 26 POWER_SUPPLY_TYPE_UNKNOWN = 0, 27 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 28 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 29 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 30 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 31 }; 32 33 enum rockchip_usb2phy_port_id { 34 USB2PHY_PORT_OTG, 35 USB2PHY_PORT_HOST, 36 USB2PHY_NUM_PORTS, 37 }; 38 39 struct usb2phy_reg { 40 u32 offset; 41 u32 bitend; 42 u32 bitstart; 43 u32 disable; 44 u32 enable; 45 }; 46 47 /** 48 * struct rockchip_chg_det_reg: usb charger detect registers 49 * @cp_det: charging port detected successfully. 50 * @dcp_det: dedicated charging port detected successfully. 51 * @dp_det: assert data pin connect successfully. 52 * @idm_sink_en: open dm sink curren. 53 * @idp_sink_en: open dp sink current. 54 * @idp_src_en: open dm source current. 55 * @rdm_pdwn_en: open dm pull down resistor. 56 * @vdm_src_en: open dm voltage source. 57 * @vdp_src_en: open dp voltage source. 58 * @opmode: utmi operational mode. 59 */ 60 struct rockchip_chg_det_reg { 61 struct usb2phy_reg cp_det; 62 struct usb2phy_reg dcp_det; 63 struct usb2phy_reg dp_det; 64 struct usb2phy_reg idm_sink_en; 65 struct usb2phy_reg idp_sink_en; 66 struct usb2phy_reg idp_src_en; 67 struct usb2phy_reg rdm_pdwn_en; 68 struct usb2phy_reg vdm_src_en; 69 struct usb2phy_reg vdp_src_en; 70 struct usb2phy_reg opmode; 71 }; 72 73 /** 74 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 75 * @phy_sus: phy suspend register. 76 * @bvalid_det_en: vbus valid rise detection enable register. 77 * @bvalid_det_st: vbus valid rise detection status register. 78 * @bvalid_det_clr: vbus valid rise detection clear register. 79 * @ls_det_en: linestate detection enable register. 80 * @ls_det_st: linestate detection state register. 81 * @ls_det_clr: linestate detection clear register. 82 * @iddig_output: iddig output from grf. 83 * @iddig_en: utmi iddig select between grf and phy, 84 * 0: from phy; 1: from grf 85 * @idfall_det_en: id fall detection enable register. 86 * @idfall_det_st: id fall detection state register. 87 * @idfall_det_clr: id fall detection clear register. 88 * @idrise_det_en: id rise detection enable register. 89 * @idrise_det_st: id rise detection state register. 90 * @idrise_det_clr: id rise detection clear register. 91 * @utmi_avalid: utmi vbus avalid status register. 92 * @utmi_bvalid: utmi vbus bvalid status register. 93 * @utmi_iddig: otg port id pin status register. 94 * @utmi_ls: utmi linestate state register. 95 * @utmi_hstdet: utmi host disconnect register. 96 * @vbus_det_en: vbus detect function power down register. 97 */ 98 struct rockchip_usb2phy_port_cfg { 99 struct usb2phy_reg phy_sus; 100 struct usb2phy_reg bvalid_det_en; 101 struct usb2phy_reg bvalid_det_st; 102 struct usb2phy_reg bvalid_det_clr; 103 struct usb2phy_reg ls_det_en; 104 struct usb2phy_reg ls_det_st; 105 struct usb2phy_reg ls_det_clr; 106 struct usb2phy_reg iddig_output; 107 struct usb2phy_reg iddig_en; 108 struct usb2phy_reg idfall_det_en; 109 struct usb2phy_reg idfall_det_st; 110 struct usb2phy_reg idfall_det_clr; 111 struct usb2phy_reg idrise_det_en; 112 struct usb2phy_reg idrise_det_st; 113 struct usb2phy_reg idrise_det_clr; 114 struct usb2phy_reg utmi_avalid; 115 struct usb2phy_reg utmi_bvalid; 116 struct usb2phy_reg utmi_iddig; 117 struct usb2phy_reg utmi_ls; 118 struct usb2phy_reg utmi_hstdet; 119 struct usb2phy_reg vbus_det_en; 120 }; 121 122 /** 123 * struct rockchip_usb2phy_cfg: usb-phy configuration. 124 * @reg: the address offset of grf for usb-phy config. 125 * @num_ports: specify how many ports that the phy has. 126 * @phy_tuning: phy default parameters tunning. 127 * @clkout_ctl: keep on/turn off output clk of phy. 128 * @chg_det: charger detection registers. 129 */ 130 struct rockchip_usb2phy_cfg { 131 u32 reg; 132 u32 num_ports; 133 int (*phy_tuning)(struct rockchip_usb2phy *); 134 struct usb2phy_reg clkout_ctl; 135 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 136 const struct rockchip_chg_det_reg chg_det; 137 }; 138 139 /** 140 * @dcd_retries: The retry count used to track Data contact 141 * detection process. 142 * @primary_retries: The retry count used to do usb bc detection 143 * primary stage. 144 * @grf: General Register Files register base. 145 * @usbgrf_base : USB General Register Files register base. 146 * @phy_cfg: phy register configuration, assigned by driver data. 147 */ 148 struct rockchip_usb2phy { 149 u8 dcd_retries; 150 u8 primary_retries; 151 void __iomem *grf_base; 152 void __iomem *usbgrf_base; 153 const struct rockchip_usb2phy_cfg *phy_cfg; 154 }; 155 156 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 157 { 158 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 159 } 160 161 static inline int property_enable(void __iomem *base, 162 const struct usb2phy_reg *reg, bool en) 163 { 164 u32 val, mask, tmp; 165 166 tmp = en ? reg->enable : reg->disable; 167 mask = GENMASK(reg->bitend, reg->bitstart); 168 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 169 170 return writel(val, base + reg->offset); 171 } 172 173 static inline bool property_enabled(void __iomem *base, 174 const struct usb2phy_reg *reg) 175 { 176 u32 tmp, orig; 177 u32 mask = GENMASK(reg->bitend, reg->bitstart); 178 179 orig = readl(base + reg->offset); 180 181 tmp = (orig & mask) >> reg->bitstart; 182 183 return tmp == reg->enable; 184 } 185 186 static int rockchip_usb2phy_parse(struct rockchip_usb2phy *rphy) 187 { 188 const struct rockchip_usb2phy_cfg *phy_cfgs; 189 ofnode u2phy_node = ofnode_null(); 190 ofnode grf_node = ofnode_null(); 191 void __iomem *usbgrf_base = NULL; 192 void __iomem *grf_base = NULL; 193 struct udevice *udev; 194 fdt_size_t size; 195 u32 reg, index; 196 int ret; 197 198 memset((void *)rphy, 0, sizeof(struct rockchip_usb2phy)); 199 200 u2phy_node = ofnode_path("/usb2-phy"); 201 if (ofnode_valid(u2phy_node)) { 202 if (ofnode_read_bool(u2phy_node, "rockchip,grf")) 203 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 204 205 if (ofnode_read_bool(u2phy_node, "rockchip,usbgrf")) 206 usbgrf_base = 207 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 208 else 209 usbgrf_base = NULL; 210 } else { 211 grf_node = ofnode_path("/syscon-usb"); 212 if (ofnode_valid(grf_node)) 213 grf_base = (void __iomem *) 214 ofnode_get_addr_size(grf_node, "reg", &size); 215 u2phy_node = ofnode_find_subnode(grf_node, "usb2-phy"); 216 } 217 218 if (!grf_base && !usbgrf_base) { 219 error("%s: get grf/usbgrf node failed\n", __func__); 220 return -EINVAL; 221 } 222 223 if (!ofnode_valid(u2phy_node)) { 224 error("%s: missing u2phy node\n", __func__); 225 return -EINVAL; 226 } 227 228 if (ofnode_read_u32(u2phy_node, "reg", ®)) { 229 error("%s: could not read reg from u2phy node\n", __func__); 230 return -EINVAL; 231 } 232 233 ret = uclass_get_device_by_ofnode(UCLASS_PHY, u2phy_node, &udev); 234 if (ret) { 235 error("%s: get u2phy node failed: %d\n", __func__, ret); 236 return -ENODEV; 237 } 238 239 phy_cfgs = 240 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(udev); 241 if (!phy_cfgs) { 242 error("%s: unable to get phy_cfgs\n", __func__); 243 return -EINVAL; 244 } 245 246 /* find out a proper config which can be matched with dt. */ 247 index = 0; 248 while (phy_cfgs[index].reg) { 249 if (phy_cfgs[index].reg == reg) { 250 rphy->phy_cfg = &phy_cfgs[index]; 251 break; 252 } 253 ++index; 254 } 255 256 if (!rphy->phy_cfg) { 257 error("%s: no phy-config can be matched\n", __func__); 258 return -EINVAL; 259 } 260 261 rphy->grf_base = grf_base; 262 rphy->usbgrf_base = usbgrf_base; 263 264 return 0; 265 } 266 267 static const char *chg_to_string(enum power_supply_type chg_type) 268 { 269 switch (chg_type) { 270 case POWER_SUPPLY_TYPE_USB: 271 return "USB_SDP_CHARGER"; 272 case POWER_SUPPLY_TYPE_USB_DCP: 273 return "USB_DCP_CHARGER"; 274 case POWER_SUPPLY_TYPE_USB_CDP: 275 return "USB_CDP_CHARGER"; 276 case POWER_SUPPLY_TYPE_USB_FLOATING: 277 return "USB_FLOATING_CHARGER"; 278 default: 279 return "INVALID_CHARGER"; 280 } 281 } 282 283 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 284 bool en) 285 { 286 void __iomem *base = get_reg_base(rphy); 287 288 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 289 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 290 } 291 292 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 293 bool en) 294 { 295 void __iomem *base = get_reg_base(rphy); 296 297 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 298 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 299 } 300 301 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 302 bool en) 303 { 304 void __iomem *base = get_reg_base(rphy); 305 306 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 307 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 308 } 309 310 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 311 { 312 bool vout = false; 313 314 while (rphy->primary_retries--) { 315 /* voltage source on DP, probe on DM */ 316 rockchip_chg_enable_primary_det(rphy, true); 317 mdelay(CHG_PRIMARY_DET_TIME); 318 vout = property_enabled(rphy->grf_base, 319 &rphy->phy_cfg->chg_det.cp_det); 320 if (vout) 321 break; 322 } 323 324 rockchip_chg_enable_primary_det(rphy, false); 325 return vout; 326 } 327 328 int rockchip_chg_get_type(void) 329 { 330 const struct rockchip_usb2phy_port_cfg *port_cfg; 331 enum power_supply_type chg_type; 332 struct rockchip_usb2phy rphy; 333 void __iomem *base; 334 bool is_dcd, vout; 335 int ret; 336 337 ret = rockchip_usb2phy_parse(&rphy); 338 if (ret) { 339 error("%s: parse usb2phy failed %d\n", __func__, ret); 340 return ret; 341 } 342 343 base = get_reg_base(&rphy); 344 port_cfg = &rphy.phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 345 346 /* Suspend USB-PHY and put the controller in non-driving mode */ 347 property_enable(base, &port_cfg->phy_sus, true); 348 property_enable(base, &rphy.phy_cfg->chg_det.opmode, false); 349 350 rphy.dcd_retries = CHG_DCD_MAX_RETRIES; 351 rphy.primary_retries = CHG_PRI_MAX_RETRIES; 352 353 /* stage 1, start DCD processing stage */ 354 rockchip_chg_enable_dcd(&rphy, true); 355 356 while (rphy.dcd_retries--) { 357 mdelay(CHG_DCD_POLL_TIME); 358 359 /* get data contact detection status */ 360 is_dcd = property_enabled(rphy.grf_base, 361 &rphy.phy_cfg->chg_det.dp_det); 362 363 if (is_dcd || !rphy.dcd_retries) { 364 /* 365 * stage 2, turn off DCD circuitry, then 366 * voltage source on DP, probe on DM. 367 */ 368 rockchip_chg_enable_dcd(&rphy, false); 369 rockchip_chg_enable_primary_det(&rphy, true); 370 break; 371 } 372 } 373 374 mdelay(CHG_PRIMARY_DET_TIME); 375 vout = property_enabled(rphy.grf_base, 376 &rphy.phy_cfg->chg_det.cp_det); 377 rockchip_chg_enable_primary_det(&rphy, false); 378 if (vout) { 379 /* stage 3, voltage source on DM, probe on DP */ 380 rockchip_chg_enable_secondary_det(&rphy, true); 381 } else { 382 if (!rphy.dcd_retries) { 383 /* floating charger found */ 384 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 385 goto out; 386 } else { 387 /* 388 * Retry some times to make sure that it's 389 * really a USB SDP charger. 390 */ 391 vout = rockchip_chg_primary_det_retry(&rphy); 392 if (vout) { 393 /* stage 3, voltage source on DM, probe on DP */ 394 rockchip_chg_enable_secondary_det(&rphy, true); 395 } else { 396 /* USB SDP charger found */ 397 chg_type = POWER_SUPPLY_TYPE_USB; 398 goto out; 399 } 400 } 401 } 402 403 mdelay(CHG_SECONDARY_DET_TIME); 404 vout = property_enabled(rphy.grf_base, 405 &rphy.phy_cfg->chg_det.dcp_det); 406 /* stage 4, turn off voltage source */ 407 rockchip_chg_enable_secondary_det(&rphy, false); 408 if (vout) 409 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 410 else 411 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 412 413 out: 414 /* Resume USB-PHY and put the controller in normal mode */ 415 property_enable(base, &rphy.phy_cfg->chg_det.opmode, true); 416 property_enable(base, &port_cfg->phy_sus, false); 417 418 debug("charger is %s\n", chg_to_string(chg_type)); 419 420 return chg_type; 421 } 422 423 void otg_phy_init(struct dwc2_udc *dev) 424 { 425 const struct rockchip_usb2phy_port_cfg *port_cfg; 426 struct rockchip_usb2phy rphy; 427 void __iomem *base; 428 int ret; 429 430 ret = rockchip_usb2phy_parse(&rphy); 431 if (ret) { 432 error("%s: parse usb2phy failed %d\n", __func__, ret); 433 return; 434 } 435 436 base = get_reg_base(&rphy); 437 port_cfg = &rphy.phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 438 439 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 440 property_enable(base, &rphy.phy_cfg->clkout_ctl, false); 441 442 /* Reset USB-PHY */ 443 property_enable(base, &port_cfg->phy_sus, true); 444 udelay(20); 445 property_enable(base, &port_cfg->phy_sus, false); 446 mdelay(2); 447 } 448 449 static int rockchip_usb2phy_init(struct phy *phy) 450 { 451 struct rockchip_usb2phy *rphy; 452 const struct rockchip_usb2phy_port_cfg *port_cfg; 453 void __iomem *base; 454 455 rphy = dev_get_priv(phy->dev); 456 base = get_reg_base(rphy); 457 458 if (phy->id == USB2PHY_PORT_OTG) { 459 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 460 } else if (phy->id == USB2PHY_PORT_HOST) { 461 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 462 } else { 463 dev_err(phy->dev, "phy id %lu not support", phy->id); 464 return -EINVAL; 465 } 466 467 property_enable(base, &port_cfg->phy_sus, false); 468 469 /* waiting for the utmi_clk to become stable */ 470 udelay(2000); 471 472 return 0; 473 } 474 475 static int rockchip_usb2phy_exit(struct phy *phy) 476 { 477 struct rockchip_usb2phy *rphy; 478 const struct rockchip_usb2phy_port_cfg *port_cfg; 479 void __iomem *base; 480 481 rphy = dev_get_priv(phy->dev); 482 base = get_reg_base(rphy); 483 484 if (phy->id == USB2PHY_PORT_OTG) { 485 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 486 } else if (phy->id == USB2PHY_PORT_HOST) { 487 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 488 } else { 489 dev_err(phy->dev, "phy id %lu not support", phy->id); 490 return -EINVAL; 491 } 492 493 property_enable(base, &port_cfg->phy_sus, true); 494 495 return 0; 496 } 497 498 static int rockchip_usb2phy_probe(struct udevice *dev) 499 { 500 const struct rockchip_usb2phy_cfg *phy_cfgs; 501 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 502 struct udevice *parent = dev->parent; 503 u32 reg, index; 504 505 if (!strncmp(parent->name, "root_driver", 11) && 506 dev_read_bool(dev, "rockchip,grf")) 507 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 508 else 509 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 510 511 if (rphy->grf_base <= 0) { 512 dev_err(dev, "get syscon grf failed\n"); 513 return -EINVAL; 514 } 515 516 if (dev_read_bool(dev, "rockchip,usbgrf")) { 517 rphy->usbgrf_base = 518 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 519 if (rphy->usbgrf_base <= 0) { 520 dev_err(dev, "get syscon usbgrf failed\n"); 521 return -EINVAL; 522 } 523 } else { 524 rphy->usbgrf_base = NULL; 525 } 526 527 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 528 dev_err(dev, "could not read reg\n"); 529 return -EINVAL; 530 } 531 532 phy_cfgs = 533 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 534 if (!phy_cfgs) { 535 dev_err(dev, "unable to get phy_cfgs\n"); 536 return -EINVAL; 537 } 538 539 /* find out a proper config which can be matched with dt. */ 540 index = 0; 541 while (phy_cfgs[index].reg) { 542 if (phy_cfgs[index].reg == reg) { 543 rphy->phy_cfg = &phy_cfgs[index]; 544 break; 545 } 546 ++index; 547 } 548 549 if (!rphy->phy_cfg) { 550 dev_err(dev, "no phy-config can be matched\n"); 551 return -EINVAL; 552 } 553 554 return 0; 555 } 556 557 static struct phy_ops rockchip_usb2phy_ops = { 558 .init = rockchip_usb2phy_init, 559 .exit = rockchip_usb2phy_exit, 560 }; 561 562 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 563 { 564 .reg = 0x17c, 565 .num_ports = 2, 566 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 567 .port_cfgs = { 568 [USB2PHY_PORT_OTG] = { 569 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 570 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 571 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 572 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 573 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 574 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 575 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 576 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 577 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 578 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 579 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 580 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 581 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 582 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 583 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 584 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 585 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 586 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 587 }, 588 [USB2PHY_PORT_HOST] = { 589 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 590 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 591 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 592 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 593 } 594 }, 595 .chg_det = { 596 .opmode = { 0x017c, 3, 0, 5, 1 }, 597 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 598 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 599 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 600 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 601 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 602 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 603 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 604 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 605 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 606 }, 607 }, 608 { /* sentinel */ } 609 }; 610 611 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 612 { 613 .reg = 0x100, 614 .num_ports = 2, 615 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 616 .port_cfgs = { 617 [USB2PHY_PORT_OTG] = { 618 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 619 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 620 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 621 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 622 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 623 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 624 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 625 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 626 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 627 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 628 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 629 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 630 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 631 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 632 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 633 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 634 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 635 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 636 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 637 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 638 }, 639 [USB2PHY_PORT_HOST] = { 640 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 641 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 642 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 643 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 644 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 645 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 646 } 647 }, 648 .chg_det = { 649 .opmode = { 0x0100, 3, 0, 5, 1 }, 650 .cp_det = { 0x0120, 24, 24, 0, 1 }, 651 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 652 .dp_det = { 0x0120, 25, 25, 0, 1 }, 653 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 654 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 655 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 656 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 657 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 658 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 659 }, 660 }, 661 { /* sentinel */ } 662 }; 663 664 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 665 { 666 .reg = 0x100, 667 .num_ports = 2, 668 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 669 .port_cfgs = { 670 [USB2PHY_PORT_OTG] = { 671 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 672 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 673 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 674 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 675 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 676 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 677 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 678 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 679 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 680 }, 681 [USB2PHY_PORT_HOST] = { 682 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 683 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 684 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 685 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 686 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 687 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 688 } 689 }, 690 .chg_det = { 691 .opmode = { 0x0100, 3, 0, 5, 1 }, 692 .cp_det = { 0x0804, 1, 1, 0, 1 }, 693 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 694 .dp_det = { 0x0804, 2, 2, 0, 1 }, 695 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 696 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 697 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 698 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 699 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 700 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 701 }, 702 }, 703 { /* sentinel */ } 704 }; 705 706 static const struct udevice_id rockchip_usb2phy_ids[] = { 707 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 708 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 709 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 710 { } 711 }; 712 713 U_BOOT_DRIVER(rockchip_usb2phy) = { 714 .name = "rockchip_usb2phy", 715 .id = UCLASS_PHY, 716 .of_match = rockchip_usb2phy_ids, 717 .ops = &rockchip_usb2phy_ops, 718 .probe = rockchip_usb2phy_probe, 719 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 720 }; 721