1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_base: the base address of USB PHY. 153 * @phy_rst: phy reset control. 154 * @phy_cfg: phy register configuration, assigned by driver data. 155 */ 156 struct rockchip_usb2phy { 157 u8 dcd_retries; 158 u8 primary_retries; 159 struct regmap *grf_base; 160 struct regmap *usbgrf_base; 161 void __iomem *phy_base; 162 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 163 struct reset_ctl phy_rst; 164 const struct rockchip_usb2phy_cfg *phy_cfg; 165 }; 166 167 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 168 { 169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 170 } 171 172 static inline int property_enable(struct regmap *base, 173 const struct usb2phy_reg *reg, bool en) 174 { 175 u32 val, mask, tmp; 176 177 tmp = en ? reg->enable : reg->disable; 178 mask = GENMASK(reg->bitend, reg->bitstart); 179 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 180 181 return regmap_write(base, reg->offset, val); 182 } 183 184 static inline bool property_enabled(struct regmap *base, 185 const struct usb2phy_reg *reg) 186 { 187 u32 tmp, orig; 188 u32 mask = GENMASK(reg->bitend, reg->bitstart); 189 190 regmap_read(base, reg->offset, &orig); 191 192 tmp = (orig & mask) >> reg->bitstart; 193 194 return tmp == reg->enable; 195 } 196 197 static const char *chg_to_string(enum power_supply_type chg_type) 198 { 199 switch (chg_type) { 200 case POWER_SUPPLY_TYPE_USB: 201 return "USB_SDP_CHARGER"; 202 case POWER_SUPPLY_TYPE_USB_DCP: 203 return "USB_DCP_CHARGER"; 204 case POWER_SUPPLY_TYPE_USB_CDP: 205 return "USB_CDP_CHARGER"; 206 case POWER_SUPPLY_TYPE_USB_FLOATING: 207 return "USB_FLOATING_CHARGER"; 208 default: 209 return "INVALID_CHARGER"; 210 } 211 } 212 213 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 214 bool en) 215 { 216 struct regmap *base = get_reg_base(rphy); 217 218 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 219 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 220 } 221 222 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 223 bool en) 224 { 225 struct regmap *base = get_reg_base(rphy); 226 227 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 228 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 229 } 230 231 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 232 bool en) 233 { 234 struct regmap *base = get_reg_base(rphy); 235 236 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 237 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 238 } 239 240 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 241 { 242 bool vout = false; 243 struct regmap *base = get_reg_base(rphy); 244 245 while (rphy->primary_retries--) { 246 /* voltage source on DP, probe on DM */ 247 rockchip_chg_enable_primary_det(rphy, true); 248 mdelay(CHG_PRIMARY_DET_TIME); 249 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 250 if (vout) 251 break; 252 } 253 254 rockchip_chg_enable_primary_det(rphy, false); 255 return vout; 256 } 257 258 int rockchip_chg_get_type(void) 259 { 260 const struct rockchip_usb2phy_port_cfg *port_cfg; 261 enum power_supply_type chg_type; 262 struct rockchip_usb2phy *rphy; 263 struct udevice *udev; 264 struct regmap *base; 265 bool is_dcd, vout; 266 int ret; 267 268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 269 if (ret == -ENODEV) { 270 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 271 if (ret) { 272 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 273 return ret; 274 } 275 } 276 277 rphy = dev_get_priv(udev); 278 base = get_reg_base(rphy); 279 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 280 281 /* Check USB-Vbus status first */ 282 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 283 pr_info("%s: no charger found\n", __func__); 284 return POWER_SUPPLY_TYPE_UNKNOWN; 285 } 286 287 /* Suspend USB-PHY and put the controller in non-driving mode */ 288 property_enable(base, &port_cfg->phy_sus, true); 289 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 290 291 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 292 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 293 294 /* stage 1, start DCD processing stage */ 295 rockchip_chg_enable_dcd(rphy, true); 296 297 while (rphy->dcd_retries--) { 298 mdelay(CHG_DCD_POLL_TIME); 299 300 /* get data contact detection status */ 301 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 302 303 if (is_dcd || !rphy->dcd_retries) { 304 /* 305 * stage 2, turn off DCD circuitry, then 306 * voltage source on DP, probe on DM. 307 */ 308 rockchip_chg_enable_dcd(rphy, false); 309 rockchip_chg_enable_primary_det(rphy, true); 310 break; 311 } 312 } 313 314 mdelay(CHG_PRIMARY_DET_TIME); 315 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 316 rockchip_chg_enable_primary_det(rphy, false); 317 if (vout) { 318 /* stage 3, voltage source on DM, probe on DP */ 319 rockchip_chg_enable_secondary_det(rphy, true); 320 } else { 321 if (!rphy->dcd_retries) { 322 /* floating charger found */ 323 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 324 goto out; 325 } else { 326 /* 327 * Retry some times to make sure that it's 328 * really a USB SDP charger. 329 */ 330 vout = rockchip_chg_primary_det_retry(rphy); 331 if (vout) { 332 /* stage 3, voltage source on DM, probe on DP */ 333 rockchip_chg_enable_secondary_det(rphy, true); 334 } else { 335 /* USB SDP charger found */ 336 chg_type = POWER_SUPPLY_TYPE_USB; 337 goto out; 338 } 339 } 340 } 341 342 mdelay(CHG_SECONDARY_DET_TIME); 343 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 344 /* stage 4, turn off voltage source */ 345 rockchip_chg_enable_secondary_det(rphy, false); 346 if (vout) 347 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 348 else 349 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 350 351 out: 352 /* Resume USB-PHY and put the controller in normal mode */ 353 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 354 property_enable(base, &port_cfg->phy_sus, false); 355 356 debug("charger is %s\n", chg_to_string(chg_type)); 357 358 return chg_type; 359 } 360 361 int rockchip_u2phy_vbus_detect(void) 362 { 363 int chg_type; 364 365 chg_type = rockchip_chg_get_type(); 366 367 return (chg_type == POWER_SUPPLY_TYPE_USB || 368 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 369 } 370 371 void otg_phy_init(struct dwc2_udc *dev) 372 { 373 const struct rockchip_usb2phy_port_cfg *port_cfg; 374 struct rockchip_usb2phy *rphy; 375 struct udevice *udev; 376 struct regmap *base; 377 int ret; 378 379 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 380 if (ret == -ENODEV) { 381 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 382 if (ret) { 383 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 384 return; 385 } 386 } 387 388 rphy = dev_get_priv(udev); 389 base = get_reg_base(rphy); 390 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 391 392 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 393 if(rphy->phy_cfg->clkout_ctl.disable) 394 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 395 396 /* Reset USB-PHY */ 397 property_enable(base, &port_cfg->phy_sus, true); 398 udelay(20); 399 property_enable(base, &port_cfg->phy_sus, false); 400 mdelay(2); 401 } 402 403 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 404 { 405 int ret; 406 407 if (rphy->phy_rst.dev) { 408 ret = reset_assert(&rphy->phy_rst); 409 if (ret < 0) { 410 pr_err("u2phy assert reset failed: %d", ret); 411 return ret; 412 } 413 414 udelay(20); 415 416 ret = reset_deassert(&rphy->phy_rst); 417 if (ret < 0) { 418 pr_err("u2phy deassert reset failed: %d", ret); 419 return ret; 420 } 421 422 udelay(100); 423 } 424 425 return 0; 426 } 427 428 static int rockchip_usb2phy_init(struct phy *phy) 429 { 430 struct udevice *parent = phy->dev->parent; 431 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 432 const struct rockchip_usb2phy_port_cfg *port_cfg; 433 struct regmap *base = get_reg_base(rphy); 434 435 if (phy->id == USB2PHY_PORT_OTG) { 436 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 437 } else if (phy->id == USB2PHY_PORT_HOST) { 438 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 439 } else { 440 dev_err(phy->dev, "phy id %lu not support", phy->id); 441 return -EINVAL; 442 } 443 444 property_enable(base, &port_cfg->phy_sus, false); 445 446 /* waiting for the utmi_clk to become stable */ 447 udelay(2000); 448 449 return 0; 450 } 451 452 static int rockchip_usb2phy_exit(struct phy *phy) 453 { 454 struct udevice *parent = phy->dev->parent; 455 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 456 const struct rockchip_usb2phy_port_cfg *port_cfg; 457 struct regmap *base = get_reg_base(rphy); 458 459 if (phy->id == USB2PHY_PORT_OTG) { 460 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 461 } else if (phy->id == USB2PHY_PORT_HOST) { 462 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 463 } else { 464 dev_err(phy->dev, "phy id %lu not support", phy->id); 465 return -EINVAL; 466 } 467 468 property_enable(base, &port_cfg->phy_sus, true); 469 470 return 0; 471 } 472 473 static int rockchip_usb2phy_power_on(struct phy *phy) 474 { 475 struct udevice *parent = phy->dev->parent; 476 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 477 struct udevice *vbus = rphy->vbus_supply[phy->id]; 478 int ret; 479 480 if (vbus) { 481 ret = regulator_set_enable(vbus, true); 482 if (ret) { 483 pr_err("%s: Failed to set VBus supply\n", __func__); 484 return ret; 485 } 486 } 487 488 return 0; 489 } 490 491 static int rockchip_usb2phy_power_off(struct phy *phy) 492 { 493 struct udevice *parent = phy->dev->parent; 494 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 495 struct udevice *vbus = rphy->vbus_supply[phy->id]; 496 int ret; 497 498 if (vbus) { 499 ret = regulator_set_enable(vbus, false); 500 if (ret) { 501 pr_err("%s: Failed to set VBus supply\n", __func__); 502 return ret; 503 } 504 } 505 506 return 0; 507 } 508 509 static int rockchip_usb2phy_of_xlate(struct phy *phy, 510 struct ofnode_phandle_args *args) 511 { 512 const char *dev_name = phy->dev->name; 513 struct udevice *parent = phy->dev->parent; 514 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 515 516 if (!strcasecmp(dev_name, "host-port")) { 517 phy->id = USB2PHY_PORT_HOST; 518 device_get_supply_regulator(phy->dev, "phy-supply", 519 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 520 } else if (!strcasecmp(dev_name, "otg-port")) { 521 phy->id = USB2PHY_PORT_OTG; 522 device_get_supply_regulator(phy->dev, "phy-supply", 523 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 524 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 525 device_get_supply_regulator(phy->dev, "vbus-supply", 526 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 527 } else { 528 pr_err("%s: invalid dev name\n", __func__); 529 return -EINVAL; 530 } 531 532 return 0; 533 } 534 535 static int rockchip_usb2phy_bind(struct udevice *dev) 536 { 537 struct udevice *child; 538 ofnode subnode; 539 const char *node_name; 540 int ret; 541 542 dev_for_each_subnode(subnode, dev) { 543 if (!ofnode_valid(subnode)) { 544 debug("%s: %s subnode not found", __func__, dev->name); 545 return -ENXIO; 546 } 547 548 node_name = ofnode_get_name(subnode); 549 debug("%s: subnode %s\n", __func__, node_name); 550 551 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 552 node_name, subnode, &child); 553 if (ret) { 554 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 555 __func__, node_name); 556 return ret; 557 } 558 } 559 560 return 0; 561 } 562 563 static int rockchip_usb2phy_probe(struct udevice *dev) 564 { 565 const struct rockchip_usb2phy_cfg *phy_cfgs; 566 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 567 struct udevice *parent = dev->parent; 568 struct udevice *syscon; 569 struct resource res; 570 u32 reg, index; 571 int ret; 572 573 rphy->phy_base = (void __iomem *)dev_read_addr(dev); 574 if (IS_ERR(rphy->phy_base)) { 575 dev_err(dev, "get the base address of usb phy failed\n"); 576 } 577 578 if (!strncmp(parent->name, "root_driver", 11) && 579 dev_read_bool(dev, "rockchip,grf")) { 580 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 581 "rockchip,grf", &syscon); 582 if (ret) { 583 dev_err(dev, "get syscon grf failed\n"); 584 return ret; 585 } 586 587 rphy->grf_base = syscon_get_regmap(syscon); 588 } else { 589 rphy->grf_base = syscon_get_regmap(parent); 590 } 591 592 if (rphy->grf_base <= 0) { 593 dev_err(dev, "get syscon grf regmap failed\n"); 594 return -EINVAL; 595 } 596 597 if (dev_read_bool(dev, "rockchip,usbgrf")) { 598 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 599 "rockchip,usbgrf", &syscon); 600 if (ret) { 601 dev_err(dev, "get syscon usbgrf failed\n"); 602 return ret; 603 } 604 605 rphy->usbgrf_base = syscon_get_regmap(syscon); 606 if (rphy->usbgrf_base <= 0) { 607 dev_err(dev, "get syscon usbgrf regmap failed\n"); 608 return -EINVAL; 609 } 610 } else { 611 rphy->usbgrf_base = NULL; 612 } 613 614 if (!strncmp(parent->name, "root_driver", 11)) { 615 ret = dev_read_resource(dev, 0, &res); 616 reg = res.start; 617 } else { 618 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 619 } 620 621 if (ret) { 622 dev_err(dev, "could not read reg\n"); 623 return -EINVAL; 624 } 625 626 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 627 if (ret) 628 dev_dbg(dev, "no u2phy reset control specified\n"); 629 630 phy_cfgs = 631 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 632 if (!phy_cfgs) { 633 dev_err(dev, "unable to get phy_cfgs\n"); 634 return -EINVAL; 635 } 636 637 /* find out a proper config which can be matched with dt. */ 638 index = 0; 639 do { 640 if (phy_cfgs[index].reg == reg) { 641 rphy->phy_cfg = &phy_cfgs[index]; 642 break; 643 } 644 ++index; 645 } while (phy_cfgs[index].reg); 646 647 if (!rphy->phy_cfg) { 648 dev_err(dev, "no phy-config can be matched\n"); 649 return -EINVAL; 650 } 651 652 if (rphy->phy_cfg->phy_tuning) 653 rphy->phy_cfg->phy_tuning(rphy); 654 655 return 0; 656 } 657 658 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 659 { 660 struct regmap *base = get_reg_base(rphy); 661 int ret = 0; 662 663 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 664 if (rphy->phy_cfg->reg == 0x760) 665 ret = regmap_write(base, 0x76c, 0x00070004); 666 667 return ret; 668 } 669 670 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 671 { 672 struct regmap *base = get_reg_base(rphy); 673 unsigned int tmp, orig; 674 int ret; 675 676 if (soc_is_rk3308bs()) { 677 /* Enable otg/host port pre-emphasis during non-chirp phase */ 678 ret = regmap_read(base, 0, &orig); 679 if (ret) 680 return ret; 681 tmp = orig & ~GENMASK(2, 0); 682 tmp |= BIT(2) & GENMASK(2, 0); 683 ret = regmap_write(base, 0, tmp); 684 if (ret) 685 return ret; 686 687 /* Set otg port squelch trigger point configure to 100mv */ 688 ret = regmap_read(base, 0x004, &orig); 689 if (ret) 690 return ret; 691 tmp = orig & ~GENMASK(7, 5); 692 tmp |= 0x40 & GENMASK(7, 5); 693 ret = regmap_write(base, 0x004, tmp); 694 if (ret) 695 return ret; 696 697 ret = regmap_read(base, 0x008, &orig); 698 if (ret) 699 return ret; 700 tmp = orig & ~BIT(0); 701 tmp |= 0x1 & BIT(0); 702 ret = regmap_write(base, 0x008, tmp); 703 if (ret) 704 return ret; 705 706 /* Enable host port pre-emphasis during non-chirp phase */ 707 ret = regmap_read(base, 0x400, &orig); 708 if (ret) 709 return ret; 710 tmp = orig & ~GENMASK(2, 0); 711 tmp |= BIT(2) & GENMASK(2, 0); 712 ret = regmap_write(base, 0x400, tmp); 713 if (ret) 714 return ret; 715 716 /* Set host port squelch trigger point configure to 100mv */ 717 ret = regmap_read(base, 0x404, &orig); 718 if (ret) 719 return ret; 720 tmp = orig & ~GENMASK(7, 5); 721 tmp |= 0x40 & GENMASK(7, 5); 722 ret = regmap_write(base, 0x404, tmp); 723 if (ret) 724 return ret; 725 726 ret = regmap_read(base, 0x408, &orig); 727 if (ret) 728 return ret; 729 tmp = orig & ~BIT(0); 730 tmp |= 0x1 & BIT(0); 731 ret = regmap_write(base, 0x408, tmp); 732 if (ret) 733 return ret; 734 } 735 736 return 0; 737 } 738 739 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 740 { 741 struct regmap *base = get_reg_base(rphy); 742 unsigned int tmp, orig; 743 int ret; 744 745 if (soc_is_px30s()) { 746 /* Enable otg/host port pre-emphasis during non-chirp phase */ 747 ret = regmap_read(base, 0x8000, &orig); 748 if (ret) 749 return ret; 750 tmp = orig & ~GENMASK(2, 0); 751 tmp |= BIT(2) & GENMASK(2, 0); 752 ret = regmap_write(base, 0x8000, tmp); 753 if (ret) 754 return ret; 755 756 /* Set otg port squelch trigger point configure to 100mv */ 757 ret = regmap_read(base, 0x8004, &orig); 758 if (ret) 759 return ret; 760 tmp = orig & ~GENMASK(7, 5); 761 tmp |= 0x40 & GENMASK(7, 5); 762 ret = regmap_write(base, 0x8004, tmp); 763 if (ret) 764 return ret; 765 766 ret = regmap_read(base, 0x8008, &orig); 767 if (ret) 768 return ret; 769 tmp = orig & ~BIT(0); 770 tmp |= 0x1 & BIT(0); 771 ret = regmap_write(base, 0x8008, tmp); 772 if (ret) 773 return ret; 774 775 /* Enable host port pre-emphasis during non-chirp phase */ 776 ret = regmap_read(base, 0x8400, &orig); 777 if (ret) 778 return ret; 779 tmp = orig & ~GENMASK(2, 0); 780 tmp |= BIT(2) & GENMASK(2, 0); 781 ret = regmap_write(base, 0x8400, tmp); 782 if (ret) 783 return ret; 784 785 /* Set host port squelch trigger point configure to 100mv */ 786 ret = regmap_read(base, 0x8404, &orig); 787 if (ret) 788 return ret; 789 tmp = orig & ~GENMASK(7, 5); 790 tmp |= 0x40 & GENMASK(7, 5); 791 ret = regmap_write(base, 0x8404, tmp); 792 if (ret) 793 return ret; 794 795 ret = regmap_read(base, 0x8408, &orig); 796 if (ret) 797 return ret; 798 tmp = orig & ~BIT(0); 799 tmp |= 0x1 & BIT(0); 800 ret = regmap_write(base, 0x8408, tmp); 801 if (ret) 802 return ret; 803 } 804 805 return 0; 806 } 807 808 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy) 809 { 810 u32 reg; 811 int ret = 0; 812 813 if (IS_ERR(rphy->phy_base)) { 814 return PTR_ERR(rphy->phy_base); 815 } 816 817 /* Turn off otg port differential receiver in suspend mode */ 818 reg = readl(rphy->phy_base + 0x30); 819 writel(reg & ~BIT(2), rphy->phy_base + 0x30); 820 821 /* Turn off host port differential receiver in suspend mode */ 822 reg = readl(rphy->phy_base + 0x0430); 823 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); 824 825 /* Set otg port HS eye height to 400mv(default is 450mv) */ 826 reg = readl(rphy->phy_base + 0x30); 827 reg &= ~GENMASK(6, 4); 828 reg |= (0x00 << 4); 829 writel(reg, rphy->phy_base + 0x30); 830 831 /* Set host port HS eye height to 400mv(default is 450mv) */ 832 reg = readl(rphy->phy_base + 0x430); 833 reg &= ~GENMASK(6, 4); 834 reg |= (0x00 << 4); 835 writel(reg, rphy->phy_base + 0x430); 836 837 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */ 838 reg = readl(rphy->phy_base + 0x94); 839 reg &= ~GENMASK(6, 3); 840 reg |= (0x03 << 3); 841 writel(reg, rphy->phy_base + 0x94); 842 843 /* Turn on output clk of phy*/ 844 reg = readl(rphy->phy_base + 0x41c); 845 reg &= ~GENMASK(7, 2); 846 reg |= (0x27 << 2); 847 writel(reg, rphy->phy_base + 0x41c); 848 849 return ret; 850 } 851 852 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy) 853 { 854 u32 reg; 855 int ret = 0; 856 857 if (IS_ERR(rphy->phy_base)) { 858 return PTR_ERR(rphy->phy_base); 859 } 860 861 /* Turn off differential receiver by default to save power */ 862 reg = readl(rphy->phy_base + 0x30); 863 writel(reg & ~BIT(2), rphy->phy_base + 0x30); 864 865 reg = readl(rphy->phy_base + 0x0430); 866 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); 867 868 /* Enable pre-emphasis during non-chirp phase */ 869 reg = readl(rphy->phy_base); 870 reg &= ~GENMASK(2, 0); 871 reg |= 0x04; 872 writel(reg, rphy->phy_base); 873 874 reg = readl(rphy->phy_base + 0x0400); 875 reg &= ~GENMASK(2, 0); 876 reg |= 0x04; 877 writel(reg, rphy->phy_base + 0x0400); 878 879 /* Set HS eye height to 425mv(default is 400mv) */ 880 reg = readl(rphy->phy_base + 0x0030); 881 reg &= ~GENMASK(6, 4); 882 reg |= (0x05 << 4); 883 writel(reg, rphy->phy_base + 0x0030); 884 885 reg = readl(rphy->phy_base + 0x0430); 886 reg &= ~GENMASK(6, 4); 887 reg |= (0x05 << 4); 888 writel(reg, rphy->phy_base + 0x0430); 889 890 return ret; 891 } 892 893 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 894 { 895 struct regmap *base = get_reg_base(rphy); 896 int ret; 897 898 /* Deassert SIDDQ to power on analog block */ 899 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 900 if (ret) 901 return ret; 902 903 /* Do reset after exit IDDQ mode */ 904 ret = rockchip_usb2phy_reset(rphy); 905 if (ret) 906 return ret; 907 908 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 909 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 910 if (ret) 911 return ret; 912 913 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 914 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 915 if (ret) 916 return ret; 917 918 return 0; 919 } 920 921 static struct phy_ops rockchip_usb2phy_ops = { 922 .init = rockchip_usb2phy_init, 923 .exit = rockchip_usb2phy_exit, 924 .power_on = rockchip_usb2phy_power_on, 925 .power_off = rockchip_usb2phy_power_off, 926 .of_xlate = rockchip_usb2phy_of_xlate, 927 }; 928 929 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 930 { 931 .reg = 0x100, 932 .num_ports = 2, 933 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 934 .port_cfgs = { 935 [USB2PHY_PORT_OTG] = { 936 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 937 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 938 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 939 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 940 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 941 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 942 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 943 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 944 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 945 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 946 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 947 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 948 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 949 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 950 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 951 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 952 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 953 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 954 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 955 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 956 }, 957 [USB2PHY_PORT_HOST] = { 958 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 959 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 960 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 961 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 962 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 963 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 964 } 965 }, 966 .chg_det = { 967 .opmode = { 0x0100, 3, 0, 5, 1 }, 968 .cp_det = { 0x0120, 24, 24, 0, 1 }, 969 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 970 .dp_det = { 0x0120, 25, 25, 0, 1 }, 971 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 972 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 973 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 974 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 975 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 976 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 977 }, 978 }, 979 { /* sentinel */ } 980 }; 981 982 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 983 { 984 .reg = 0x17c, 985 .num_ports = 2, 986 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 987 .port_cfgs = { 988 [USB2PHY_PORT_OTG] = { 989 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 990 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 991 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 992 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 993 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 994 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 995 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 996 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 997 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 998 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 999 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1000 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1001 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1002 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1003 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1004 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1005 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1006 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1007 }, 1008 [USB2PHY_PORT_HOST] = { 1009 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1010 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1011 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1012 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1013 } 1014 }, 1015 .chg_det = { 1016 .opmode = { 0x017c, 3, 0, 5, 1 }, 1017 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 1018 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 1019 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 1020 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 1021 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 1022 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 1023 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 1024 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 1025 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 1026 }, 1027 }, 1028 { /* sentinel */ } 1029 }; 1030 1031 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 1032 { 1033 .reg = 0x760, 1034 .num_ports = 2, 1035 .phy_tuning = rk322x_usb2phy_tuning, 1036 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1037 .port_cfgs = { 1038 [USB2PHY_PORT_OTG] = { 1039 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 1040 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1041 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1042 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1043 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 1044 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 1045 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 1046 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 1047 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 1048 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 1049 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 1050 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 1051 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1052 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1053 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1054 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1055 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 1056 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1057 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 1058 }, 1059 [USB2PHY_PORT_HOST] = { 1060 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 1061 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1062 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1063 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1064 } 1065 }, 1066 .chg_det = { 1067 .opmode = { 0x0760, 3, 0, 5, 1 }, 1068 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1069 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1070 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1071 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1072 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1073 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1074 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1075 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1076 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1077 }, 1078 }, 1079 { 1080 .reg = 0x800, 1081 .num_ports = 2, 1082 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1083 .port_cfgs = { 1084 [USB2PHY_PORT_OTG] = { 1085 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1086 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1087 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1088 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1089 }, 1090 [USB2PHY_PORT_HOST] = { 1091 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1092 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1093 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1094 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1095 } 1096 }, 1097 }, 1098 { /* sentinel */ } 1099 }; 1100 1101 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1102 { 1103 .reg = 0x100, 1104 .num_ports = 2, 1105 .phy_tuning = rk3308_usb2phy_tuning, 1106 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1107 .port_cfgs = { 1108 [USB2PHY_PORT_OTG] = { 1109 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1110 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1111 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1112 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1113 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1114 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1115 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1116 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1117 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1118 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1119 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1120 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1121 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1122 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1123 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1124 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1125 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1126 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1127 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1128 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1129 }, 1130 [USB2PHY_PORT_HOST] = { 1131 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1132 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1133 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1134 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1135 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1136 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1137 } 1138 }, 1139 .chg_det = { 1140 .opmode = { 0x0100, 3, 0, 5, 1 }, 1141 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1142 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1143 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1144 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1145 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1146 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1147 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1148 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1149 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1150 }, 1151 }, 1152 { /* sentinel */ } 1153 }; 1154 1155 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1156 { 1157 .reg = 0x100, 1158 .num_ports = 2, 1159 .phy_tuning = rk3328_usb2phy_tuning, 1160 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1161 .port_cfgs = { 1162 [USB2PHY_PORT_OTG] = { 1163 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1164 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1165 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1166 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1167 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1168 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1169 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1170 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1171 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1172 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1173 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1174 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1175 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1176 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1177 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1178 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1179 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1180 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1181 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1182 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1183 }, 1184 [USB2PHY_PORT_HOST] = { 1185 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1186 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1187 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1188 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1189 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1190 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1191 } 1192 }, 1193 .chg_det = { 1194 .opmode = { 0x0100, 3, 0, 5, 1 }, 1195 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1196 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1197 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1198 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1199 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1200 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1201 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1202 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1203 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1204 }, 1205 }, 1206 { /* sentinel */ } 1207 }; 1208 1209 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1210 { 1211 .reg = 0x700, 1212 .num_ports = 2, 1213 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1214 .port_cfgs = { 1215 [USB2PHY_PORT_OTG] = { 1216 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1217 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1218 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1219 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1220 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1221 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1222 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1223 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1224 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1225 }, 1226 [USB2PHY_PORT_HOST] = { 1227 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1228 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1229 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1230 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1231 } 1232 }, 1233 .chg_det = { 1234 .opmode = { 0x0700, 3, 0, 5, 1 }, 1235 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1236 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1237 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1238 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1239 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1240 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1241 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1242 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1243 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1244 }, 1245 }, 1246 { /* sentinel */ } 1247 }; 1248 1249 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1250 { 1251 .reg = 0xe450, 1252 .num_ports = 2, 1253 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1254 .port_cfgs = { 1255 [USB2PHY_PORT_OTG] = { 1256 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1257 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1258 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1259 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1260 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1261 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1262 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1263 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1264 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1265 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1266 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1267 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1268 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1269 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1270 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1271 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1272 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1273 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1274 }, 1275 [USB2PHY_PORT_HOST] = { 1276 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1277 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1278 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1279 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1280 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1281 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1282 } 1283 }, 1284 .chg_det = { 1285 .opmode = { 0xe454, 3, 0, 5, 1 }, 1286 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1287 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1288 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1289 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1290 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1291 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1292 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1293 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1294 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1295 }, 1296 }, 1297 { 1298 .reg = 0xe460, 1299 .num_ports = 2, 1300 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1301 .port_cfgs = { 1302 [USB2PHY_PORT_OTG] = { 1303 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1304 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1305 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1306 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1307 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1308 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1309 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1310 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1311 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1312 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1313 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1314 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1315 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1316 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1317 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1318 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1319 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1320 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1321 }, 1322 [USB2PHY_PORT_HOST] = { 1323 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1324 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1325 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1326 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1327 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1328 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1329 } 1330 }, 1331 .chg_det = { 1332 .opmode = { 0xe464, 3, 0, 5, 1 }, 1333 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1334 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1335 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1336 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1337 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1338 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1339 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1340 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1341 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1342 }, 1343 }, 1344 { /* sentinel */ } 1345 }; 1346 1347 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = { 1348 { 1349 .reg = 0xff3e0000, 1350 .num_ports = 1, 1351 .clkout_ctl = { 0x0058, 4, 4, 1, 0 }, 1352 .port_cfgs = { 1353 [USB2PHY_PORT_OTG] = { 1354 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 }, 1355 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 }, 1356 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 }, 1357 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 }, 1358 .iddig_output = { 0x0050, 10, 10, 0, 1 }, 1359 .iddig_en = { 0x0050, 9, 9, 0, 1 }, 1360 .idfall_det_en = { 0x0100, 5, 5, 0, 1 }, 1361 .idfall_det_st = { 0x0104, 5, 5, 0, 1 }, 1362 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 }, 1363 .idrise_det_en = { 0x0100, 4, 4, 0, 1 }, 1364 .idrise_det_st = { 0x0104, 4, 4, 0, 1 }, 1365 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 }, 1366 .ls_det_en = { 0x0100, 0, 0, 0, 1 }, 1367 .ls_det_st = { 0x0104, 0, 0, 0, 1 }, 1368 .ls_det_clr = { 0x0108, 0, 0, 0, 1 }, 1369 .utmi_avalid = { 0x0060, 10, 10, 0, 1 }, 1370 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 }, 1371 .utmi_iddig = { 0x0060, 6, 6, 0, 1 }, 1372 .utmi_ls = { 0x0060, 5, 4, 0, 1 }, 1373 }, 1374 }, 1375 .chg_det = { 1376 .opmode = { 0x0050, 3, 0, 5, 1 }, 1377 .cp_det = { 0x0060, 13, 13, 0, 1 }, 1378 .dcp_det = { 0x0060, 12, 12, 0, 1 }, 1379 .dp_det = { 0x0060, 14, 14, 0, 1 }, 1380 .idm_sink_en = { 0x0058, 8, 8, 0, 1 }, 1381 .idp_sink_en = { 0x0058, 7, 7, 0, 1 }, 1382 .idp_src_en = { 0x0058, 9, 9, 0, 1 }, 1383 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 }, 1384 .vdm_src_en = { 0x0058, 12, 12, 0, 1 }, 1385 .vdp_src_en = { 0x0058, 11, 11, 0, 1 }, 1386 }, 1387 }, 1388 { /* sentinel */ } 1389 }; 1390 1391 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1392 { 1393 .reg = 0x100, 1394 .num_ports = 2, 1395 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1396 .port_cfgs = { 1397 [USB2PHY_PORT_OTG] = { 1398 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1399 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1400 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1401 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1402 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1403 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1404 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1405 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1406 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1407 }, 1408 [USB2PHY_PORT_HOST] = { 1409 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1410 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1411 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1412 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1413 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1414 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1415 } 1416 }, 1417 .chg_det = { 1418 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1419 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1420 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1421 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1422 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1423 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1424 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1425 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1426 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1427 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1428 }, 1429 }, 1430 { /* sentinel */ } 1431 }; 1432 1433 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1434 { 1435 .reg = 0xffdf0000, 1436 .num_ports = 2, 1437 .phy_tuning = rk3528_usb2phy_tuning, 1438 .port_cfgs = { 1439 [USB2PHY_PORT_OTG] = { 1440 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1441 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1442 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1443 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1444 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1445 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1446 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1447 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1448 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1449 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1450 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1451 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1452 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1453 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1454 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1455 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1456 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1457 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1458 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1459 }, 1460 [USB2PHY_PORT_HOST] = { 1461 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1462 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1463 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1464 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1465 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1466 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1467 } 1468 }, 1469 .chg_det = { 1470 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1471 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1472 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1473 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1474 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1475 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1476 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1477 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1478 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1479 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1480 }, 1481 } 1482 }; 1483 1484 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { 1485 { 1486 .reg = 0xff740000, 1487 .num_ports = 2, 1488 .phy_tuning = rk3562_usb2phy_tuning, 1489 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1490 .port_cfgs = { 1491 [USB2PHY_PORT_OTG] = { 1492 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1493 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1494 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1495 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1496 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1497 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1498 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1499 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1500 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1501 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1502 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1503 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1504 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1505 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1506 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1507 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1508 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1509 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1510 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1511 }, 1512 [USB2PHY_PORT_HOST] = { 1513 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, 1514 .ls_det_en = { 0x0110, 1, 1, 0, 1 }, 1515 .ls_det_st = { 0x0114, 1, 1, 0, 1 }, 1516 .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, 1517 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1518 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1519 } 1520 }, 1521 .chg_det = { 1522 .opmode = { 0x0100, 3, 0, 5, 1 }, 1523 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1524 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1525 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1526 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1527 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1528 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1529 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1530 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1531 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1532 }, 1533 }, 1534 { /* sentinel */ } 1535 }; 1536 1537 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1538 { 1539 .reg = 0xfe8a0000, 1540 .num_ports = 2, 1541 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1542 .port_cfgs = { 1543 [USB2PHY_PORT_OTG] = { 1544 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1545 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1546 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1547 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1548 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1549 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1550 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1551 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1552 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1553 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1554 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1555 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1556 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1557 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1558 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1559 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1560 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1561 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1562 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1563 }, 1564 [USB2PHY_PORT_HOST] = { 1565 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1566 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1567 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1568 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1569 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1570 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1571 } 1572 }, 1573 .chg_det = { 1574 .opmode = { 0x0000, 3, 0, 5, 1 }, 1575 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1576 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1577 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1578 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1579 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1580 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1581 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1582 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1583 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1584 }, 1585 }, 1586 { 1587 .reg = 0xfe8b0000, 1588 .num_ports = 2, 1589 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1590 .port_cfgs = { 1591 [USB2PHY_PORT_OTG] = { 1592 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1593 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1594 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1595 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1596 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1597 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1598 }, 1599 [USB2PHY_PORT_HOST] = { 1600 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1601 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1602 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1603 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1604 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1605 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1606 } 1607 }, 1608 }, 1609 { /* sentinel */ } 1610 }; 1611 1612 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1613 { 1614 .reg = 0x0000, 1615 .num_ports = 1, 1616 .phy_tuning = rk3588_usb2phy_tuning, 1617 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1618 .port_cfgs = { 1619 [USB2PHY_PORT_OTG] = { 1620 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1621 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1622 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1623 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1624 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1625 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1626 } 1627 }, 1628 .chg_det = { 1629 .opmode = { 0x0008, 2, 2, 1, 0 }, 1630 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1631 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1632 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1633 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1634 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1635 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1636 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1637 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1638 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1639 }, 1640 }, 1641 { 1642 .reg = 0x4000, 1643 .num_ports = 1, 1644 .phy_tuning = rk3588_usb2phy_tuning, 1645 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1646 .port_cfgs = { 1647 /* Select suspend control from controller */ 1648 [USB2PHY_PORT_OTG] = { 1649 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1650 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1651 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1652 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1653 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1654 } 1655 }, 1656 }, 1657 { 1658 .reg = 0x8000, 1659 .num_ports = 1, 1660 .phy_tuning = rk3588_usb2phy_tuning, 1661 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1662 .port_cfgs = { 1663 [USB2PHY_PORT_HOST] = { 1664 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1665 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1666 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1667 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1668 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1669 } 1670 }, 1671 }, 1672 { 1673 .reg = 0xc000, 1674 .num_ports = 1, 1675 .phy_tuning = rk3588_usb2phy_tuning, 1676 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1677 .port_cfgs = { 1678 [USB2PHY_PORT_HOST] = { 1679 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1680 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1681 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1682 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1683 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1684 } 1685 }, 1686 }, 1687 { /* sentinel */ } 1688 }; 1689 1690 static const struct udevice_id rockchip_usb2phy_ids[] = { 1691 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1692 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1693 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1694 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1695 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1696 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1697 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1698 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 1699 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs }, 1700 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1701 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1702 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs }, 1703 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1704 { } 1705 }; 1706 1707 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1708 .name = "rockchip_usb2phy_port", 1709 .id = UCLASS_PHY, 1710 .ops = &rockchip_usb2phy_ops, 1711 }; 1712 1713 U_BOOT_DRIVER(rockchip_usb2phy) = { 1714 .name = "rockchip_usb2phy", 1715 .id = UCLASS_PHY, 1716 .of_match = rockchip_usb2phy_ids, 1717 .probe = rockchip_usb2phy_probe, 1718 .bind = rockchip_usb2phy_bind, 1719 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1720 }; 1721