1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <linux/ioport.h> 12 #include <power/regulator.h> 13 #include <regmap.h> 14 #include <syscon.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <reset-uclass.h> 19 20 #include "../usb/gadget/dwc2_udc_otg_priv.h" 21 22 #define U2PHY_BIT_WRITEABLE_SHIFT 16 23 #define CHG_DCD_MAX_RETRIES 6 24 #define CHG_PRI_MAX_RETRIES 2 25 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 26 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 27 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 28 29 struct rockchip_usb2phy; 30 31 enum power_supply_type { 32 POWER_SUPPLY_TYPE_UNKNOWN = 0, 33 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 34 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 35 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 37 }; 38 39 enum rockchip_usb2phy_port_id { 40 USB2PHY_PORT_OTG, 41 USB2PHY_PORT_HOST, 42 USB2PHY_NUM_PORTS, 43 }; 44 45 struct usb2phy_reg { 46 u32 offset; 47 u32 bitend; 48 u32 bitstart; 49 u32 disable; 50 u32 enable; 51 }; 52 53 /** 54 * struct rockchip_chg_det_reg: usb charger detect registers 55 * @cp_det: charging port detected successfully. 56 * @dcp_det: dedicated charging port detected successfully. 57 * @dp_det: assert data pin connect successfully. 58 * @idm_sink_en: open dm sink curren. 59 * @idp_sink_en: open dp sink current. 60 * @idp_src_en: open dm source current. 61 * @rdm_pdwn_en: open dm pull down resistor. 62 * @vdm_src_en: open dm voltage source. 63 * @vdp_src_en: open dp voltage source. 64 * @opmode: utmi operational mode. 65 */ 66 struct rockchip_chg_det_reg { 67 struct usb2phy_reg cp_det; 68 struct usb2phy_reg dcp_det; 69 struct usb2phy_reg dp_det; 70 struct usb2phy_reg idm_sink_en; 71 struct usb2phy_reg idp_sink_en; 72 struct usb2phy_reg idp_src_en; 73 struct usb2phy_reg rdm_pdwn_en; 74 struct usb2phy_reg vdm_src_en; 75 struct usb2phy_reg vdp_src_en; 76 struct usb2phy_reg opmode; 77 }; 78 79 /** 80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 81 * @phy_sus: phy suspend register. 82 * @bvalid_det_en: vbus valid rise detection enable register. 83 * @bvalid_det_st: vbus valid rise detection status register. 84 * @bvalid_det_clr: vbus valid rise detection clear register. 85 * @ls_det_en: linestate detection enable register. 86 * @ls_det_st: linestate detection state register. 87 * @ls_det_clr: linestate detection clear register. 88 * @iddig_output: iddig output from grf. 89 * @iddig_en: utmi iddig select between grf and phy, 90 * 0: from phy; 1: from grf 91 * @idfall_det_en: id fall detection enable register. 92 * @idfall_det_st: id fall detection state register. 93 * @idfall_det_clr: id fall detection clear register. 94 * @idrise_det_en: id rise detection enable register. 95 * @idrise_det_st: id rise detection state register. 96 * @idrise_det_clr: id rise detection clear register. 97 * @utmi_avalid: utmi vbus avalid status register. 98 * @utmi_bvalid: utmi vbus bvalid status register. 99 * @utmi_iddig: otg port id pin status register. 100 * @utmi_ls: utmi linestate state register. 101 * @utmi_hstdet: utmi host disconnect register. 102 * @vbus_det_en: vbus detect function power down register. 103 */ 104 struct rockchip_usb2phy_port_cfg { 105 struct usb2phy_reg phy_sus; 106 struct usb2phy_reg bvalid_det_en; 107 struct usb2phy_reg bvalid_det_st; 108 struct usb2phy_reg bvalid_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg iddig_output; 113 struct usb2phy_reg iddig_en; 114 struct usb2phy_reg idfall_det_en; 115 struct usb2phy_reg idfall_det_st; 116 struct usb2phy_reg idfall_det_clr; 117 struct usb2phy_reg idrise_det_en; 118 struct usb2phy_reg idrise_det_st; 119 struct usb2phy_reg idrise_det_clr; 120 struct usb2phy_reg utmi_avalid; 121 struct usb2phy_reg utmi_bvalid; 122 struct usb2phy_reg utmi_iddig; 123 struct usb2phy_reg utmi_ls; 124 struct usb2phy_reg utmi_hstdet; 125 struct usb2phy_reg vbus_det_en; 126 }; 127 128 /** 129 * struct rockchip_usb2phy_cfg: usb-phy configuration. 130 * @reg: the address offset of grf for usb-phy config. 131 * @num_ports: specify how many ports that the phy has. 132 * @phy_tuning: phy default parameters tunning. 133 * @clkout_ctl: keep on/turn off output clk of phy. 134 * @chg_det: charger detection registers. 135 */ 136 struct rockchip_usb2phy_cfg { 137 u32 reg; 138 u32 num_ports; 139 int (*phy_tuning)(struct rockchip_usb2phy *); 140 struct usb2phy_reg clkout_ctl; 141 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 142 const struct rockchip_chg_det_reg chg_det; 143 }; 144 145 /** 146 * @dcd_retries: The retry count used to track Data contact 147 * detection process. 148 * @primary_retries: The retry count used to do usb bc detection 149 * primary stage. 150 * @grf: General Register Files register base. 151 * @usbgrf_base : USB General Register Files register base. 152 * @phy_base: the base address of USB PHY. 153 * @phy_rst: phy reset control. 154 * @phy_cfg: phy register configuration, assigned by driver data. 155 */ 156 struct rockchip_usb2phy { 157 u8 dcd_retries; 158 u8 primary_retries; 159 struct regmap *grf_base; 160 struct regmap *usbgrf_base; 161 void __iomem *phy_base; 162 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 163 struct reset_ctl phy_rst; 164 const struct rockchip_usb2phy_cfg *phy_cfg; 165 }; 166 167 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 168 { 169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 170 } 171 172 static inline int property_enable(struct regmap *base, 173 const struct usb2phy_reg *reg, bool en) 174 { 175 u32 val, mask, tmp; 176 177 tmp = en ? reg->enable : reg->disable; 178 mask = GENMASK(reg->bitend, reg->bitstart); 179 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 180 181 return regmap_write(base, reg->offset, val); 182 } 183 184 static inline bool property_enabled(struct regmap *base, 185 const struct usb2phy_reg *reg) 186 { 187 u32 tmp, orig; 188 u32 mask = GENMASK(reg->bitend, reg->bitstart); 189 190 regmap_read(base, reg->offset, &orig); 191 192 tmp = (orig & mask) >> reg->bitstart; 193 194 return tmp == reg->enable; 195 } 196 197 static inline void phy_clear_bits(void __iomem *reg, u32 bits) 198 { 199 u32 tmp = readl(reg); 200 201 tmp &= ~bits; 202 writel(tmp, reg); 203 } 204 205 static inline void phy_set_bits(void __iomem *reg, u32 bits) 206 { 207 u32 tmp = readl(reg); 208 209 tmp |= bits; 210 writel(tmp, reg); 211 } 212 213 static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val) 214 { 215 u32 tmp = readl(reg); 216 217 tmp &= ~mask; 218 tmp |= val & mask; 219 writel(tmp, reg); 220 } 221 222 static const char *chg_to_string(enum power_supply_type chg_type) 223 { 224 switch (chg_type) { 225 case POWER_SUPPLY_TYPE_USB: 226 return "USB_SDP_CHARGER"; 227 case POWER_SUPPLY_TYPE_USB_DCP: 228 return "USB_DCP_CHARGER"; 229 case POWER_SUPPLY_TYPE_USB_CDP: 230 return "USB_CDP_CHARGER"; 231 case POWER_SUPPLY_TYPE_USB_FLOATING: 232 return "USB_FLOATING_CHARGER"; 233 default: 234 return "INVALID_CHARGER"; 235 } 236 } 237 238 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 239 bool en) 240 { 241 struct regmap *base = get_reg_base(rphy); 242 243 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 244 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 245 } 246 247 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 248 bool en) 249 { 250 struct regmap *base = get_reg_base(rphy); 251 252 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 253 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 254 } 255 256 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 257 bool en) 258 { 259 struct regmap *base = get_reg_base(rphy); 260 261 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 262 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 263 } 264 265 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 266 { 267 bool vout = false; 268 struct regmap *base = get_reg_base(rphy); 269 270 while (rphy->primary_retries--) { 271 /* voltage source on DP, probe on DM */ 272 rockchip_chg_enable_primary_det(rphy, true); 273 mdelay(CHG_PRIMARY_DET_TIME); 274 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 275 if (vout) 276 break; 277 } 278 279 rockchip_chg_enable_primary_det(rphy, false); 280 return vout; 281 } 282 283 int rockchip_chg_get_type(void) 284 { 285 const struct rockchip_usb2phy_port_cfg *port_cfg; 286 enum power_supply_type chg_type; 287 struct rockchip_usb2phy *rphy; 288 struct udevice *udev; 289 struct regmap *base; 290 bool is_dcd, vout; 291 int ret; 292 293 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 294 if (ret == -ENODEV) { 295 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 296 if (ret) { 297 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 298 return ret; 299 } 300 } 301 302 rphy = dev_get_priv(udev); 303 base = get_reg_base(rphy); 304 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 305 306 /* Check USB-Vbus status first */ 307 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 308 pr_info("%s: no charger found\n", __func__); 309 return POWER_SUPPLY_TYPE_UNKNOWN; 310 } 311 312 #ifdef CONFIG_ROCKCHIP_RK3036 313 chg_type = POWER_SUPPLY_TYPE_USB; 314 goto out; 315 #endif 316 317 /* Suspend USB-PHY and put the controller in non-driving mode */ 318 property_enable(base, &port_cfg->phy_sus, true); 319 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 320 321 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 322 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 323 324 /* stage 1, start DCD processing stage */ 325 rockchip_chg_enable_dcd(rphy, true); 326 327 while (rphy->dcd_retries--) { 328 mdelay(CHG_DCD_POLL_TIME); 329 330 /* get data contact detection status */ 331 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); 332 333 if (is_dcd || !rphy->dcd_retries) { 334 /* 335 * stage 2, turn off DCD circuitry, then 336 * voltage source on DP, probe on DM. 337 */ 338 rockchip_chg_enable_dcd(rphy, false); 339 rockchip_chg_enable_primary_det(rphy, true); 340 break; 341 } 342 } 343 344 mdelay(CHG_PRIMARY_DET_TIME); 345 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); 346 rockchip_chg_enable_primary_det(rphy, false); 347 if (vout) { 348 /* stage 3, voltage source on DM, probe on DP */ 349 rockchip_chg_enable_secondary_det(rphy, true); 350 } else { 351 if (!rphy->dcd_retries) { 352 /* floating charger found */ 353 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 354 goto out; 355 } else { 356 /* 357 * Retry some times to make sure that it's 358 * really a USB SDP charger. 359 */ 360 vout = rockchip_chg_primary_det_retry(rphy); 361 if (vout) { 362 /* stage 3, voltage source on DM, probe on DP */ 363 rockchip_chg_enable_secondary_det(rphy, true); 364 } else { 365 /* USB SDP charger found */ 366 chg_type = POWER_SUPPLY_TYPE_USB; 367 goto out; 368 } 369 } 370 } 371 372 mdelay(CHG_SECONDARY_DET_TIME); 373 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); 374 /* stage 4, turn off voltage source */ 375 rockchip_chg_enable_secondary_det(rphy, false); 376 if (vout) 377 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 378 else 379 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 380 381 out: 382 /* Resume USB-PHY and put the controller in normal mode */ 383 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 384 property_enable(base, &port_cfg->phy_sus, false); 385 386 debug("charger is %s\n", chg_to_string(chg_type)); 387 388 return chg_type; 389 } 390 391 int rockchip_u2phy_vbus_detect(void) 392 { 393 int chg_type; 394 395 chg_type = rockchip_chg_get_type(); 396 397 return (chg_type == POWER_SUPPLY_TYPE_USB || 398 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 399 } 400 401 void otg_phy_init(struct dwc2_udc *dev) 402 { 403 const struct rockchip_usb2phy_port_cfg *port_cfg; 404 struct rockchip_usb2phy *rphy; 405 struct udevice *udev; 406 struct regmap *base; 407 int ret; 408 409 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 410 if (ret == -ENODEV) { 411 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev); 412 if (ret) { 413 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret); 414 return; 415 } 416 } 417 418 rphy = dev_get_priv(udev); 419 base = get_reg_base(rphy); 420 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 421 422 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 423 if(rphy->phy_cfg->clkout_ctl.disable) 424 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 425 426 /* Reset USB-PHY */ 427 property_enable(base, &port_cfg->phy_sus, true); 428 udelay(20); 429 property_enable(base, &port_cfg->phy_sus, false); 430 mdelay(2); 431 } 432 433 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 434 { 435 int ret; 436 437 if (rphy->phy_rst.dev) { 438 ret = reset_assert(&rphy->phy_rst); 439 if (ret < 0) { 440 pr_err("u2phy assert reset failed: %d", ret); 441 return ret; 442 } 443 444 udelay(20); 445 446 ret = reset_deassert(&rphy->phy_rst); 447 if (ret < 0) { 448 pr_err("u2phy deassert reset failed: %d", ret); 449 return ret; 450 } 451 452 udelay(100); 453 } 454 455 return 0; 456 } 457 458 static int rockchip_usb2phy_init(struct phy *phy) 459 { 460 struct udevice *parent = phy->dev->parent; 461 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 462 const struct rockchip_usb2phy_port_cfg *port_cfg; 463 struct regmap *base = get_reg_base(rphy); 464 465 if (phy->id == USB2PHY_PORT_OTG) { 466 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 467 } else if (phy->id == USB2PHY_PORT_HOST) { 468 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 469 } else { 470 dev_err(phy->dev, "phy id %lu not support", phy->id); 471 return -EINVAL; 472 } 473 474 property_enable(base, &port_cfg->phy_sus, false); 475 476 /* waiting for the utmi_clk to become stable */ 477 udelay(2000); 478 479 return 0; 480 } 481 482 static int rockchip_usb2phy_exit(struct phy *phy) 483 { 484 struct udevice *parent = phy->dev->parent; 485 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 486 const struct rockchip_usb2phy_port_cfg *port_cfg; 487 struct regmap *base = get_reg_base(rphy); 488 489 if (phy->id == USB2PHY_PORT_OTG) { 490 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 491 } else if (phy->id == USB2PHY_PORT_HOST) { 492 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 493 } else { 494 dev_err(phy->dev, "phy id %lu not support", phy->id); 495 return -EINVAL; 496 } 497 498 property_enable(base, &port_cfg->phy_sus, true); 499 500 return 0; 501 } 502 503 static int rockchip_usb2phy_power_on(struct phy *phy) 504 { 505 struct udevice *parent = phy->dev->parent; 506 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 507 struct udevice *vbus = rphy->vbus_supply[phy->id]; 508 int ret; 509 510 if (vbus) { 511 ret = regulator_set_enable(vbus, true); 512 if (ret) { 513 pr_err("%s: Failed to set VBus supply\n", __func__); 514 return ret; 515 } 516 } 517 518 return 0; 519 } 520 521 static int rockchip_usb2phy_power_off(struct phy *phy) 522 { 523 struct udevice *parent = phy->dev->parent; 524 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 525 struct udevice *vbus = rphy->vbus_supply[phy->id]; 526 int ret; 527 528 if (vbus) { 529 ret = regulator_set_enable(vbus, false); 530 if (ret) { 531 pr_err("%s: Failed to set VBus supply\n", __func__); 532 return ret; 533 } 534 } 535 536 return 0; 537 } 538 539 static int rockchip_usb2phy_of_xlate(struct phy *phy, 540 struct ofnode_phandle_args *args) 541 { 542 const char *dev_name = phy->dev->name; 543 struct udevice *parent = phy->dev->parent; 544 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 545 546 if (!strcasecmp(dev_name, "host-port")) { 547 phy->id = USB2PHY_PORT_HOST; 548 device_get_supply_regulator(phy->dev, "phy-supply", 549 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 550 } else if (!strcasecmp(dev_name, "otg-port")) { 551 phy->id = USB2PHY_PORT_OTG; 552 device_get_supply_regulator(phy->dev, "phy-supply", 553 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 554 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) 555 device_get_supply_regulator(phy->dev, "vbus-supply", 556 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 557 } else { 558 pr_err("%s: invalid dev name\n", __func__); 559 return -EINVAL; 560 } 561 562 return 0; 563 } 564 565 static int rockchip_usb2phy_bind(struct udevice *dev) 566 { 567 struct udevice *child; 568 ofnode subnode; 569 const char *node_name; 570 int ret; 571 572 dev_for_each_subnode(subnode, dev) { 573 if (!ofnode_valid(subnode)) { 574 debug("%s: %s subnode not found", __func__, dev->name); 575 return -ENXIO; 576 } 577 578 node_name = ofnode_get_name(subnode); 579 debug("%s: subnode %s\n", __func__, node_name); 580 581 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 582 node_name, subnode, &child); 583 if (ret) { 584 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 585 __func__, node_name); 586 return ret; 587 } 588 } 589 590 return 0; 591 } 592 593 static int rockchip_usb2phy_probe(struct udevice *dev) 594 { 595 const struct rockchip_usb2phy_cfg *phy_cfgs; 596 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 597 struct udevice *parent = dev->parent; 598 struct udevice *syscon; 599 struct resource res; 600 u32 reg, index; 601 int ret; 602 603 rphy->phy_base = (void __iomem *)dev_read_addr(dev); 604 if (IS_ERR(rphy->phy_base)) { 605 dev_err(dev, "get the base address of usb phy failed\n"); 606 } 607 608 if (!strncmp(parent->name, "root_driver", 11) && 609 dev_read_bool(dev, "rockchip,grf")) { 610 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 611 "rockchip,grf", &syscon); 612 if (ret) { 613 dev_err(dev, "get syscon grf failed\n"); 614 return ret; 615 } 616 617 rphy->grf_base = syscon_get_regmap(syscon); 618 } else { 619 rphy->grf_base = syscon_get_regmap(parent); 620 } 621 622 if (rphy->grf_base <= 0) { 623 dev_err(dev, "get syscon grf regmap failed\n"); 624 return -EINVAL; 625 } 626 627 if (dev_read_bool(dev, "rockchip,usbgrf")) { 628 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 629 "rockchip,usbgrf", &syscon); 630 if (ret) { 631 dev_err(dev, "get syscon usbgrf failed\n"); 632 return ret; 633 } 634 635 rphy->usbgrf_base = syscon_get_regmap(syscon); 636 if (rphy->usbgrf_base <= 0) { 637 dev_err(dev, "get syscon usbgrf regmap failed\n"); 638 return -EINVAL; 639 } 640 } else { 641 rphy->usbgrf_base = NULL; 642 } 643 644 if (!strncmp(parent->name, "root_driver", 11)) { 645 ret = dev_read_resource(dev, 0, &res); 646 reg = res.start; 647 } else { 648 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); 649 } 650 651 if (ret) { 652 dev_err(dev, "could not read reg\n"); 653 return -EINVAL; 654 } 655 656 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); 657 if (ret) 658 dev_dbg(dev, "no u2phy reset control specified\n"); 659 660 phy_cfgs = 661 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 662 if (!phy_cfgs) { 663 dev_err(dev, "unable to get phy_cfgs\n"); 664 return -EINVAL; 665 } 666 667 /* find out a proper config which can be matched with dt. */ 668 index = 0; 669 do { 670 if (phy_cfgs[index].reg == reg) { 671 rphy->phy_cfg = &phy_cfgs[index]; 672 break; 673 } 674 ++index; 675 } while (phy_cfgs[index].reg); 676 677 if (!rphy->phy_cfg) { 678 dev_err(dev, "no phy-config can be matched\n"); 679 return -EINVAL; 680 } 681 682 if (rphy->phy_cfg->phy_tuning) 683 rphy->phy_cfg->phy_tuning(rphy); 684 685 return 0; 686 } 687 688 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 689 { 690 struct regmap *base = get_reg_base(rphy); 691 int ret = 0; 692 693 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 694 if (rphy->phy_cfg->reg == 0x760) 695 ret = regmap_write(base, 0x76c, 0x00070004); 696 697 return ret; 698 } 699 700 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy) 701 { 702 struct regmap *base = get_reg_base(rphy); 703 unsigned int tmp, orig; 704 int ret; 705 706 if (soc_is_rk3308bs()) { 707 /* Enable otg/host port pre-emphasis during non-chirp phase */ 708 ret = regmap_read(base, 0, &orig); 709 if (ret) 710 return ret; 711 tmp = orig & ~GENMASK(2, 0); 712 tmp |= BIT(2) & GENMASK(2, 0); 713 ret = regmap_write(base, 0, tmp); 714 if (ret) 715 return ret; 716 717 /* Set otg port squelch trigger point configure to 100mv */ 718 ret = regmap_read(base, 0x004, &orig); 719 if (ret) 720 return ret; 721 tmp = orig & ~GENMASK(7, 5); 722 tmp |= 0x40 & GENMASK(7, 5); 723 ret = regmap_write(base, 0x004, tmp); 724 if (ret) 725 return ret; 726 727 ret = regmap_read(base, 0x008, &orig); 728 if (ret) 729 return ret; 730 tmp = orig & ~BIT(0); 731 tmp |= 0x1 & BIT(0); 732 ret = regmap_write(base, 0x008, tmp); 733 if (ret) 734 return ret; 735 736 /* Enable host port pre-emphasis during non-chirp phase */ 737 ret = regmap_read(base, 0x400, &orig); 738 if (ret) 739 return ret; 740 tmp = orig & ~GENMASK(2, 0); 741 tmp |= BIT(2) & GENMASK(2, 0); 742 ret = regmap_write(base, 0x400, tmp); 743 if (ret) 744 return ret; 745 746 /* Set host port squelch trigger point configure to 100mv */ 747 ret = regmap_read(base, 0x404, &orig); 748 if (ret) 749 return ret; 750 tmp = orig & ~GENMASK(7, 5); 751 tmp |= 0x40 & GENMASK(7, 5); 752 ret = regmap_write(base, 0x404, tmp); 753 if (ret) 754 return ret; 755 756 ret = regmap_read(base, 0x408, &orig); 757 if (ret) 758 return ret; 759 tmp = orig & ~BIT(0); 760 tmp |= 0x1 & BIT(0); 761 ret = regmap_write(base, 0x408, tmp); 762 if (ret) 763 return ret; 764 } 765 766 return 0; 767 } 768 769 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy) 770 { 771 struct regmap *base = get_reg_base(rphy); 772 unsigned int tmp, orig; 773 int ret; 774 775 if (soc_is_px30s()) { 776 /* Enable otg/host port pre-emphasis during non-chirp phase */ 777 ret = regmap_read(base, 0x8000, &orig); 778 if (ret) 779 return ret; 780 tmp = orig & ~GENMASK(2, 0); 781 tmp |= BIT(2) & GENMASK(2, 0); 782 ret = regmap_write(base, 0x8000, tmp); 783 if (ret) 784 return ret; 785 786 /* Set otg port squelch trigger point configure to 100mv */ 787 ret = regmap_read(base, 0x8004, &orig); 788 if (ret) 789 return ret; 790 tmp = orig & ~GENMASK(7, 5); 791 tmp |= 0x40 & GENMASK(7, 5); 792 ret = regmap_write(base, 0x8004, tmp); 793 if (ret) 794 return ret; 795 796 ret = regmap_read(base, 0x8008, &orig); 797 if (ret) 798 return ret; 799 tmp = orig & ~BIT(0); 800 tmp |= 0x1 & BIT(0); 801 ret = regmap_write(base, 0x8008, tmp); 802 if (ret) 803 return ret; 804 805 /* Enable host port pre-emphasis during non-chirp phase */ 806 ret = regmap_read(base, 0x8400, &orig); 807 if (ret) 808 return ret; 809 tmp = orig & ~GENMASK(2, 0); 810 tmp |= BIT(2) & GENMASK(2, 0); 811 ret = regmap_write(base, 0x8400, tmp); 812 if (ret) 813 return ret; 814 815 /* Set host port squelch trigger point configure to 100mv */ 816 ret = regmap_read(base, 0x8404, &orig); 817 if (ret) 818 return ret; 819 tmp = orig & ~GENMASK(7, 5); 820 tmp |= 0x40 & GENMASK(7, 5); 821 ret = regmap_write(base, 0x8404, tmp); 822 if (ret) 823 return ret; 824 825 ret = regmap_read(base, 0x8408, &orig); 826 if (ret) 827 return ret; 828 tmp = orig & ~BIT(0); 829 tmp |= 0x1 & BIT(0); 830 ret = regmap_write(base, 0x8408, tmp); 831 if (ret) 832 return ret; 833 } 834 835 return 0; 836 } 837 838 static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy) 839 { 840 /* Set HS disconnect detect mode to single ended detect mode */ 841 phy_set_bits(rphy->phy_base + 0x70, BIT(2)); 842 843 return 0; 844 } 845 846 static int rk3506_usb2phy_tuning(struct rockchip_usb2phy *rphy) 847 { 848 /* Turn off otg0 port differential receiver in suspend mode */ 849 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 850 851 /* Turn off otg1 port differential receiver in suspend mode */ 852 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 853 854 /* Set otg0 port HS eye height to 425mv(default is 450mv) */ 855 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x05 << 4)); 856 857 /* Set otg1 port HS eye height to 425mv(default is 450mv) */ 858 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x05 << 4)); 859 860 /* Choose the Tx fs/ls data as linestate from TX driver for otg0 port */ 861 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 862 863 /* Choose the Tx fs/ls data as linestate from TX driver for otg1 port */ 864 phy_update_bits(rphy->phy_base + 0x494, GENMASK(6, 3), (0x03 << 3)); 865 866 return 0; 867 } 868 869 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy) 870 { 871 if (IS_ERR(rphy->phy_base)) { 872 return PTR_ERR(rphy->phy_base); 873 } 874 875 /* Turn off otg port differential receiver in suspend mode */ 876 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); 877 878 /* Turn off host port differential receiver in suspend mode */ 879 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); 880 881 /* Set otg port HS eye height to 400mv(default is 450mv) */ 882 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4)); 883 884 /* Set host port HS eye height to 400mv(default is 450mv) */ 885 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4)); 886 887 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */ 888 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); 889 890 /* Turn on output clk of phy*/ 891 phy_update_bits(rphy->phy_base + 0x41c, GENMASK(7, 2), (0x27 << 2)); 892 893 return 0; 894 } 895 896 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy) 897 { 898 if (IS_ERR(rphy->phy_base)) { 899 return PTR_ERR(rphy->phy_base); 900 } 901 902 /* Turn off differential receiver by default to save power */ 903 phy_clear_bits(rphy->phy_base + 0x0030, BIT(2)); 904 phy_clear_bits(rphy->phy_base + 0x0430, BIT(2)); 905 906 /* Enable pre-emphasis during non-chirp phase */ 907 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); 908 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); 909 910 /* Set HS eye height to 425mv(default is 400mv) */ 911 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); 912 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); 913 914 return 0; 915 } 916 917 static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy) 918 { 919 struct regmap *base = get_reg_base(rphy); 920 int ret; 921 922 if (rphy->phy_cfg->reg == 0x0) { 923 /* Deassert SIDDQ to power on analog block */ 924 ret = regmap_write(base, 0x0010, GENMASK(29, 29) | 0x0000); 925 if (ret) 926 return ret; 927 928 /* Do reset after exit IDDQ mode */ 929 ret = rockchip_usb2phy_reset(rphy); 930 if (ret) 931 return ret; 932 933 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 934 ret = regmap_write(base, 0x000c, GENMASK(27, 24) | 0x0900); 935 if (ret) 936 return ret; 937 938 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 939 ret = regmap_write(base, 0x0010, GENMASK(20, 19) | 0x0010); 940 if (ret) 941 return ret; 942 } else if (rphy->phy_cfg->reg == 0x2000) { 943 /* Deassert SIDDQ to power on analog block */ 944 ret = regmap_write(base, 0x2010, GENMASK(29, 29) | 0x0000); 945 if (ret) 946 return ret; 947 948 /* Do reset after exit IDDQ mode */ 949 ret = rockchip_usb2phy_reset(rphy); 950 if (ret) 951 return ret; 952 953 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 954 ret = regmap_write(base, 0x200c, GENMASK(27, 24) | 0x0900); 955 if (ret) 956 return ret; 957 958 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 959 ret = regmap_write(base, 0x2010, GENMASK(20, 19) | 0x0010); 960 if (ret) 961 return ret; 962 } 963 964 return 0; 965 } 966 967 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 968 { 969 struct regmap *base = get_reg_base(rphy); 970 int ret; 971 972 /* Deassert SIDDQ to power on analog block */ 973 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); 974 if (ret) 975 return ret; 976 977 /* Do reset after exit IDDQ mode */ 978 ret = rockchip_usb2phy_reset(rphy); 979 if (ret) 980 return ret; 981 982 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 983 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); 984 if (ret) 985 return ret; 986 987 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 988 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); 989 if (ret) 990 return ret; 991 992 return 0; 993 } 994 995 static struct phy_ops rockchip_usb2phy_ops = { 996 .init = rockchip_usb2phy_init, 997 .exit = rockchip_usb2phy_exit, 998 .power_on = rockchip_usb2phy_power_on, 999 .power_off = rockchip_usb2phy_power_off, 1000 .of_xlate = rockchip_usb2phy_of_xlate, 1001 }; 1002 1003 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 1004 { 1005 .reg = 0x100, 1006 .num_ports = 2, 1007 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1008 .port_cfgs = { 1009 [USB2PHY_PORT_OTG] = { 1010 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1011 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1012 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1013 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1014 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1015 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1016 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1017 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1018 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1019 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1020 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1021 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1022 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1023 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1024 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1025 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1026 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1027 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1028 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1029 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1030 }, 1031 [USB2PHY_PORT_HOST] = { 1032 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1033 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1034 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1035 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1036 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1037 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1038 } 1039 }, 1040 .chg_det = { 1041 .opmode = { 0x0100, 3, 0, 5, 1 }, 1042 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1043 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1044 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1045 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1046 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1047 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1048 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1049 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1050 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1051 }, 1052 }, 1053 { /* sentinel */ } 1054 }; 1055 1056 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = { 1057 { 1058 .reg = 0x17c, 1059 .num_ports = 2, 1060 .clkout_ctl = { 0x017c, 11, 11, 1, 0 }, 1061 .port_cfgs = { 1062 [USB2PHY_PORT_OTG] = { 1063 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1064 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1065 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1066 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1067 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1068 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1069 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1070 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1071 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1072 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1073 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1074 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1075 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1076 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1077 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1078 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1079 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1080 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1081 }, 1082 [USB2PHY_PORT_HOST] = { 1083 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1084 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1085 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1086 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1087 } 1088 }, 1089 }, 1090 { /* sentinel */ } 1091 }; 1092 1093 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 1094 { 1095 .reg = 0x17c, 1096 .num_ports = 2, 1097 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 1098 .port_cfgs = { 1099 [USB2PHY_PORT_OTG] = { 1100 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 1101 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 1102 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 1103 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 1104 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 1105 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 1106 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 1107 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 1108 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 1109 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 1110 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 1111 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 1112 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 1113 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 1114 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 1115 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 1116 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 1117 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 1118 }, 1119 [USB2PHY_PORT_HOST] = { 1120 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 1121 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 1122 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 1123 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 1124 } 1125 }, 1126 .chg_det = { 1127 .opmode = { 0x017c, 3, 0, 5, 1 }, 1128 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 1129 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 1130 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 1131 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 1132 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 1133 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 1134 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 1135 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 1136 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 1137 }, 1138 }, 1139 { /* sentinel */ } 1140 }; 1141 1142 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 1143 { 1144 .reg = 0x760, 1145 .num_ports = 2, 1146 .phy_tuning = rk322x_usb2phy_tuning, 1147 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1148 .port_cfgs = { 1149 [USB2PHY_PORT_OTG] = { 1150 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 1151 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1152 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1153 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1154 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 1155 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 1156 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 1157 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 1158 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 1159 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 1160 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 1161 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 1162 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1163 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1164 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1165 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1166 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 1167 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1168 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 1169 }, 1170 [USB2PHY_PORT_HOST] = { 1171 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 1172 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1173 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1174 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1175 } 1176 }, 1177 .chg_det = { 1178 .opmode = { 0x0760, 3, 0, 5, 1 }, 1179 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1180 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1181 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1182 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1183 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1184 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1185 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1186 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1187 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1188 }, 1189 }, 1190 { 1191 .reg = 0x800, 1192 .num_ports = 2, 1193 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1194 .port_cfgs = { 1195 [USB2PHY_PORT_OTG] = { 1196 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 1197 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1198 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1199 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1200 }, 1201 [USB2PHY_PORT_HOST] = { 1202 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 1203 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1204 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1205 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1206 } 1207 }, 1208 }, 1209 { /* sentinel */ } 1210 }; 1211 1212 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1213 { 1214 .reg = 0x100, 1215 .num_ports = 2, 1216 .phy_tuning = rk3308_usb2phy_tuning, 1217 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1218 .port_cfgs = { 1219 [USB2PHY_PORT_OTG] = { 1220 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1221 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1222 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1223 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1224 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1225 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1226 .idfall_det_en = { 0x3020, 5, 5, 0, 1 }, 1227 .idfall_det_st = { 0x3024, 5, 5, 0, 1 }, 1228 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 }, 1229 .idrise_det_en = { 0x3020, 4, 4, 0, 1 }, 1230 .idrise_det_st = { 0x3024, 4, 4, 0, 1 }, 1231 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 }, 1232 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1233 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1234 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1235 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1236 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1237 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1238 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1239 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1240 }, 1241 [USB2PHY_PORT_HOST] = { 1242 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1243 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1244 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1245 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1246 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1247 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1248 } 1249 }, 1250 .chg_det = { 1251 .opmode = { 0x0100, 3, 0, 5, 1 }, 1252 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1253 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1254 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1255 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1256 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1257 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1258 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1259 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1260 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1261 }, 1262 }, 1263 { /* sentinel */ } 1264 }; 1265 1266 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1267 { 1268 .reg = 0x100, 1269 .num_ports = 2, 1270 .phy_tuning = rk3328_usb2phy_tuning, 1271 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1272 .port_cfgs = { 1273 [USB2PHY_PORT_OTG] = { 1274 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1275 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1276 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1277 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1278 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1279 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1280 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1281 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1282 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1283 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1284 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1285 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1286 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1287 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1288 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1289 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1290 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1291 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1292 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1293 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 1294 }, 1295 [USB2PHY_PORT_HOST] = { 1296 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 1297 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1298 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1299 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1300 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1301 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1302 } 1303 }, 1304 .chg_det = { 1305 .opmode = { 0x0100, 3, 0, 5, 1 }, 1306 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1307 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1308 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1309 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1310 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1311 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1312 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1313 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1314 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1315 }, 1316 }, 1317 { /* sentinel */ } 1318 }; 1319 1320 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 1321 { 1322 .reg = 0x700, 1323 .num_ports = 2, 1324 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1325 .port_cfgs = { 1326 [USB2PHY_PORT_OTG] = { 1327 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 1328 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1329 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1330 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1331 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1332 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1333 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1334 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 1335 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 1336 }, 1337 [USB2PHY_PORT_HOST] = { 1338 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 1339 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1340 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1341 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1342 } 1343 }, 1344 .chg_det = { 1345 .opmode = { 0x0700, 3, 0, 5, 1 }, 1346 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 1347 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 1348 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 1349 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 1350 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 1351 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 1352 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 1353 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 1354 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 1355 }, 1356 }, 1357 { /* sentinel */ } 1358 }; 1359 1360 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1361 { 1362 .reg = 0xe450, 1363 .num_ports = 2, 1364 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1365 .port_cfgs = { 1366 [USB2PHY_PORT_OTG] = { 1367 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 1368 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1369 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1370 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1371 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 1372 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 1373 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 1374 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 1375 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 1376 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 1377 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 1378 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 1379 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 1380 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1381 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1382 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 1383 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 1384 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 1385 }, 1386 [USB2PHY_PORT_HOST] = { 1387 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1388 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1389 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1390 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1391 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1392 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1393 } 1394 }, 1395 .chg_det = { 1396 .opmode = { 0xe454, 3, 0, 5, 1 }, 1397 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1398 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1399 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1400 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1401 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1402 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1403 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1404 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1405 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1406 }, 1407 }, 1408 { 1409 .reg = 0xe460, 1410 .num_ports = 2, 1411 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1412 .port_cfgs = { 1413 [USB2PHY_PORT_OTG] = { 1414 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 1415 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1416 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1417 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1418 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 1419 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 1420 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 1421 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 1422 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 1423 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 1424 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 1425 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 1426 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 1427 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1428 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1429 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 1430 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 1431 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 1432 }, 1433 [USB2PHY_PORT_HOST] = { 1434 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1435 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1436 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1437 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1438 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1439 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1440 } 1441 }, 1442 .chg_det = { 1443 .opmode = { 0xe464, 3, 0, 5, 1 }, 1444 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 1445 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 1446 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 1447 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 1448 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 1449 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 1450 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 1451 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 1452 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 1453 }, 1454 }, 1455 { /* sentinel */ } 1456 }; 1457 1458 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = { 1459 { 1460 .reg = 0xff3e0000, 1461 .num_ports = 1, 1462 .phy_tuning = rv1106_usb2phy_tuning, 1463 .clkout_ctl = { 0x0058, 4, 4, 1, 0 }, 1464 .port_cfgs = { 1465 [USB2PHY_PORT_OTG] = { 1466 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 }, 1467 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 }, 1468 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 }, 1469 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 }, 1470 .iddig_output = { 0x0050, 10, 10, 0, 1 }, 1471 .iddig_en = { 0x0050, 9, 9, 0, 1 }, 1472 .idfall_det_en = { 0x0100, 5, 5, 0, 1 }, 1473 .idfall_det_st = { 0x0104, 5, 5, 0, 1 }, 1474 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 }, 1475 .idrise_det_en = { 0x0100, 4, 4, 0, 1 }, 1476 .idrise_det_st = { 0x0104, 4, 4, 0, 1 }, 1477 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 }, 1478 .ls_det_en = { 0x0100, 0, 0, 0, 1 }, 1479 .ls_det_st = { 0x0104, 0, 0, 0, 1 }, 1480 .ls_det_clr = { 0x0108, 0, 0, 0, 1 }, 1481 .utmi_avalid = { 0x0060, 10, 10, 0, 1 }, 1482 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 }, 1483 .utmi_iddig = { 0x0060, 6, 6, 0, 1 }, 1484 .utmi_ls = { 0x0060, 5, 4, 0, 1 }, 1485 }, 1486 }, 1487 .chg_det = { 1488 .opmode = { 0x0050, 3, 0, 5, 1 }, 1489 .cp_det = { 0x0060, 13, 13, 0, 1 }, 1490 .dcp_det = { 0x0060, 12, 12, 0, 1 }, 1491 .dp_det = { 0x0060, 14, 14, 0, 1 }, 1492 .idm_sink_en = { 0x0058, 8, 8, 0, 1 }, 1493 .idp_sink_en = { 0x0058, 7, 7, 0, 1 }, 1494 .idp_src_en = { 0x0058, 9, 9, 0, 1 }, 1495 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 }, 1496 .vdm_src_en = { 0x0058, 12, 12, 0, 1 }, 1497 .vdp_src_en = { 0x0058, 11, 11, 0, 1 }, 1498 }, 1499 }, 1500 { /* sentinel */ } 1501 }; 1502 1503 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1504 { 1505 .reg = 0x100, 1506 .num_ports = 2, 1507 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1508 .port_cfgs = { 1509 [USB2PHY_PORT_OTG] = { 1510 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 1511 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1512 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1513 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1514 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1515 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1516 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1517 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1518 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1519 }, 1520 [USB2PHY_PORT_HOST] = { 1521 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1522 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1523 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1524 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1525 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1526 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1527 } 1528 }, 1529 .chg_det = { 1530 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1531 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1532 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1533 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1534 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1535 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1536 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1537 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1538 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1539 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1540 }, 1541 }, 1542 { /* sentinel */ } 1543 }; 1544 1545 static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { 1546 { 1547 .reg = 0xff2b0000, 1548 .num_ports = 2, 1549 .phy_tuning = rk3506_usb2phy_tuning, 1550 .port_cfgs = { 1551 [USB2PHY_PORT_OTG] = { 1552 .phy_sus = { 0x0060, 8, 0, 0, 0x1d1 }, 1553 .bvalid_det_en = { 0x0150, 2, 2, 0, 1 }, 1554 .bvalid_det_st = { 0x0154, 2, 2, 0, 1 }, 1555 .bvalid_det_clr = { 0x0158, 2, 2, 0, 1 }, 1556 .iddig_output = { 0x0060, 10, 10, 0, 1 }, 1557 .iddig_en = { 0x0060, 9, 9, 0, 1 }, 1558 .idfall_det_en = { 0x0150, 5, 5, 0, 1 }, 1559 .idfall_det_st = { 0x0154, 5, 5, 0, 1 }, 1560 .idfall_det_clr = { 0x0158, 5, 5, 0, 1 }, 1561 .idrise_det_en = { 0x0150, 4, 4, 0, 1 }, 1562 .idrise_det_st = { 0x0154, 4, 4, 0, 1 }, 1563 .idrise_det_clr = { 0x0158, 4, 4, 0, 1 }, 1564 .ls_det_en = { 0x0150, 0, 0, 0, 1 }, 1565 .ls_det_st = { 0x0154, 0, 0, 0, 1 }, 1566 .ls_det_clr = { 0x0158, 0, 0, 0, 1 }, 1567 .utmi_avalid = { 0x0118, 1, 1, 0, 1 }, 1568 .utmi_bvalid = { 0x0118, 0, 0, 0, 1 }, 1569 .utmi_iddig = { 0x0118, 6, 6, 0, 1 }, 1570 .utmi_ls = { 0x0118, 5, 4, 0, 1 }, 1571 }, 1572 [USB2PHY_PORT_HOST] = { 1573 .phy_sus = { 0x0070, 8, 0, 0x1d2, 0x1d1 }, 1574 .ls_det_en = { 0x0170, 0, 0, 0, 1 }, 1575 .ls_det_st = { 0x0174, 0, 0, 0, 1 }, 1576 .ls_det_clr = { 0x0178, 0, 0, 0, 1 }, 1577 .utmi_ls = { 0x0118, 13, 12, 0, 1 }, 1578 .utmi_hstdet = { 0x0118, 15, 15, 0, 1 } 1579 } 1580 }, 1581 .chg_det = { 1582 .opmode = { 0x0060, 3, 0, 5, 1 }, 1583 .cp_det = { 0x0118, 19, 19, 0, 1 }, 1584 .dcp_det = { 0x0118, 18, 18, 0, 1 }, 1585 .dp_det = { 0x0118, 20, 20, 0, 1 }, 1586 .idm_sink_en = { 0x006c, 1, 1, 0, 1 }, 1587 .idp_sink_en = { 0x006c, 0, 0, 0, 1 }, 1588 .idp_src_en = { 0x006c, 2, 2, 0, 1 }, 1589 .rdm_pdwn_en = { 0x006c, 3, 3, 0, 1 }, 1590 .vdm_src_en = { 0x006c, 5, 5, 0, 1 }, 1591 .vdp_src_en = { 0x006c, 4, 4, 0, 1 }, 1592 }, 1593 } 1594 }; 1595 1596 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { 1597 { 1598 .reg = 0xffdf0000, 1599 .num_ports = 2, 1600 .phy_tuning = rk3528_usb2phy_tuning, 1601 .port_cfgs = { 1602 [USB2PHY_PORT_OTG] = { 1603 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 }, 1604 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 }, 1605 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 }, 1606 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 }, 1607 .iddig_output = { 0x6004c, 10, 10, 0, 1 }, 1608 .iddig_en = { 0x6004c, 9, 9, 0, 1 }, 1609 .idfall_det_en = { 0x60074, 5, 5, 0, 1 }, 1610 .idfall_det_st = { 0x60078, 5, 5, 0, 1 }, 1611 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 }, 1612 .idrise_det_en = { 0x60074, 4, 4, 0, 1 }, 1613 .idrise_det_st = { 0x60078, 4, 4, 0, 1 }, 1614 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 }, 1615 .ls_det_en = { 0x60074, 0, 0, 0, 1 }, 1616 .ls_det_st = { 0x60078, 0, 0, 0, 1 }, 1617 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, 1618 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, 1619 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, 1620 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 }, 1621 .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, 1622 }, 1623 [USB2PHY_PORT_HOST] = { 1624 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 }, 1625 .ls_det_en = { 0x60090, 0, 0, 0, 1 }, 1626 .ls_det_st = { 0x60094, 0, 0, 0, 1 }, 1627 .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, 1628 .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, 1629 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } 1630 } 1631 }, 1632 .chg_det = { 1633 .opmode = { 0x6004c, 3, 0, 5, 1 }, 1634 .cp_det = { 0x6006c, 19, 19, 0, 1 }, 1635 .dcp_det = { 0x6006c, 18, 18, 0, 1 }, 1636 .dp_det = { 0x6006c, 20, 20, 0, 1 }, 1637 .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, 1638 .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, 1639 .idp_src_en = { 0x60058, 2, 2, 0, 1 }, 1640 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, 1641 .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, 1642 .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, 1643 }, 1644 } 1645 }; 1646 1647 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = { 1648 { 1649 .reg = 0xff740000, 1650 .num_ports = 2, 1651 .phy_tuning = rk3562_usb2phy_tuning, 1652 .clkout_ctl = { 0x0108, 4, 4, 1, 0 }, 1653 .port_cfgs = { 1654 [USB2PHY_PORT_OTG] = { 1655 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1656 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1657 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1658 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1659 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 1660 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 1661 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 1662 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 1663 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 1664 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 1665 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 1666 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 1667 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1668 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1669 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1670 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1671 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1672 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 1673 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1674 }, 1675 [USB2PHY_PORT_HOST] = { 1676 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 }, 1677 .ls_det_en = { 0x0110, 1, 1, 0, 1 }, 1678 .ls_det_st = { 0x0114, 1, 1, 0, 1 }, 1679 .ls_det_clr = { 0x0118, 1, 1, 0, 1 }, 1680 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1681 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1682 } 1683 }, 1684 .chg_det = { 1685 .opmode = { 0x0100, 3, 0, 5, 1 }, 1686 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1687 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1688 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1689 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1690 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1691 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1692 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1693 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1694 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1695 }, 1696 }, 1697 { /* sentinel */ } 1698 }; 1699 1700 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1701 { 1702 .reg = 0xfe8a0000, 1703 .num_ports = 2, 1704 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1705 .port_cfgs = { 1706 [USB2PHY_PORT_OTG] = { 1707 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, 1708 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, 1709 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, 1710 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, 1711 .iddig_output = { 0x0000, 10, 10, 0, 1 }, 1712 .iddig_en = { 0x0000, 9, 9, 0, 1 }, 1713 .idfall_det_en = { 0x0080, 5, 5, 0, 1 }, 1714 .idfall_det_st = { 0x0084, 5, 5, 0, 1 }, 1715 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 }, 1716 .idrise_det_en = { 0x0080, 4, 4, 0, 1 }, 1717 .idrise_det_st = { 0x0084, 4, 4, 0, 1 }, 1718 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 }, 1719 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1720 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1721 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1722 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1723 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1724 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 }, 1725 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1726 }, 1727 [USB2PHY_PORT_HOST] = { 1728 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1729 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1730 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1731 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1732 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1733 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1734 } 1735 }, 1736 .chg_det = { 1737 .opmode = { 0x0000, 3, 0, 5, 1 }, 1738 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1739 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1740 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1741 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1742 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1743 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1744 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1745 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1746 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1747 }, 1748 }, 1749 { 1750 .reg = 0xfe8b0000, 1751 .num_ports = 2, 1752 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1753 .port_cfgs = { 1754 [USB2PHY_PORT_OTG] = { 1755 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1756 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1757 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1758 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1759 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1760 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1761 }, 1762 [USB2PHY_PORT_HOST] = { 1763 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1764 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1765 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1766 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1767 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1768 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1769 } 1770 }, 1771 }, 1772 { /* sentinel */ } 1773 }; 1774 1775 static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { 1776 { 1777 .reg = 0x0000, 1778 .num_ports = 1, 1779 .phy_tuning = rk3576_usb2phy_tuning, 1780 .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, 1781 .port_cfgs = { 1782 [USB2PHY_PORT_OTG] = { 1783 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, 1784 .ls_det_en = { 0x00c0, 0, 0, 0, 1 }, 1785 .ls_det_st = { 0x00c4, 0, 0, 0, 1 }, 1786 .ls_det_clr = { 0x00c8, 0, 0, 0, 1 }, 1787 .utmi_avalid = { 0x0080, 1, 1, 0, 1 }, 1788 .utmi_bvalid = { 0x0080, 0, 0, 0, 1 }, 1789 .utmi_iddig = { 0x0080, 6, 6, 0, 1 }, 1790 .utmi_ls = { 0x0080, 5, 4, 0, 1 }, 1791 } 1792 }, 1793 .chg_det = { 1794 .opmode = { 0x0000, 8, 0, 0x055, 0x001 }, 1795 .cp_det = { 0x0080, 8, 8, 0, 1 }, 1796 .dcp_det = { 0x0080, 8, 8, 0, 1 }, 1797 .dp_det = { 0x0080, 9, 9, 1, 0 }, 1798 .idm_sink_en = { 0x0010, 5, 5, 1, 0 }, 1799 .idp_sink_en = { 0x0010, 5, 5, 0, 1 }, 1800 .idp_src_en = { 0x0010, 14, 14, 0, 1 }, 1801 .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 }, 1802 .vdm_src_en = { 0x0010, 7, 6, 0, 3 }, 1803 .vdp_src_en = { 0x0010, 7, 6, 0, 3 }, 1804 }, 1805 }, 1806 { 1807 .reg = 0x2000, 1808 .num_ports = 1, 1809 .phy_tuning = rk3576_usb2phy_tuning, 1810 .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, 1811 .port_cfgs = { 1812 [USB2PHY_PORT_OTG] = { 1813 .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 }, 1814 .ls_det_en = { 0x20c0, 0, 0, 0, 1 }, 1815 .ls_det_st = { 0x20c4, 0, 0, 0, 1 }, 1816 .ls_det_clr = { 0x20c8, 0, 0, 0, 1 }, 1817 .utmi_avalid = { 0x2080, 1, 1, 0, 1 }, 1818 .utmi_bvalid = { 0x2080, 0, 0, 0, 1 }, 1819 .utmi_iddig = { 0x2080, 6, 6, 0, 1 }, 1820 .utmi_ls = { 0x2080, 5, 4, 0, 1 }, 1821 } 1822 }, 1823 }, 1824 { /* sentinel */ } 1825 }; 1826 1827 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1828 { 1829 .reg = 0x0000, 1830 .num_ports = 1, 1831 .phy_tuning = rk3588_usb2phy_tuning, 1832 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1833 .port_cfgs = { 1834 [USB2PHY_PORT_OTG] = { 1835 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1836 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1837 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1838 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1839 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, 1840 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, 1841 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 }, 1842 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1843 } 1844 }, 1845 .chg_det = { 1846 .opmode = { 0x0008, 2, 2, 1, 0 }, 1847 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1848 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1849 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1850 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1851 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1852 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1853 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1854 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1855 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1856 }, 1857 }, 1858 { 1859 .reg = 0x4000, 1860 .num_ports = 1, 1861 .phy_tuning = rk3588_usb2phy_tuning, 1862 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1863 .port_cfgs = { 1864 /* Select suspend control from controller */ 1865 [USB2PHY_PORT_OTG] = { 1866 .phy_sus = { 0x000c, 11, 11, 0, 0 }, 1867 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1868 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1869 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1870 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1871 } 1872 }, 1873 }, 1874 { 1875 .reg = 0x8000, 1876 .num_ports = 1, 1877 .phy_tuning = rk3588_usb2phy_tuning, 1878 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1879 .port_cfgs = { 1880 [USB2PHY_PORT_HOST] = { 1881 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1882 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1883 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1884 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1885 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1886 } 1887 }, 1888 }, 1889 { 1890 .reg = 0xc000, 1891 .num_ports = 1, 1892 .phy_tuning = rk3588_usb2phy_tuning, 1893 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1894 .port_cfgs = { 1895 [USB2PHY_PORT_HOST] = { 1896 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1897 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1898 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1899 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1900 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1901 } 1902 }, 1903 }, 1904 { /* sentinel */ } 1905 }; 1906 1907 static const struct udevice_id rockchip_usb2phy_ids[] = { 1908 #ifdef CONFIG_ROCKCHIP_RK1808 1909 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1910 #endif 1911 #ifdef CONFIG_ROCKCHIP_RK3036 1912 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs }, 1913 #endif 1914 #if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126 1915 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1916 #endif 1917 #ifdef CONFIG_ROCKCHIP_RK322X 1918 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1919 #endif 1920 #ifdef CONFIG_ROCKCHIP_RK3308 1921 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs }, 1922 #endif 1923 #if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30 1924 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1925 #endif 1926 #ifdef CONFIG_ROCKCHIP_RK3368 1927 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1928 #endif 1929 #ifdef CONFIG_ROCKCHIP_RK3399 1930 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1931 #endif 1932 #ifdef CONFIG_ROCKCHIP_RK3506 1933 { .compatible = "rockchip,rk3506-usb2phy", .data = (ulong)&rk3506_phy_cfgs }, 1934 #endif 1935 #ifdef CONFIG_ROCKCHIP_RK3528 1936 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs }, 1937 #endif 1938 #ifdef CONFIG_ROCKCHIP_RK3562 1939 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs }, 1940 #endif 1941 #ifdef CONFIG_ROCKCHIP_RK3568 1942 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs }, 1943 #endif 1944 #ifdef CONFIG_ROCKCHIP_RK3576 1945 { .compatible = "rockchip,rk3576-usb2phy", .data = (ulong)&rk3576_phy_cfgs }, 1946 #endif 1947 #ifdef CONFIG_ROCKCHIP_RK3588 1948 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs }, 1949 #endif 1950 #ifdef CONFIG_ROCKCHIP_RV1106 1951 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs }, 1952 #endif 1953 #ifdef CONFIG_ROCKCHIP_RV1108 1954 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1955 #endif 1956 { } 1957 }; 1958 1959 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1960 .name = "rockchip_usb2phy_port", 1961 .id = UCLASS_PHY, 1962 .ops = &rockchip_usb2phy_ops, 1963 }; 1964 1965 U_BOOT_DRIVER(rockchip_usb2phy) = { 1966 .name = "rockchip_usb2phy", 1967 .id = UCLASS_PHY, 1968 .of_match = rockchip_usb2phy_ids, 1969 .probe = rockchip_usb2phy_probe, 1970 .bind = rockchip_usb2phy_bind, 1971 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1972 }; 1973