1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <generic-phy.h> 10 #include <syscon.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 14 #include "../usb/gadget/dwc2_udc_otg_priv.h" 15 16 #define U2PHY_BIT_WRITEABLE_SHIFT 16 17 #define CHG_DCD_MAX_RETRIES 6 18 #define CHG_PRI_MAX_RETRIES 2 19 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 20 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 21 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 22 23 struct rockchip_usb2phy; 24 25 enum power_supply_type { 26 POWER_SUPPLY_TYPE_UNKNOWN = 0, 27 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 28 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 29 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 30 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 31 }; 32 33 enum rockchip_usb2phy_port_id { 34 USB2PHY_PORT_OTG, 35 USB2PHY_PORT_HOST, 36 USB2PHY_NUM_PORTS, 37 }; 38 39 struct usb2phy_reg { 40 u32 offset; 41 u32 bitend; 42 u32 bitstart; 43 u32 disable; 44 u32 enable; 45 }; 46 47 /** 48 * struct rockchip_chg_det_reg: usb charger detect registers 49 * @cp_det: charging port detected successfully. 50 * @dcp_det: dedicated charging port detected successfully. 51 * @dp_det: assert data pin connect successfully. 52 * @idm_sink_en: open dm sink curren. 53 * @idp_sink_en: open dp sink current. 54 * @idp_src_en: open dm source current. 55 * @rdm_pdwn_en: open dm pull down resistor. 56 * @vdm_src_en: open dm voltage source. 57 * @vdp_src_en: open dp voltage source. 58 * @opmode: utmi operational mode. 59 */ 60 struct rockchip_chg_det_reg { 61 struct usb2phy_reg cp_det; 62 struct usb2phy_reg dcp_det; 63 struct usb2phy_reg dp_det; 64 struct usb2phy_reg idm_sink_en; 65 struct usb2phy_reg idp_sink_en; 66 struct usb2phy_reg idp_src_en; 67 struct usb2phy_reg rdm_pdwn_en; 68 struct usb2phy_reg vdm_src_en; 69 struct usb2phy_reg vdp_src_en; 70 struct usb2phy_reg opmode; 71 }; 72 73 /** 74 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 75 * @phy_sus: phy suspend register. 76 * @bvalid_det_en: vbus valid rise detection enable register. 77 * @bvalid_det_st: vbus valid rise detection status register. 78 * @bvalid_det_clr: vbus valid rise detection clear register. 79 * @ls_det_en: linestate detection enable register. 80 * @ls_det_st: linestate detection state register. 81 * @ls_det_clr: linestate detection clear register. 82 * @iddig_output: iddig output from grf. 83 * @iddig_en: utmi iddig select between grf and phy, 84 * 0: from phy; 1: from grf 85 * @idfall_det_en: id fall detection enable register. 86 * @idfall_det_st: id fall detection state register. 87 * @idfall_det_clr: id fall detection clear register. 88 * @idrise_det_en: id rise detection enable register. 89 * @idrise_det_st: id rise detection state register. 90 * @idrise_det_clr: id rise detection clear register. 91 * @utmi_avalid: utmi vbus avalid status register. 92 * @utmi_bvalid: utmi vbus bvalid status register. 93 * @utmi_iddig: otg port id pin status register. 94 * @utmi_ls: utmi linestate state register. 95 * @utmi_hstdet: utmi host disconnect register. 96 * @vbus_det_en: vbus detect function power down register. 97 */ 98 struct rockchip_usb2phy_port_cfg { 99 struct usb2phy_reg phy_sus; 100 struct usb2phy_reg bvalid_det_en; 101 struct usb2phy_reg bvalid_det_st; 102 struct usb2phy_reg bvalid_det_clr; 103 struct usb2phy_reg ls_det_en; 104 struct usb2phy_reg ls_det_st; 105 struct usb2phy_reg ls_det_clr; 106 struct usb2phy_reg iddig_output; 107 struct usb2phy_reg iddig_en; 108 struct usb2phy_reg idfall_det_en; 109 struct usb2phy_reg idfall_det_st; 110 struct usb2phy_reg idfall_det_clr; 111 struct usb2phy_reg idrise_det_en; 112 struct usb2phy_reg idrise_det_st; 113 struct usb2phy_reg idrise_det_clr; 114 struct usb2phy_reg utmi_avalid; 115 struct usb2phy_reg utmi_bvalid; 116 struct usb2phy_reg utmi_iddig; 117 struct usb2phy_reg utmi_ls; 118 struct usb2phy_reg utmi_hstdet; 119 struct usb2phy_reg vbus_det_en; 120 }; 121 122 /** 123 * struct rockchip_usb2phy_cfg: usb-phy configuration. 124 * @reg: the address offset of grf for usb-phy config. 125 * @num_ports: specify how many ports that the phy has. 126 * @phy_tuning: phy default parameters tunning. 127 * @clkout_ctl: keep on/turn off output clk of phy. 128 * @chg_det: charger detection registers. 129 */ 130 struct rockchip_usb2phy_cfg { 131 u32 reg; 132 u32 num_ports; 133 int (*phy_tuning)(struct rockchip_usb2phy *); 134 struct usb2phy_reg clkout_ctl; 135 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 136 const struct rockchip_chg_det_reg chg_det; 137 }; 138 139 /** 140 * @dcd_retries: The retry count used to track Data contact 141 * detection process. 142 * @primary_retries: The retry count used to do usb bc detection 143 * primary stage. 144 * @grf: General Register Files register base. 145 * @usbgrf_base : USB General Register Files register base. 146 * @phy_cfg: phy register configuration, assigned by driver data. 147 */ 148 struct rockchip_usb2phy { 149 u8 dcd_retries; 150 u8 primary_retries; 151 void __iomem *grf_base; 152 void __iomem *usbgrf_base; 153 const struct rockchip_usb2phy_cfg *phy_cfg; 154 }; 155 156 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 157 { 158 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 159 } 160 161 static inline int property_enable(void __iomem *base, 162 const struct usb2phy_reg *reg, bool en) 163 { 164 u32 val, mask, tmp; 165 166 tmp = en ? reg->enable : reg->disable; 167 mask = GENMASK(reg->bitend, reg->bitstart); 168 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 169 170 return writel(val, base + reg->offset); 171 } 172 173 static inline bool property_enabled(void __iomem *base, 174 const struct usb2phy_reg *reg) 175 { 176 u32 tmp, orig; 177 u32 mask = GENMASK(reg->bitend, reg->bitstart); 178 179 orig = readl(base + reg->offset); 180 181 tmp = (orig & mask) >> reg->bitstart; 182 183 return tmp == reg->enable; 184 } 185 186 static const char *chg_to_string(enum power_supply_type chg_type) 187 { 188 switch (chg_type) { 189 case POWER_SUPPLY_TYPE_USB: 190 return "USB_SDP_CHARGER"; 191 case POWER_SUPPLY_TYPE_USB_DCP: 192 return "USB_DCP_CHARGER"; 193 case POWER_SUPPLY_TYPE_USB_CDP: 194 return "USB_CDP_CHARGER"; 195 case POWER_SUPPLY_TYPE_USB_FLOATING: 196 return "USB_FLOATING_CHARGER"; 197 default: 198 return "INVALID_CHARGER"; 199 } 200 } 201 202 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 203 bool en) 204 { 205 void __iomem *base = get_reg_base(rphy); 206 207 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 208 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 209 } 210 211 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 212 bool en) 213 { 214 void __iomem *base = get_reg_base(rphy); 215 216 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 217 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 218 } 219 220 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 221 bool en) 222 { 223 void __iomem *base = get_reg_base(rphy); 224 225 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 226 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 227 } 228 229 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 230 { 231 bool vout = false; 232 233 while (rphy->primary_retries--) { 234 /* voltage source on DP, probe on DM */ 235 rockchip_chg_enable_primary_det(rphy, true); 236 mdelay(CHG_PRIMARY_DET_TIME); 237 vout = property_enabled(rphy->grf_base, 238 &rphy->phy_cfg->chg_det.cp_det); 239 if (vout) 240 break; 241 } 242 243 rockchip_chg_enable_primary_det(rphy, false); 244 return vout; 245 } 246 247 int rockchip_chg_get_type(void) 248 { 249 const struct rockchip_usb2phy_port_cfg *port_cfg; 250 enum power_supply_type chg_type; 251 struct rockchip_usb2phy *rphy; 252 struct udevice *udev; 253 void __iomem *base; 254 bool is_dcd, vout; 255 int ret; 256 257 ret = uclass_get_device(UCLASS_PHY, 0, &udev); 258 if (ret == -ENODEV) { 259 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 260 return ret; 261 } 262 263 rphy = dev_get_priv(udev); 264 base = get_reg_base(rphy); 265 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 266 267 /* Suspend USB-PHY and put the controller in non-driving mode */ 268 property_enable(base, &port_cfg->phy_sus, true); 269 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 270 271 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 272 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 273 274 /* stage 1, start DCD processing stage */ 275 rockchip_chg_enable_dcd(rphy, true); 276 277 while (rphy->dcd_retries--) { 278 mdelay(CHG_DCD_POLL_TIME); 279 280 /* get data contact detection status */ 281 is_dcd = property_enabled(rphy->grf_base, 282 &rphy->phy_cfg->chg_det.dp_det); 283 284 if (is_dcd || !rphy->dcd_retries) { 285 /* 286 * stage 2, turn off DCD circuitry, then 287 * voltage source on DP, probe on DM. 288 */ 289 rockchip_chg_enable_dcd(rphy, false); 290 rockchip_chg_enable_primary_det(rphy, true); 291 break; 292 } 293 } 294 295 mdelay(CHG_PRIMARY_DET_TIME); 296 vout = property_enabled(rphy->grf_base, 297 &rphy->phy_cfg->chg_det.cp_det); 298 rockchip_chg_enable_primary_det(rphy, false); 299 if (vout) { 300 /* stage 3, voltage source on DM, probe on DP */ 301 rockchip_chg_enable_secondary_det(rphy, true); 302 } else { 303 if (!rphy->dcd_retries) { 304 /* floating charger found */ 305 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 306 goto out; 307 } else { 308 /* 309 * Retry some times to make sure that it's 310 * really a USB SDP charger. 311 */ 312 vout = rockchip_chg_primary_det_retry(rphy); 313 if (vout) { 314 /* stage 3, voltage source on DM, probe on DP */ 315 rockchip_chg_enable_secondary_det(rphy, true); 316 } else { 317 /* USB SDP charger found */ 318 chg_type = POWER_SUPPLY_TYPE_USB; 319 goto out; 320 } 321 } 322 } 323 324 mdelay(CHG_SECONDARY_DET_TIME); 325 vout = property_enabled(rphy->grf_base, 326 &rphy->phy_cfg->chg_det.dcp_det); 327 /* stage 4, turn off voltage source */ 328 rockchip_chg_enable_secondary_det(rphy, false); 329 if (vout) 330 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 331 else 332 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 333 334 out: 335 /* Resume USB-PHY and put the controller in normal mode */ 336 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 337 property_enable(base, &port_cfg->phy_sus, false); 338 339 debug("charger is %s\n", chg_to_string(chg_type)); 340 341 return chg_type; 342 } 343 344 void otg_phy_init(struct dwc2_udc *dev) 345 { 346 const struct rockchip_usb2phy_port_cfg *port_cfg; 347 struct rockchip_usb2phy *rphy; 348 struct udevice *udev; 349 void __iomem *base; 350 int ret; 351 352 ret = uclass_get_device(UCLASS_PHY, 0, &udev); 353 if (ret == -ENODEV) { 354 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 355 return; 356 } 357 358 rphy = dev_get_priv(udev); 359 base = get_reg_base(rphy); 360 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 361 362 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 363 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 364 365 /* Reset USB-PHY */ 366 property_enable(base, &port_cfg->phy_sus, true); 367 udelay(20); 368 property_enable(base, &port_cfg->phy_sus, false); 369 mdelay(2); 370 } 371 372 static int rockchip_usb2phy_init(struct phy *phy) 373 { 374 struct rockchip_usb2phy *rphy; 375 const struct rockchip_usb2phy_port_cfg *port_cfg; 376 void __iomem *base; 377 378 rphy = dev_get_priv(phy->dev); 379 base = get_reg_base(rphy); 380 381 if (phy->id == USB2PHY_PORT_OTG) { 382 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 383 } else if (phy->id == USB2PHY_PORT_HOST) { 384 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 385 } else { 386 dev_err(phy->dev, "phy id %lu not support", phy->id); 387 return -EINVAL; 388 } 389 390 property_enable(base, &port_cfg->phy_sus, false); 391 392 /* waiting for the utmi_clk to become stable */ 393 udelay(2000); 394 395 return 0; 396 } 397 398 static int rockchip_usb2phy_exit(struct phy *phy) 399 { 400 struct rockchip_usb2phy *rphy; 401 const struct rockchip_usb2phy_port_cfg *port_cfg; 402 void __iomem *base; 403 404 rphy = dev_get_priv(phy->dev); 405 base = get_reg_base(rphy); 406 407 if (phy->id == USB2PHY_PORT_OTG) { 408 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 409 } else if (phy->id == USB2PHY_PORT_HOST) { 410 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 411 } else { 412 dev_err(phy->dev, "phy id %lu not support", phy->id); 413 return -EINVAL; 414 } 415 416 property_enable(base, &port_cfg->phy_sus, true); 417 418 return 0; 419 } 420 421 static int rockchip_usb2phy_probe(struct udevice *dev) 422 { 423 const struct rockchip_usb2phy_cfg *phy_cfgs; 424 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 425 struct udevice *parent = dev->parent; 426 u32 reg, index; 427 428 if (!strncmp(parent->name, "root_driver", 11) && 429 dev_read_bool(dev, "rockchip,grf")) 430 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 431 else 432 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 433 434 if (rphy->grf_base <= 0) { 435 dev_err(dev, "get syscon grf failed\n"); 436 return -EINVAL; 437 } 438 439 if (dev_read_bool(dev, "rockchip,usbgrf")) { 440 rphy->usbgrf_base = 441 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 442 if (rphy->usbgrf_base <= 0) { 443 dev_err(dev, "get syscon usbgrf failed\n"); 444 return -EINVAL; 445 } 446 } else { 447 rphy->usbgrf_base = NULL; 448 } 449 450 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 451 dev_err(dev, "could not read reg\n"); 452 return -EINVAL; 453 } 454 455 phy_cfgs = 456 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 457 if (!phy_cfgs) { 458 dev_err(dev, "unable to get phy_cfgs\n"); 459 return -EINVAL; 460 } 461 462 /* find out a proper config which can be matched with dt. */ 463 index = 0; 464 while (phy_cfgs[index].reg) { 465 if (phy_cfgs[index].reg == reg) { 466 rphy->phy_cfg = &phy_cfgs[index]; 467 break; 468 } 469 ++index; 470 } 471 472 if (!rphy->phy_cfg) { 473 dev_err(dev, "no phy-config can be matched\n"); 474 return -EINVAL; 475 } 476 477 return 0; 478 } 479 480 static struct phy_ops rockchip_usb2phy_ops = { 481 .init = rockchip_usb2phy_init, 482 .exit = rockchip_usb2phy_exit, 483 }; 484 485 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 486 { 487 .reg = 0x17c, 488 .num_ports = 2, 489 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 490 .port_cfgs = { 491 [USB2PHY_PORT_OTG] = { 492 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 493 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 494 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 495 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 496 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 497 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 498 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 499 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 500 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 501 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 502 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 503 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 504 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 505 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 506 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 507 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 508 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 509 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 510 }, 511 [USB2PHY_PORT_HOST] = { 512 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 513 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 514 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 515 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 516 } 517 }, 518 .chg_det = { 519 .opmode = { 0x017c, 3, 0, 5, 1 }, 520 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 521 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 522 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 523 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 524 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 525 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 526 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 527 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 528 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 529 }, 530 }, 531 { /* sentinel */ } 532 }; 533 534 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 535 { 536 .reg = 0x100, 537 .num_ports = 2, 538 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 539 .port_cfgs = { 540 [USB2PHY_PORT_OTG] = { 541 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 542 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 543 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 544 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 545 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 546 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 547 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 548 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 549 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 550 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 551 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 552 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 553 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 554 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 555 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 556 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 557 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 558 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 559 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 560 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 561 }, 562 [USB2PHY_PORT_HOST] = { 563 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 564 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 565 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 566 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 567 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 568 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 569 } 570 }, 571 .chg_det = { 572 .opmode = { 0x0100, 3, 0, 5, 1 }, 573 .cp_det = { 0x0120, 24, 24, 0, 1 }, 574 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 575 .dp_det = { 0x0120, 25, 25, 0, 1 }, 576 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 577 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 578 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 579 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 580 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 581 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 582 }, 583 }, 584 { /* sentinel */ } 585 }; 586 587 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 588 { 589 .reg = 0x100, 590 .num_ports = 2, 591 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 592 .port_cfgs = { 593 [USB2PHY_PORT_OTG] = { 594 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 595 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 596 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 597 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 598 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 599 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 600 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 601 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 602 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 603 }, 604 [USB2PHY_PORT_HOST] = { 605 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 606 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 607 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 608 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 609 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 610 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 611 } 612 }, 613 .chg_det = { 614 .opmode = { 0x0100, 3, 0, 5, 1 }, 615 .cp_det = { 0x0804, 1, 1, 0, 1 }, 616 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 617 .dp_det = { 0x0804, 2, 2, 0, 1 }, 618 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 619 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 620 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 621 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 622 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 623 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 624 }, 625 }, 626 { /* sentinel */ } 627 }; 628 629 static const struct udevice_id rockchip_usb2phy_ids[] = { 630 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 631 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 632 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 633 { } 634 }; 635 636 U_BOOT_DRIVER(rockchip_usb2phy) = { 637 .name = "rockchip_usb2phy", 638 .id = UCLASS_PHY, 639 .of_match = rockchip_usb2phy_ids, 640 .ops = &rockchip_usb2phy_ops, 641 .probe = rockchip_usb2phy_probe, 642 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 643 }; 644