1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <syscon.h> 12 #include <power/regulator.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 16 #include "../usb/gadget/dwc2_udc_otg_priv.h" 17 18 #define U2PHY_BIT_WRITEABLE_SHIFT 16 19 #define CHG_DCD_MAX_RETRIES 6 20 #define CHG_PRI_MAX_RETRIES 2 21 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 22 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 23 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 24 25 struct rockchip_usb2phy; 26 27 enum power_supply_type { 28 POWER_SUPPLY_TYPE_UNKNOWN = 0, 29 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 30 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 31 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 32 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 33 }; 34 35 enum rockchip_usb2phy_port_id { 36 USB2PHY_PORT_OTG, 37 USB2PHY_PORT_HOST, 38 USB2PHY_NUM_PORTS, 39 }; 40 41 struct usb2phy_reg { 42 u32 offset; 43 u32 bitend; 44 u32 bitstart; 45 u32 disable; 46 u32 enable; 47 }; 48 49 /** 50 * struct rockchip_chg_det_reg: usb charger detect registers 51 * @cp_det: charging port detected successfully. 52 * @dcp_det: dedicated charging port detected successfully. 53 * @dp_det: assert data pin connect successfully. 54 * @idm_sink_en: open dm sink curren. 55 * @idp_sink_en: open dp sink current. 56 * @idp_src_en: open dm source current. 57 * @rdm_pdwn_en: open dm pull down resistor. 58 * @vdm_src_en: open dm voltage source. 59 * @vdp_src_en: open dp voltage source. 60 * @opmode: utmi operational mode. 61 */ 62 struct rockchip_chg_det_reg { 63 struct usb2phy_reg cp_det; 64 struct usb2phy_reg dcp_det; 65 struct usb2phy_reg dp_det; 66 struct usb2phy_reg idm_sink_en; 67 struct usb2phy_reg idp_sink_en; 68 struct usb2phy_reg idp_src_en; 69 struct usb2phy_reg rdm_pdwn_en; 70 struct usb2phy_reg vdm_src_en; 71 struct usb2phy_reg vdp_src_en; 72 struct usb2phy_reg opmode; 73 }; 74 75 /** 76 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 77 * @phy_sus: phy suspend register. 78 * @bvalid_det_en: vbus valid rise detection enable register. 79 * @bvalid_det_st: vbus valid rise detection status register. 80 * @bvalid_det_clr: vbus valid rise detection clear register. 81 * @ls_det_en: linestate detection enable register. 82 * @ls_det_st: linestate detection state register. 83 * @ls_det_clr: linestate detection clear register. 84 * @iddig_output: iddig output from grf. 85 * @iddig_en: utmi iddig select between grf and phy, 86 * 0: from phy; 1: from grf 87 * @idfall_det_en: id fall detection enable register. 88 * @idfall_det_st: id fall detection state register. 89 * @idfall_det_clr: id fall detection clear register. 90 * @idrise_det_en: id rise detection enable register. 91 * @idrise_det_st: id rise detection state register. 92 * @idrise_det_clr: id rise detection clear register. 93 * @utmi_avalid: utmi vbus avalid status register. 94 * @utmi_bvalid: utmi vbus bvalid status register. 95 * @utmi_iddig: otg port id pin status register. 96 * @utmi_ls: utmi linestate state register. 97 * @utmi_hstdet: utmi host disconnect register. 98 * @vbus_det_en: vbus detect function power down register. 99 */ 100 struct rockchip_usb2phy_port_cfg { 101 struct usb2phy_reg phy_sus; 102 struct usb2phy_reg bvalid_det_en; 103 struct usb2phy_reg bvalid_det_st; 104 struct usb2phy_reg bvalid_det_clr; 105 struct usb2phy_reg ls_det_en; 106 struct usb2phy_reg ls_det_st; 107 struct usb2phy_reg ls_det_clr; 108 struct usb2phy_reg iddig_output; 109 struct usb2phy_reg iddig_en; 110 struct usb2phy_reg idfall_det_en; 111 struct usb2phy_reg idfall_det_st; 112 struct usb2phy_reg idfall_det_clr; 113 struct usb2phy_reg idrise_det_en; 114 struct usb2phy_reg idrise_det_st; 115 struct usb2phy_reg idrise_det_clr; 116 struct usb2phy_reg utmi_avalid; 117 struct usb2phy_reg utmi_bvalid; 118 struct usb2phy_reg utmi_iddig; 119 struct usb2phy_reg utmi_ls; 120 struct usb2phy_reg utmi_hstdet; 121 struct usb2phy_reg vbus_det_en; 122 }; 123 124 /** 125 * struct rockchip_usb2phy_cfg: usb-phy configuration. 126 * @reg: the address offset of grf for usb-phy config. 127 * @num_ports: specify how many ports that the phy has. 128 * @phy_tuning: phy default parameters tunning. 129 * @clkout_ctl: keep on/turn off output clk of phy. 130 * @chg_det: charger detection registers. 131 */ 132 struct rockchip_usb2phy_cfg { 133 u32 reg; 134 u32 num_ports; 135 int (*phy_tuning)(struct rockchip_usb2phy *); 136 struct usb2phy_reg clkout_ctl; 137 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 138 const struct rockchip_chg_det_reg chg_det; 139 }; 140 141 /** 142 * @dcd_retries: The retry count used to track Data contact 143 * detection process. 144 * @primary_retries: The retry count used to do usb bc detection 145 * primary stage. 146 * @grf: General Register Files register base. 147 * @usbgrf_base : USB General Register Files register base. 148 * @phy_cfg: phy register configuration, assigned by driver data. 149 */ 150 struct rockchip_usb2phy { 151 u8 dcd_retries; 152 u8 primary_retries; 153 void __iomem *grf_base; 154 void __iomem *usbgrf_base; 155 struct udevice *vbus_supply[USB2PHY_NUM_PORTS]; 156 const struct rockchip_usb2phy_cfg *phy_cfg; 157 }; 158 159 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 160 { 161 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 162 } 163 164 static inline int property_enable(void __iomem *base, 165 const struct usb2phy_reg *reg, bool en) 166 { 167 u32 val, mask, tmp; 168 169 tmp = en ? reg->enable : reg->disable; 170 mask = GENMASK(reg->bitend, reg->bitstart); 171 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 172 173 return writel(val, base + reg->offset); 174 } 175 176 static inline bool property_enabled(void __iomem *base, 177 const struct usb2phy_reg *reg) 178 { 179 u32 tmp, orig; 180 u32 mask = GENMASK(reg->bitend, reg->bitstart); 181 182 orig = readl(base + reg->offset); 183 184 tmp = (orig & mask) >> reg->bitstart; 185 186 return tmp == reg->enable; 187 } 188 189 static const char *chg_to_string(enum power_supply_type chg_type) 190 { 191 switch (chg_type) { 192 case POWER_SUPPLY_TYPE_USB: 193 return "USB_SDP_CHARGER"; 194 case POWER_SUPPLY_TYPE_USB_DCP: 195 return "USB_DCP_CHARGER"; 196 case POWER_SUPPLY_TYPE_USB_CDP: 197 return "USB_CDP_CHARGER"; 198 case POWER_SUPPLY_TYPE_USB_FLOATING: 199 return "USB_FLOATING_CHARGER"; 200 default: 201 return "INVALID_CHARGER"; 202 } 203 } 204 205 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 206 bool en) 207 { 208 void __iomem *base = get_reg_base(rphy); 209 210 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 211 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 212 } 213 214 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 215 bool en) 216 { 217 void __iomem *base = get_reg_base(rphy); 218 219 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 220 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 221 } 222 223 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 224 bool en) 225 { 226 void __iomem *base = get_reg_base(rphy); 227 228 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 229 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 230 } 231 232 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 233 { 234 bool vout = false; 235 236 while (rphy->primary_retries--) { 237 /* voltage source on DP, probe on DM */ 238 rockchip_chg_enable_primary_det(rphy, true); 239 mdelay(CHG_PRIMARY_DET_TIME); 240 vout = property_enabled(rphy->grf_base, 241 &rphy->phy_cfg->chg_det.cp_det); 242 if (vout) 243 break; 244 } 245 246 rockchip_chg_enable_primary_det(rphy, false); 247 return vout; 248 } 249 250 int rockchip_chg_get_type(void) 251 { 252 const struct rockchip_usb2phy_port_cfg *port_cfg; 253 enum power_supply_type chg_type; 254 struct rockchip_usb2phy *rphy; 255 struct udevice *udev; 256 void __iomem *base; 257 bool is_dcd, vout; 258 int ret; 259 260 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 261 if (ret == -ENODEV) { 262 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 263 return ret; 264 } 265 266 rphy = dev_get_priv(udev); 267 base = get_reg_base(rphy); 268 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 269 270 /* Check USB-Vbus status first */ 271 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 272 pr_info("%s: no charger found\n", __func__); 273 return POWER_SUPPLY_TYPE_UNKNOWN; 274 } 275 276 /* Suspend USB-PHY and put the controller in non-driving mode */ 277 property_enable(base, &port_cfg->phy_sus, true); 278 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 279 280 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 281 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 282 283 /* stage 1, start DCD processing stage */ 284 rockchip_chg_enable_dcd(rphy, true); 285 286 while (rphy->dcd_retries--) { 287 mdelay(CHG_DCD_POLL_TIME); 288 289 /* get data contact detection status */ 290 is_dcd = property_enabled(rphy->grf_base, 291 &rphy->phy_cfg->chg_det.dp_det); 292 293 if (is_dcd || !rphy->dcd_retries) { 294 /* 295 * stage 2, turn off DCD circuitry, then 296 * voltage source on DP, probe on DM. 297 */ 298 rockchip_chg_enable_dcd(rphy, false); 299 rockchip_chg_enable_primary_det(rphy, true); 300 break; 301 } 302 } 303 304 mdelay(CHG_PRIMARY_DET_TIME); 305 vout = property_enabled(rphy->grf_base, 306 &rphy->phy_cfg->chg_det.cp_det); 307 rockchip_chg_enable_primary_det(rphy, false); 308 if (vout) { 309 /* stage 3, voltage source on DM, probe on DP */ 310 rockchip_chg_enable_secondary_det(rphy, true); 311 } else { 312 if (!rphy->dcd_retries) { 313 /* floating charger found */ 314 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 315 goto out; 316 } else { 317 /* 318 * Retry some times to make sure that it's 319 * really a USB SDP charger. 320 */ 321 vout = rockchip_chg_primary_det_retry(rphy); 322 if (vout) { 323 /* stage 3, voltage source on DM, probe on DP */ 324 rockchip_chg_enable_secondary_det(rphy, true); 325 } else { 326 /* USB SDP charger found */ 327 chg_type = POWER_SUPPLY_TYPE_USB; 328 goto out; 329 } 330 } 331 } 332 333 mdelay(CHG_SECONDARY_DET_TIME); 334 vout = property_enabled(rphy->grf_base, 335 &rphy->phy_cfg->chg_det.dcp_det); 336 /* stage 4, turn off voltage source */ 337 rockchip_chg_enable_secondary_det(rphy, false); 338 if (vout) 339 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 340 else 341 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 342 343 out: 344 /* Resume USB-PHY and put the controller in normal mode */ 345 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 346 property_enable(base, &port_cfg->phy_sus, false); 347 348 debug("charger is %s\n", chg_to_string(chg_type)); 349 350 return chg_type; 351 } 352 353 int rockchip_u2phy_vbus_detect(void) 354 { 355 int chg_type; 356 357 chg_type = rockchip_chg_get_type(); 358 359 return (chg_type == POWER_SUPPLY_TYPE_USB || 360 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 361 } 362 363 void otg_phy_init(struct dwc2_udc *dev) 364 { 365 const struct rockchip_usb2phy_port_cfg *port_cfg; 366 struct rockchip_usb2phy *rphy; 367 struct udevice *udev; 368 void __iomem *base; 369 int ret; 370 371 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 372 if (ret == -ENODEV) { 373 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 374 return; 375 } 376 377 rphy = dev_get_priv(udev); 378 base = get_reg_base(rphy); 379 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 380 381 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 382 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 383 384 /* Reset USB-PHY */ 385 property_enable(base, &port_cfg->phy_sus, true); 386 udelay(20); 387 property_enable(base, &port_cfg->phy_sus, false); 388 mdelay(2); 389 } 390 391 static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy) 392 { 393 struct udevice *parent = phy->dev->parent; 394 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 395 const struct rockchip_usb2phy_port_cfg *port_cfg; 396 void __iomem *base = get_reg_base(rphy); 397 struct udevice *vbus = NULL; 398 bool iddig = true; 399 400 if (phy->id == USB2PHY_PORT_HOST) { 401 vbus = rphy->vbus_supply[USB2PHY_PORT_HOST]; 402 } else if (phy->id == USB2PHY_PORT_OTG) { 403 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 404 if (port_cfg->utmi_iddig.offset) { 405 iddig = property_enabled(base, &port_cfg->utmi_iddig); 406 if (!iddig) 407 vbus = rphy->vbus_supply[USB2PHY_PORT_OTG]; 408 } 409 } 410 411 return vbus; 412 } 413 414 static int rockchip_usb2phy_init(struct phy *phy) 415 { 416 struct udevice *parent = phy->dev->parent; 417 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 418 const struct rockchip_usb2phy_port_cfg *port_cfg; 419 void __iomem *base = get_reg_base(rphy); 420 421 if (phy->id == USB2PHY_PORT_OTG) { 422 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 423 } else if (phy->id == USB2PHY_PORT_HOST) { 424 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 425 } else { 426 dev_err(phy->dev, "phy id %lu not support", phy->id); 427 return -EINVAL; 428 } 429 430 property_enable(base, &port_cfg->phy_sus, false); 431 432 /* waiting for the utmi_clk to become stable */ 433 udelay(2000); 434 435 return 0; 436 } 437 438 static int rockchip_usb2phy_exit(struct phy *phy) 439 { 440 struct udevice *parent = phy->dev->parent; 441 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 442 const struct rockchip_usb2phy_port_cfg *port_cfg; 443 void __iomem *base = get_reg_base(rphy); 444 445 if (phy->id == USB2PHY_PORT_OTG) { 446 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 447 } else if (phy->id == USB2PHY_PORT_HOST) { 448 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 449 } else { 450 dev_err(phy->dev, "phy id %lu not support", phy->id); 451 return -EINVAL; 452 } 453 454 property_enable(base, &port_cfg->phy_sus, true); 455 456 return 0; 457 } 458 459 static int rockchip_usb2phy_power_on(struct phy *phy) 460 { 461 struct udevice *vbus = NULL; 462 int ret; 463 464 vbus = rockchip_usb2phy_check_vbus(phy); 465 if (vbus) { 466 ret = regulator_set_enable(vbus, true); 467 if (ret) { 468 pr_err("%s: Failed to set VBus supply\n", __func__); 469 return ret; 470 } 471 } 472 473 return 0; 474 } 475 476 static int rockchip_usb2phy_power_off(struct phy *phy) 477 { 478 struct udevice *vbus = NULL; 479 int ret; 480 481 vbus = rockchip_usb2phy_check_vbus(phy); 482 if (vbus) { 483 ret = regulator_set_enable(vbus, false); 484 if (ret) { 485 pr_err("%s: Failed to set VBus supply\n", __func__); 486 return ret; 487 } 488 } 489 490 return 0; 491 } 492 493 static int rockchip_usb2phy_of_xlate(struct phy *phy, 494 struct ofnode_phandle_args *args) 495 { 496 const char *dev_name = phy->dev->name; 497 struct udevice *parent = phy->dev->parent; 498 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 499 500 if (!strcasecmp(dev_name, "host-port")) { 501 phy->id = USB2PHY_PORT_HOST; 502 device_get_supply_regulator(phy->dev, "phy-supply", 503 &rphy->vbus_supply[USB2PHY_PORT_HOST]); 504 } else if (!strcasecmp(dev_name, "otg-port")) { 505 phy->id = USB2PHY_PORT_OTG; 506 device_get_supply_regulator(phy->dev, "phy-supply", 507 &rphy->vbus_supply[USB2PHY_PORT_OTG]); 508 } else { 509 pr_err("%s: invalid dev name\n", __func__); 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static int rockchip_usb2phy_bind(struct udevice *dev) 517 { 518 struct udevice *child; 519 ofnode subnode; 520 const char *node_name; 521 int ret; 522 523 dev_for_each_subnode(subnode, dev) { 524 if (!ofnode_valid(subnode)) { 525 debug("%s: %s subnode not found", __func__, dev->name); 526 return -ENXIO; 527 } 528 529 node_name = ofnode_get_name(subnode); 530 debug("%s: subnode %s\n", __func__, node_name); 531 532 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 533 node_name, subnode, &child); 534 if (ret) { 535 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 536 __func__, node_name); 537 return ret; 538 } 539 } 540 541 return 0; 542 } 543 544 static int rockchip_usb2phy_probe(struct udevice *dev) 545 { 546 const struct rockchip_usb2phy_cfg *phy_cfgs; 547 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 548 struct udevice *parent = dev->parent; 549 u32 reg, index; 550 551 if (!strncmp(parent->name, "root_driver", 11) && 552 dev_read_bool(dev, "rockchip,grf")) 553 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 554 else 555 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 556 557 if (rphy->grf_base <= 0) { 558 dev_err(dev, "get syscon grf failed\n"); 559 return -EINVAL; 560 } 561 562 if (dev_read_bool(dev, "rockchip,usbgrf")) { 563 rphy->usbgrf_base = 564 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 565 if (rphy->usbgrf_base <= 0) { 566 dev_err(dev, "get syscon usbgrf failed\n"); 567 return -EINVAL; 568 } 569 } else { 570 rphy->usbgrf_base = NULL; 571 } 572 573 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 574 dev_err(dev, "could not read reg\n"); 575 return -EINVAL; 576 } 577 578 phy_cfgs = 579 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 580 if (!phy_cfgs) { 581 dev_err(dev, "unable to get phy_cfgs\n"); 582 return -EINVAL; 583 } 584 585 /* find out a proper config which can be matched with dt. */ 586 index = 0; 587 while (phy_cfgs[index].reg) { 588 if (phy_cfgs[index].reg == reg) { 589 rphy->phy_cfg = &phy_cfgs[index]; 590 break; 591 } 592 ++index; 593 } 594 595 if (!rphy->phy_cfg) { 596 dev_err(dev, "no phy-config can be matched\n"); 597 return -EINVAL; 598 } 599 600 if (rphy->phy_cfg->phy_tuning) 601 rphy->phy_cfg->phy_tuning(rphy); 602 603 return 0; 604 } 605 606 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 607 { 608 void __iomem *base = get_reg_base(rphy); 609 int ret = 0; 610 611 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 612 if (rphy->phy_cfg->reg == 0x760) 613 ret = writel(0x00070004, base + 0x76c); 614 615 return ret; 616 } 617 618 static struct phy_ops rockchip_usb2phy_ops = { 619 .init = rockchip_usb2phy_init, 620 .exit = rockchip_usb2phy_exit, 621 .power_on = rockchip_usb2phy_power_on, 622 .power_off = rockchip_usb2phy_power_off, 623 .of_xlate = rockchip_usb2phy_of_xlate, 624 }; 625 626 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 627 { 628 .reg = 0x100, 629 .num_ports = 2, 630 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 631 .port_cfgs = { 632 [USB2PHY_PORT_OTG] = { 633 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 634 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 635 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 636 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 637 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 638 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 639 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 640 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 641 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 642 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 643 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 644 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 645 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 646 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 647 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 648 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 649 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 650 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 651 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 652 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 653 }, 654 [USB2PHY_PORT_HOST] = { 655 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 656 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 657 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 658 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 659 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 660 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 661 } 662 }, 663 .chg_det = { 664 .opmode = { 0x0100, 3, 0, 5, 1 }, 665 .cp_det = { 0x0120, 24, 24, 0, 1 }, 666 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 667 .dp_det = { 0x0120, 25, 25, 0, 1 }, 668 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 669 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 670 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 671 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 672 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 673 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 674 }, 675 }, 676 { /* sentinel */ } 677 }; 678 679 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 680 { 681 .reg = 0x17c, 682 .num_ports = 2, 683 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 684 .port_cfgs = { 685 [USB2PHY_PORT_OTG] = { 686 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 687 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 688 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 689 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 690 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 691 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 692 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 693 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 694 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 695 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 696 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 697 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 698 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 699 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 700 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 701 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 702 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 703 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 704 }, 705 [USB2PHY_PORT_HOST] = { 706 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 707 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 708 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 709 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 710 } 711 }, 712 .chg_det = { 713 .opmode = { 0x017c, 3, 0, 5, 1 }, 714 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 715 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 716 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 717 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 718 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 719 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 720 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 721 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 722 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 723 }, 724 }, 725 { /* sentinel */ } 726 }; 727 728 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 729 { 730 .reg = 0x760, 731 .num_ports = 2, 732 .phy_tuning = rk322x_usb2phy_tuning, 733 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 734 .port_cfgs = { 735 [USB2PHY_PORT_OTG] = { 736 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 737 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 738 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 739 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 740 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 741 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 742 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 743 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 744 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 745 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 746 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 747 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 748 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 749 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 750 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 751 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 752 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 753 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 754 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 755 }, 756 [USB2PHY_PORT_HOST] = { 757 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 758 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 759 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 760 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 761 } 762 }, 763 .chg_det = { 764 .opmode = { 0x0760, 3, 0, 5, 1 }, 765 .cp_det = { 0x0884, 4, 4, 0, 1 }, 766 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 767 .dp_det = { 0x0884, 5, 5, 0, 1 }, 768 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 769 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 770 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 771 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 772 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 773 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 774 }, 775 }, 776 { 777 .reg = 0x800, 778 .num_ports = 2, 779 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 780 .port_cfgs = { 781 [USB2PHY_PORT_OTG] = { 782 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 783 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 784 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 785 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 786 }, 787 [USB2PHY_PORT_HOST] = { 788 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 789 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 790 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 791 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 792 } 793 }, 794 }, 795 { /* sentinel */ } 796 }; 797 798 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 799 { 800 .reg = 0x100, 801 .num_ports = 2, 802 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 803 .port_cfgs = { 804 [USB2PHY_PORT_OTG] = { 805 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 806 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 807 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 808 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 809 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 810 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 811 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 812 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 813 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 814 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 815 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 816 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 817 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 818 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 819 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 820 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 821 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 822 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 823 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 824 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 825 }, 826 [USB2PHY_PORT_HOST] = { 827 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 828 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 829 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 830 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 831 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 832 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 833 } 834 }, 835 .chg_det = { 836 .opmode = { 0x0100, 3, 0, 5, 1 }, 837 .cp_det = { 0x0120, 24, 24, 0, 1 }, 838 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 839 .dp_det = { 0x0120, 25, 25, 0, 1 }, 840 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 841 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 842 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 843 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 844 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 845 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 846 }, 847 }, 848 { /* sentinel */ } 849 }; 850 851 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 852 { 853 .reg = 0x700, 854 .num_ports = 2, 855 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 856 .port_cfgs = { 857 [USB2PHY_PORT_OTG] = { 858 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 859 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 860 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 861 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 862 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 863 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 864 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 865 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 866 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 867 }, 868 [USB2PHY_PORT_HOST] = { 869 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 870 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 871 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 872 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 873 } 874 }, 875 .chg_det = { 876 .opmode = { 0x0700, 3, 0, 5, 1 }, 877 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 878 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 879 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 880 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 881 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 882 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 883 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 884 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 885 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 886 }, 887 }, 888 { /* sentinel */ } 889 }; 890 891 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 892 { 893 .reg = 0xe450, 894 .num_ports = 2, 895 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 896 .port_cfgs = { 897 [USB2PHY_PORT_OTG] = { 898 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 899 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 900 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 901 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 902 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 903 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 904 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 905 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 906 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 907 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 908 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 909 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 910 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 911 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 912 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 913 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 914 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 915 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 916 }, 917 [USB2PHY_PORT_HOST] = { 918 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 919 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 920 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 921 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 922 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 923 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 924 } 925 }, 926 .chg_det = { 927 .opmode = { 0xe454, 3, 0, 5, 1 }, 928 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 929 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 930 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 931 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 932 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 933 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 934 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 935 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 936 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 937 }, 938 }, 939 { 940 .reg = 0xe460, 941 .num_ports = 2, 942 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 943 .port_cfgs = { 944 [USB2PHY_PORT_OTG] = { 945 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 946 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 947 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 948 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 949 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 950 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 951 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 952 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 953 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 954 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 955 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 956 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 957 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 958 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 959 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 960 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 961 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 962 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 963 }, 964 [USB2PHY_PORT_HOST] = { 965 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 966 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 967 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 968 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 969 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 970 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 971 } 972 }, 973 .chg_det = { 974 .opmode = { 0xe464, 3, 0, 5, 1 }, 975 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 976 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 977 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 978 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 979 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 980 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 981 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 982 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 983 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 984 }, 985 }, 986 { /* sentinel */ } 987 }; 988 989 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 990 { 991 .reg = 0x100, 992 .num_ports = 2, 993 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 994 .port_cfgs = { 995 [USB2PHY_PORT_OTG] = { 996 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 997 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 998 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 999 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1000 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1001 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1002 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1003 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1004 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1005 }, 1006 [USB2PHY_PORT_HOST] = { 1007 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 1008 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1009 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1010 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1011 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1012 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1013 } 1014 }, 1015 .chg_det = { 1016 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 1017 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1018 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1019 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1020 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 1021 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 1022 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 1023 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 1024 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 1025 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 1026 }, 1027 }, 1028 { /* sentinel */ } 1029 }; 1030 1031 static const struct udevice_id rockchip_usb2phy_ids[] = { 1032 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 1033 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 1034 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 1035 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1036 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 1037 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 1038 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 1039 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 1040 { } 1041 }; 1042 1043 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 1044 .name = "rockchip_usb2phy_port", 1045 .id = UCLASS_PHY, 1046 .ops = &rockchip_usb2phy_ops, 1047 }; 1048 1049 U_BOOT_DRIVER(rockchip_usb2phy) = { 1050 .name = "rockchip_usb2phy", 1051 .id = UCLASS_PHY, 1052 .of_match = rockchip_usb2phy_ids, 1053 .probe = rockchip_usb2phy_probe, 1054 .bind = rockchip_usb2phy_bind, 1055 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 1056 }; 1057