1 /* 2 * Copyright (C) 2015-2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "comphy.h" 14 #include "comphy_hpipe.h" 15 #include "sata.h" 16 #include "utmi_phy.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) 21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) 22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) 23 24 struct utmi_phy_data { 25 void __iomem *utmi_base_addr; 26 void __iomem *usb_cfg_addr; 27 void __iomem *utmi_cfg_addr; 28 u32 utmi_phy_port; 29 }; 30 31 /* 32 * For CP-110 we have 2 Selector registers "PHY Selectors", 33 * and "PIPE Selectors". 34 * PIPE selector include USB and PCIe options. 35 * PHY selector include the Ethernet and SATA options, every Ethernet 36 * option has different options, for example: serdes lane2 had option 37 * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) 38 */ 39 struct comphy_mux_data cp110_comphy_phy_mux_data[] = { 40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ 41 {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */ 43 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, 44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ 45 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, 46 {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, 47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ 48 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, 49 {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, 50 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 51 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ 52 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2}, 53 {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, 54 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ 55 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, 56 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, 57 }; 58 59 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { 60 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ 61 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ 62 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, 63 {PHY_TYPE_PEX0, 0x4} } }, 64 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ 65 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 66 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ 67 {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 68 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ 69 {PHY_TYPE_USB3_HOST1, 0x1}, 70 {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, 71 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ 72 }; 73 74 static u32 polling_with_timeout(void __iomem *addr, u32 val, 75 u32 mask, unsigned long usec_timout) 76 { 77 u32 data; 78 79 do { 80 udelay(1); 81 data = readl(addr) & mask; 82 } while (data != val && --usec_timout > 0); 83 84 if (usec_timout == 0) 85 return data; 86 87 return 0; 88 } 89 90 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, 91 bool is_end_point, void __iomem *hpipe_base, 92 void __iomem *comphy_base) 93 { 94 u32 mask, data, ret = 1; 95 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 96 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 97 void __iomem *addr; 98 u32 pcie_clk = 0; /* set input by default */ 99 100 debug_enter(); 101 102 /* 103 * ToDo: 104 * Add SAR (Sample-At-Reset) configuration for the PCIe clock 105 * direction. SAR code is currently not ported from Marvell 106 * U-Boot to mainline version. 107 * 108 * SerDes Lane 4/5 got the PCIe ref-clock #1, 109 * and SerDes Lane 0 got PCIe ref-clock #0 110 */ 111 debug("PCIe clock = %x\n", pcie_clk); 112 debug("PCIe RC = %d\n", !is_end_point); 113 debug("PCIe width = %d\n", pcie_width); 114 115 /* enable PCIe by4 and by2 */ 116 if (lane == 0) { 117 if (pcie_width == 4) { 118 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 119 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, 120 COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); 121 } else if (pcie_width == 2) { 122 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 123 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, 124 COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); 125 } 126 } 127 128 /* 129 * If PCIe clock is output and clock source from SerDes lane 5, 130 * we need to configure the clock-source MUX. 131 * By default, the clock source is from lane 4 132 */ 133 if (pcie_clk && clk_src && (lane == 5)) { 134 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, 135 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, 136 DFX_DEV_GEN_PCIE_CLK_SRC_MASK); 137 } 138 139 debug("stage: RFU configurations - hard reset comphy\n"); 140 /* RFU configurations - hard reset comphy */ 141 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 142 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 143 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 144 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 145 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 146 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 147 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 148 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 149 mask |= COMMON_PHY_PHY_MODE_MASK; 150 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; 151 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 152 153 /* release from hard reset */ 154 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 155 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 156 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 157 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 158 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 159 160 /* Wait 1ms - until band gap and ref clock ready */ 161 mdelay(1); 162 /* Start comphy Configuration */ 163 debug("stage: Comphy configuration\n"); 164 /* Set PIPE soft reset */ 165 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 166 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 167 /* Set PHY datapath width mode for V0 */ 168 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 169 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 170 /* Set Data bus width USB mode for V0 */ 171 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 172 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 173 /* Set CORE_CLK output frequency for 250Mhz */ 174 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 175 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 176 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 177 /* Set PLL ready delay for 0x2 */ 178 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; 179 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; 180 if (pcie_width != 1) { 181 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; 182 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; 183 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; 184 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; 185 } 186 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); 187 188 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ 189 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; 190 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; 191 if (pcie_width != 1) { 192 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; 193 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; 194 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; 195 if (lane == 0) { 196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; 197 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; 198 } else if (lane == (pcie_width - 1)) { 199 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; 200 } 201 } 202 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); 203 /* Config update polarity equalization */ 204 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, 205 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, 206 HPIPE_CFG_UPDATE_POLARITY_MASK); 207 /* Set PIPE version 4 to mode enable */ 208 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, 209 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, 210 HPIPE_DFE_CTRL_28_PIPE4_MASK); 211 /* TODO: check if pcie clock is output/input - for bringup use input*/ 212 /* Enable PIN clock 100M_125M */ 213 mask = 0; 214 data = 0; 215 /* Only if clock is output, configure the clock-source mux */ 216 if (pcie_clk) { 217 mask |= HPIPE_MISC_CLK100M_125M_MASK; 218 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; 219 } 220 /* 221 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz 222 * clock 223 */ 224 mask |= HPIPE_MISC_TXDCLK_2X_MASK; 225 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; 226 /* Enable 500MHz Clock */ 227 mask |= HPIPE_MISC_CLK500_EN_MASK; 228 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; 229 if (pcie_clk) { /* output */ 230 /* Set reference clock comes from group 1 */ 231 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 232 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 233 } else { 234 /* Set reference clock comes from group 2 */ 235 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 236 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; 237 } 238 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 239 if (pcie_clk) { /* output */ 240 /* Set reference frequcency select - 0x2 for 25MHz*/ 241 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 242 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 243 } else { 244 /* Set reference frequcency select - 0x0 for 100MHz*/ 245 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 246 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 247 } 248 /* Set PHY mode to PCIe */ 249 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 250 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 251 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 252 253 /* ref clock alignment */ 254 if (pcie_width != 1) { 255 mask = HPIPE_LANE_ALIGN_OFF_MASK; 256 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; 257 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); 258 } 259 260 /* 261 * Set the amount of time spent in the LoZ state - set for 0x7 only if 262 * the PCIe clock is output 263 */ 264 if (pcie_clk) { 265 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 266 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 267 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 268 } 269 270 /* Set Maximal PHY Generation Setting(8Gbps) */ 271 mask = HPIPE_INTERFACE_GEN_MAX_MASK; 272 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; 273 /* Set Link Train Mode (Tx training control pins are used) */ 274 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; 275 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; 276 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); 277 278 /* Set Idle_sync enable */ 279 mask = HPIPE_PCIE_IDLE_SYNC_MASK; 280 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; 281 /* Select bits for PCIE Gen3(32bit) */ 282 mask |= HPIPE_PCIE_SEL_BITS_MASK; 283 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; 284 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); 285 286 /* Enable Tx_adapt_g1 */ 287 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; 288 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; 289 /* Enable Tx_adapt_gn1 */ 290 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; 291 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; 292 /* Disable Tx_adapt_g0 */ 293 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; 294 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 295 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 296 297 /* Set reg_tx_train_chk_init */ 298 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; 299 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; 300 /* Enable TX_COE_FM_PIN_PCIE3_EN */ 301 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; 302 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; 303 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); 304 305 debug("stage: TRx training parameters\n"); 306 /* Set Preset sweep configurations */ 307 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; 308 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; 309 310 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; 311 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; 312 313 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; 314 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; 315 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); 316 317 /* Tx train start configuration */ 318 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; 319 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; 320 321 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; 322 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; 323 324 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; 325 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; 326 327 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; 328 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; 329 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); 330 331 /* Enable Tx train P2P */ 332 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; 333 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; 334 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); 335 336 /* Configure Tx train timeout */ 337 mask = HPIPE_TRX_TRAIN_TIMER_MASK; 338 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; 339 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); 340 341 /* Disable G0/G1/GN1 adaptation */ 342 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK 343 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 344 data = 0; 345 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 346 347 /* Disable DTL frequency loop */ 348 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 349 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 350 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 351 352 /* Configure G3 DFE */ 353 mask = HPIPE_G3_DFE_RES_MASK; 354 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; 355 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 356 357 /* Force DFE resolution (use GEN table value) */ 358 mask = HPIPE_DFE_RES_FORCE_MASK; 359 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 360 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 361 362 /* Configure initial and final coefficient value for receiver */ 363 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 364 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 365 366 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 367 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 368 369 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 370 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 371 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 372 373 /* Trigger sampler enable pulse */ 374 mask = HPIPE_SMAPLER_MASK; 375 data = 0x1 << HPIPE_SMAPLER_OFFSET; 376 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 377 udelay(5); 378 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); 379 380 /* FFE resistor tuning for different bandwidth */ 381 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 382 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 383 384 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 385 data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 386 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 387 388 if (!is_end_point) { 389 /* Set phy in root complex mode */ 390 mask = HPIPE_CFG_PHY_RC_EP_MASK; 391 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; 392 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); 393 } 394 395 debug("stage: Comphy power up\n"); 396 397 /* 398 * For PCIe by4 or by2 - release from reset only after finish to 399 * configure all lanes 400 */ 401 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { 402 u32 i, start_lane, end_lane; 403 404 if (pcie_width != 1) { 405 /* allows writing to all lanes in one write */ 406 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 407 0x0 << 408 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 409 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 410 start_lane = 0; 411 end_lane = pcie_width; 412 413 /* 414 * Release from PIPE soft reset 415 * for PCIe by4 or by2 - release from soft reset 416 * all lanes - can't use read modify write 417 */ 418 reg_set(HPIPE_ADDR(hpipe_base, 0) + 419 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); 420 } else { 421 start_lane = lane; 422 end_lane = lane + 1; 423 424 /* 425 * Release from PIPE soft reset 426 * for PCIe by4 or by2 - release from soft reset 427 * all lanes 428 */ 429 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 430 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 431 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 432 } 433 434 435 if (pcie_width != 1) { 436 /* disable writing to all lanes with one write */ 437 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 438 0x3210 << 439 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 440 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 441 } 442 443 debug("stage: Check PLL\n"); 444 /* Read lane status */ 445 for (i = start_lane; i < end_lane; i++) { 446 addr = HPIPE_ADDR(hpipe_base, i) + 447 HPIPE_LANE_STATUS1_REG; 448 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 449 mask = data; 450 data = polling_with_timeout(addr, data, mask, 15000); 451 if (data != 0) { 452 debug("Read from reg = %p - value = 0x%x\n", 453 hpipe_addr + HPIPE_LANE_STATUS1_REG, 454 data); 455 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 456 ret = 0; 457 } 458 } 459 } 460 461 debug_exit(); 462 return ret; 463 } 464 465 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, 466 void __iomem *comphy_base) 467 { 468 u32 mask, data, ret = 1; 469 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 470 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 471 void __iomem *addr; 472 473 debug_enter(); 474 debug("stage: RFU configurations - hard reset comphy\n"); 475 /* RFU configurations - hard reset comphy */ 476 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 477 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 478 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 479 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 480 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 481 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 482 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 483 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 484 mask |= COMMON_PHY_PHY_MODE_MASK; 485 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; 486 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 487 488 /* release from hard reset */ 489 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 490 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 491 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 492 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 493 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 494 495 /* Wait 1ms - until band gap and ref clock ready */ 496 mdelay(1); 497 498 /* Start comphy Configuration */ 499 debug("stage: Comphy configuration\n"); 500 /* Set PIPE soft reset */ 501 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 502 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 503 /* Set PHY datapath width mode for V0 */ 504 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 505 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 506 /* Set Data bus width USB mode for V0 */ 507 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 508 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 509 /* Set CORE_CLK output frequency for 250Mhz */ 510 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 511 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 512 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 513 /* Set PLL ready delay for 0x2 */ 514 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, 515 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, 516 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); 517 /* Set reference clock to come from group 1 - 25Mhz */ 518 reg_set(hpipe_addr + HPIPE_MISC_REG, 519 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 520 HPIPE_MISC_REFCLK_SEL_MASK); 521 /* Set reference frequcency select - 0x2 */ 522 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 523 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 524 /* Set PHY mode to USB - 0x5 */ 525 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 526 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 527 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 528 /* Set the amount of time spent in the LoZ state - set for 0x7 */ 529 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 530 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 531 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 532 /* Set max PHY generation setting - 5Gbps */ 533 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 534 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 535 HPIPE_INTERFACE_GEN_MAX_MASK); 536 /* Set select data width 20Bit (SEL_BITS[2:0]) */ 537 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 538 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, 539 HPIPE_LOOPBACK_SEL_MASK); 540 /* select de-emphasize 3.5db */ 541 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, 542 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, 543 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); 544 /* override tx margining from the MAC */ 545 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, 546 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, 547 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); 548 549 /* Start analog paramters from ETP(HW) */ 550 debug("stage: Analog paramters from ETP(HW)\n"); 551 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ 552 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; 553 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; 554 /* Set Override PHY DFE control pins for 0x1 */ 555 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; 556 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; 557 /* Set Spread Spectrum Clock Enable fot 0x1 */ 558 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; 559 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; 560 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); 561 /* End of analog parameters */ 562 563 debug("stage: Comphy power up\n"); 564 /* Release from PIPE soft reset */ 565 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 566 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 567 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 568 569 /* wait 15ms - for comphy calibration done */ 570 debug("stage: Check PLL\n"); 571 /* Read lane status */ 572 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; 573 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 574 mask = data; 575 data = polling_with_timeout(addr, data, mask, 15000); 576 if (data != 0) { 577 debug("Read from reg = %p - value = 0x%x\n", 578 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 579 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 580 ret = 0; 581 } 582 583 debug_exit(); 584 return ret; 585 } 586 587 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, 588 void __iomem *comphy_base, int comphy_index) 589 { 590 u32 mask, data, i, ret = 1; 591 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 592 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 593 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 594 void __iomem *addr; 595 void __iomem *sata_base = NULL; 596 int sata_node = -1; /* Set to -1 in order to read the first sata node */ 597 598 debug_enter(); 599 600 /* 601 * Assumption - each CP has only one SATA controller 602 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 603 * will return the first node always. 604 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible 605 * must be called again (according to the CP id) 606 */ 607 for (i = 0; i < (comphy_index + 1); i++) 608 sata_node = fdt_node_offset_by_compatible( 609 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); 610 611 if (sata_node == 0) { 612 error("SATA node not found in FDT\n"); 613 return 0; 614 } 615 616 sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( 617 gd->fdt_blob, sata_node, "reg", 0, NULL, true); 618 if (sata_base == NULL) { 619 error("SATA address not found in FDT\n"); 620 return 0; 621 } 622 623 debug("SATA address found in FDT %p\n", sata_base); 624 625 debug("stage: MAC configuration - power down comphy\n"); 626 /* 627 * MAC configuration powe down comphy use indirect address for 628 * vendor spesific SATA control register 629 */ 630 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 631 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 632 SATA3_VENDOR_ADDR_MASK); 633 /* SATA 0 power down */ 634 mask = SATA3_CTRL_SATA0_PD_MASK; 635 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; 636 /* SATA 1 power down */ 637 mask |= SATA3_CTRL_SATA1_PD_MASK; 638 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; 639 /* SATA SSU disable */ 640 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 641 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 642 /* SATA port 1 disable */ 643 mask |= SATA3_CTRL_SATA_SSU_MASK; 644 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; 645 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 646 647 debug("stage: RFU configurations - hard reset comphy\n"); 648 /* RFU configurations - hard reset comphy */ 649 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 650 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 651 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 652 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 653 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 654 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 655 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 656 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 657 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 658 659 /* Set select data width 40Bit - SATA mode only */ 660 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, 661 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, 662 COMMON_PHY_CFG6_IF_40_SEL_MASK); 663 664 /* release from hard reset in SD external */ 665 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 666 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 667 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 668 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 669 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 670 671 /* Wait 1ms - until band gap and ref clock ready */ 672 mdelay(1); 673 674 debug("stage: Comphy configuration\n"); 675 /* Start comphy Configuration */ 676 /* Set reference clock to comes from group 1 - choose 25Mhz */ 677 reg_set(hpipe_addr + HPIPE_MISC_REG, 678 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 679 HPIPE_MISC_REFCLK_SEL_MASK); 680 /* Reference frequency select set 1 (for SATA = 25Mhz) */ 681 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 682 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 683 /* PHY mode select (set SATA = 0x0 */ 684 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 685 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 686 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 687 /* Set max PHY generation setting - 6Gbps */ 688 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 689 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 690 HPIPE_INTERFACE_GEN_MAX_MASK); 691 /* Set select data width 40Bit (SEL_BITS[2:0]) */ 692 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 693 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 694 695 debug("stage: Analog paramters from ETP(HW)\n"); 696 /* Set analog parameters from ETP(HW) */ 697 /* G1 settings */ 698 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 699 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 700 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 701 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 702 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; 703 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; 704 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; 705 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; 706 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; 707 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; 708 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 709 710 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; 711 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; 712 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; 713 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; 714 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; 715 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; 716 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; 717 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; 718 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; 719 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; 720 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 721 722 /* G2 settings */ 723 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; 724 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; 725 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; 726 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; 727 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; 728 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; 729 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; 730 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; 731 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; 732 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; 733 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); 734 735 /* G3 settings */ 736 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 737 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 738 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 739 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 740 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; 741 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; 742 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; 743 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; 744 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; 745 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; 746 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; 747 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; 748 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 749 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 750 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 751 752 /* DTL Control */ 753 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; 754 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; 755 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; 756 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; 757 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 758 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 759 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; 760 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; 761 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; 762 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; 763 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; 764 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; 765 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; 766 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; 767 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 768 769 /* Trigger sampler enable pulse (by toggleing the bit) */ 770 mask = HPIPE_SMAPLER_MASK; 771 data = 0x1 << HPIPE_SMAPLER_OFFSET; 772 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 773 mask = HPIPE_SMAPLER_MASK; 774 data = 0x0 << HPIPE_SMAPLER_OFFSET; 775 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 776 777 /* VDD Calibration Control 3 */ 778 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; 779 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; 780 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); 781 782 /* DFE Resolution Control */ 783 mask = HPIPE_DFE_RES_FORCE_MASK; 784 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 785 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 786 787 /* DFE F3-F5 Coefficient Control */ 788 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 789 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 790 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 791 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 792 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 793 794 /* G3 Setting 3 */ 795 mask = HPIPE_G3_FFE_CAP_SEL_MASK; 796 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; 797 mask |= HPIPE_G3_FFE_RES_SEL_MASK; 798 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; 799 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; 800 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; 801 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 802 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 803 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 804 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 805 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 806 807 /* G3 Setting 4 */ 808 mask = HPIPE_G3_DFE_RES_MASK; 809 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; 810 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 811 812 /* Offset Phase Control */ 813 mask = HPIPE_OS_PH_OFFSET_MASK; 814 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; 815 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; 816 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; 817 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 818 mask = HPIPE_OS_PH_VALID_MASK; 819 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; 820 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 821 mask = HPIPE_OS_PH_VALID_MASK; 822 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; 823 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 824 825 /* Set G1 TX amplitude and TX post emphasis value */ 826 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 827 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 828 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; 829 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; 830 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 831 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 832 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; 833 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; 834 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 835 836 /* Set G2 TX amplitude and TX post emphasis value */ 837 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; 838 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; 839 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; 840 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; 841 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; 842 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; 843 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; 844 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; 845 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); 846 847 /* Set G3 TX amplitude and TX post emphasis value */ 848 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; 849 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; 850 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; 851 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; 852 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; 853 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; 854 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; 855 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; 856 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; 857 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; 858 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; 859 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; 860 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); 861 862 /* SERDES External Configuration 2 register */ 863 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; 864 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; 865 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 866 867 /* DFE reset sequence */ 868 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 869 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 870 HPIPE_PWR_CTR_RST_DFE_MASK); 871 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 872 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 873 HPIPE_PWR_CTR_RST_DFE_MASK); 874 /* SW reset for interupt logic */ 875 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 876 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 877 HPIPE_PWR_CTR_SFT_RST_MASK); 878 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 879 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 880 HPIPE_PWR_CTR_SFT_RST_MASK); 881 882 debug("stage: Comphy power up\n"); 883 /* 884 * MAC configuration power up comphy - power up PLL/TX/RX 885 * use indirect address for vendor spesific SATA control register 886 */ 887 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 888 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 889 SATA3_VENDOR_ADDR_MASK); 890 /* SATA 0 power up */ 891 mask = SATA3_CTRL_SATA0_PD_MASK; 892 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; 893 /* SATA 1 power up */ 894 mask |= SATA3_CTRL_SATA1_PD_MASK; 895 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; 896 /* SATA SSU enable */ 897 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 898 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 899 /* SATA port 1 enable */ 900 mask |= SATA3_CTRL_SATA_SSU_MASK; 901 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; 902 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 903 904 /* MBUS request size and interface select register */ 905 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 906 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, 907 SATA3_VENDOR_ADDR_MASK); 908 /* Mbus regret enable */ 909 reg_set(sata_base + SATA3_VENDOR_DATA, 910 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); 911 912 debug("stage: Check PLL\n"); 913 914 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 915 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & 916 SD_EXTERNAL_STATUS0_PLL_RX_MASK; 917 mask = data; 918 data = polling_with_timeout(addr, data, mask, 15000); 919 if (data != 0) { 920 debug("Read from reg = %p - value = 0x%x\n", 921 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 922 error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", 923 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), 924 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); 925 ret = 0; 926 } 927 928 debug_exit(); 929 return ret; 930 } 931 932 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, 933 void __iomem *hpipe_base, 934 void __iomem *comphy_base) 935 { 936 u32 mask, data, ret = 1; 937 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 938 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 939 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 940 void __iomem *addr; 941 942 debug_enter(); 943 debug("stage: RFU configurations - hard reset comphy\n"); 944 /* RFU configurations - hard reset comphy */ 945 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 946 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 947 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 948 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 949 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 950 951 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 952 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 953 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 954 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 955 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 956 if (sgmii_speed == PHY_SPEED_1_25G) { 957 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 958 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 959 } else { 960 /* 3.125G */ 961 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 962 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 963 } 964 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 965 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 966 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 967 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 968 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 969 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 970 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 971 972 /* release from hard reset */ 973 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 974 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 975 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 976 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 977 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 978 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 979 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 980 981 /* release from hard reset */ 982 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 983 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 984 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 985 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 986 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 987 988 989 /* Wait 1ms - until band gap and ref clock ready */ 990 mdelay(1); 991 992 /* Start comphy Configuration */ 993 debug("stage: Comphy configuration\n"); 994 /* set reference clock */ 995 mask = HPIPE_MISC_REFCLK_SEL_MASK; 996 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 997 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 998 /* Power and PLL Control */ 999 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1000 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1001 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1002 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1003 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1004 /* Loopback register */ 1005 mask = HPIPE_LOOPBACK_SEL_MASK; 1006 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1007 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1008 /* rx control 1 */ 1009 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1010 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1011 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1012 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1013 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1014 /* DTL Control */ 1015 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1016 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1017 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1018 1019 /* Set analog paramters from ETP(HW) - for now use the default datas */ 1020 debug("stage: Analog paramters from ETP(HW)\n"); 1021 1022 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1023 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1024 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1025 1026 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1027 /* SERDES External Configuration */ 1028 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1029 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1030 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1031 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1032 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1033 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1034 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1035 1036 /* check PLL rx & tx ready */ 1037 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1038 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1039 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1040 mask = data; 1041 data = polling_with_timeout(addr, data, mask, 15000); 1042 if (data != 0) { 1043 debug("Read from reg = %p - value = 0x%x\n", 1044 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1045 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1046 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1047 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1048 ret = 0; 1049 } 1050 1051 /* RX init */ 1052 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1053 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1054 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1055 1056 /* check that RX init done */ 1057 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1058 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1059 mask = data; 1060 data = polling_with_timeout(addr, data, mask, 100); 1061 if (data != 0) { 1062 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1063 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1064 ret = 0; 1065 } 1066 1067 debug("stage: RF Reset\n"); 1068 /* RF Reset */ 1069 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1070 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1071 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1072 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1073 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1074 1075 debug_exit(); 1076 return ret; 1077 } 1078 1079 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, 1080 void __iomem *comphy_base) 1081 { 1082 u32 mask, data, ret = 1; 1083 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1084 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1085 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1086 void __iomem *addr; 1087 1088 debug_enter(); 1089 debug("stage: RFU configurations - hard reset comphy\n"); 1090 /* RFU configurations - hard reset comphy */ 1091 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1092 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1093 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1094 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1095 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1096 1097 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1098 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1099 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1100 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1101 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1102 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1103 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1104 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1105 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1106 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1107 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1108 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1109 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1110 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1111 1112 /* release from hard reset */ 1113 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1114 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1115 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1116 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1117 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1118 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1119 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1120 1121 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1122 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1123 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1124 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1125 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1126 1127 1128 /* Wait 1ms - until band gap and ref clock ready */ 1129 mdelay(1); 1130 1131 /* Start comphy Configuration */ 1132 debug("stage: Comphy configuration\n"); 1133 /* set reference clock */ 1134 mask = HPIPE_MISC_ICP_FORCE_MASK; 1135 data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; 1136 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 1137 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 1138 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 1139 /* Power and PLL Control */ 1140 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1141 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1142 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1143 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1144 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1145 /* Loopback register */ 1146 mask = HPIPE_LOOPBACK_SEL_MASK; 1147 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1148 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1149 /* rx control 1 */ 1150 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1151 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1152 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1153 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1154 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1155 /* DTL Control */ 1156 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1157 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1158 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1159 1160 /* Set analog paramters from ETP(HW) */ 1161 debug("stage: Analog paramters from ETP(HW)\n"); 1162 /* SERDES External Configuration 2 */ 1163 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; 1164 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; 1165 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 1166 /* 0x7-DFE Resolution control */ 1167 mask = HPIPE_DFE_RES_FORCE_MASK; 1168 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 1169 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 1170 /* 0xd-G1_Setting_0 */ 1171 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 1172 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 1173 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1174 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1175 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 1176 /* Genration 1 setting 2 (G1_Setting_2) */ 1177 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; 1178 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; 1179 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; 1180 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; 1181 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); 1182 /* Transmitter Slew Rate Control register (tx_reg1) */ 1183 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; 1184 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; 1185 mask |= HPIPE_TX_REG1_SLC_EN_MASK; 1186 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; 1187 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); 1188 /* Impedance Calibration Control register (cal_reg1) */ 1189 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; 1190 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1191 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; 1192 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; 1193 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); 1194 /* Generation 1 Setting 5 (g1_setting_5) */ 1195 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; 1196 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1197 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); 1198 /* 0xE-G1_Setting_1 */ 1199 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1200 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1201 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1202 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1203 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1204 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1205 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1206 /* 0xA-DFE_Reg3 */ 1207 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1208 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1209 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1210 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1211 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1212 1213 /* 0x111-G1_Setting_4 */ 1214 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1215 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1216 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1217 /* Genration 1 setting 3 (G1_Setting_3) */ 1218 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; 1219 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; 1220 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 1221 1222 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1223 /* SERDES External Configuration */ 1224 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1225 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1226 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1227 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1228 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1229 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1230 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1231 1232 1233 /* check PLL rx & tx ready */ 1234 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1235 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1236 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1237 mask = data; 1238 data = polling_with_timeout(addr, data, mask, 15000); 1239 if (data != 0) { 1240 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1241 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1242 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1243 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1244 ret = 0; 1245 } 1246 1247 /* RX init */ 1248 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1249 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1250 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1251 1252 1253 /* check that RX init done */ 1254 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1255 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1256 mask = data; 1257 data = polling_with_timeout(addr, data, mask, 100); 1258 if (data != 0) { 1259 debug("Read from reg = %p - value = 0x%x\n", 1260 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1261 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1262 ret = 0; 1263 } 1264 1265 debug("stage: RF Reset\n"); 1266 /* RF Reset */ 1267 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1268 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1269 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1270 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1271 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1272 1273 debug_exit(); 1274 return ret; 1275 } 1276 1277 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, 1278 void __iomem *comphy_base) 1279 { 1280 u32 mask, data, ret = 1; 1281 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1282 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1283 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1284 void __iomem *addr; 1285 1286 debug_enter(); 1287 debug("stage: RFU configurations - hard reset comphy\n"); 1288 /* RFU configurations - hard reset comphy */ 1289 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1290 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1291 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1292 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1293 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1294 1295 if (lane == 2) { 1296 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1297 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, 1298 COMMON_PHY_SD_CTRL1_RXAUI0_MASK); 1299 } 1300 if (lane == 4) { 1301 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1302 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, 1303 COMMON_PHY_SD_CTRL1_RXAUI1_MASK); 1304 } 1305 1306 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1307 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1308 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1309 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1310 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1311 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1312 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1313 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1314 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1315 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1316 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1317 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1318 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1319 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; 1320 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; 1321 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1322 1323 /* release from hard reset */ 1324 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1325 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1326 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1327 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1328 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1329 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1330 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1331 1332 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1333 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1334 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1335 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1336 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1337 1338 /* Wait 1ms - until band gap and ref clock ready */ 1339 mdelay(1); 1340 1341 /* Start comphy Configuration */ 1342 debug("stage: Comphy configuration\n"); 1343 /* set reference clock */ 1344 reg_set(hpipe_addr + HPIPE_MISC_REG, 1345 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 1346 HPIPE_MISC_REFCLK_SEL_MASK); 1347 /* Power and PLL Control */ 1348 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1349 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1350 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1351 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1352 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1353 /* Loopback register */ 1354 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 1355 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 1356 /* rx control 1 */ 1357 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1358 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1359 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1360 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1361 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1362 /* DTL Control */ 1363 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, 1364 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, 1365 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); 1366 1367 /* Set analog paramters from ETP(HW) */ 1368 debug("stage: Analog paramters from ETP(HW)\n"); 1369 /* SERDES External Configuration 2 */ 1370 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 1371 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, 1372 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); 1373 /* 0x7-DFE Resolution control */ 1374 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, 1375 HPIPE_DFE_RES_FORCE_MASK); 1376 /* 0xd-G1_Setting_0 */ 1377 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1378 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1379 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1380 /* 0xE-G1_Setting_1 */ 1381 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1382 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1383 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1384 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1385 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1386 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1387 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1388 /* 0xA-DFE_Reg3 */ 1389 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1390 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1391 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1392 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1393 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1394 1395 /* 0x111-G1_Setting_4 */ 1396 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1397 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1398 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1399 1400 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1401 /* SERDES External Configuration */ 1402 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1403 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1404 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1405 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1406 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1407 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1408 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1409 1410 1411 /* check PLL rx & tx ready */ 1412 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1413 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1414 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1415 mask = data; 1416 data = polling_with_timeout(addr, data, mask, 15000); 1417 if (data != 0) { 1418 debug("Read from reg = %p - value = 0x%x\n", 1419 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1420 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1421 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1422 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1423 ret = 0; 1424 } 1425 1426 /* RX init */ 1427 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, 1428 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, 1429 SD_EXTERNAL_CONFIG1_RX_INIT_MASK); 1430 1431 /* check that RX init done */ 1432 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1433 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1434 mask = data; 1435 data = polling_with_timeout(addr, data, mask, 100); 1436 if (data != 0) { 1437 debug("Read from reg = %p - value = 0x%x\n", 1438 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1439 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1440 ret = 0; 1441 } 1442 1443 debug("stage: RF Reset\n"); 1444 /* RF Reset */ 1445 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1446 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1447 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1448 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1449 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1450 1451 debug_exit(); 1452 return ret; 1453 } 1454 1455 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, 1456 void __iomem *usb_cfg_addr, 1457 void __iomem *utmi_cfg_addr, 1458 u32 utmi_phy_port) 1459 { 1460 u32 mask, data; 1461 1462 debug_enter(); 1463 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", 1464 utmi_index); 1465 /* Power down UTMI PHY */ 1466 reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, 1467 UTMI_PHY_CFG_PU_MASK); 1468 1469 /* 1470 * If UTMI connected to USB Device, configure mux prior to PHY init 1471 * (Device can be connected to UTMI0 or to UTMI1) 1472 */ 1473 if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { 1474 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", 1475 utmi_index); 1476 /* USB3 Device UTMI enable */ 1477 mask = UTMI_USB_CFG_DEVICE_EN_MASK; 1478 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; 1479 /* USB3 Device UTMI MUX */ 1480 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; 1481 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; 1482 reg_set(usb_cfg_addr, data, mask); 1483 } 1484 1485 /* Set Test suspendm mode */ 1486 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; 1487 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; 1488 /* Enable Test UTMI select */ 1489 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; 1490 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; 1491 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); 1492 1493 /* Wait for UTMI power down */ 1494 mdelay(1); 1495 1496 debug_exit(); 1497 return; 1498 } 1499 1500 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, 1501 void __iomem *usb_cfg_addr, 1502 void __iomem *utmi_cfg_addr, 1503 u32 utmi_phy_port) 1504 { 1505 u32 mask, data; 1506 1507 debug_exit(); 1508 debug("stage: Configure UTMI PHY %d registers\n", utmi_index); 1509 /* Reference Clock Divider Select */ 1510 mask = UTMI_PLL_CTRL_REFDIV_MASK; 1511 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; 1512 /* Feedback Clock Divider Select - 90 for 25Mhz*/ 1513 mask |= UTMI_PLL_CTRL_FBDIV_MASK; 1514 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; 1515 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ 1516 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; 1517 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; 1518 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); 1519 1520 /* Impedance Calibration Threshold Setting */ 1521 reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, 1522 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, 1523 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); 1524 1525 /* Set LS TX driver strength coarse control */ 1526 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; 1527 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; 1528 /* Set LS TX driver fine adjustment */ 1529 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; 1530 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; 1531 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); 1532 1533 /* Enable SQ */ 1534 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; 1535 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; 1536 /* Enable analog squelch detect */ 1537 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; 1538 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; 1539 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); 1540 1541 /* Set External squelch calibration number */ 1542 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; 1543 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; 1544 /* Enable the External squelch calibration */ 1545 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; 1546 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; 1547 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); 1548 1549 /* Set Control VDAT Reference Voltage - 0.325V */ 1550 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; 1551 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; 1552 /* Set Control VSRC Reference Voltage - 0.6V */ 1553 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; 1554 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; 1555 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); 1556 1557 debug_exit(); 1558 return; 1559 } 1560 1561 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, 1562 void __iomem *usb_cfg_addr, 1563 void __iomem *utmi_cfg_addr, u32 utmi_phy_port) 1564 { 1565 u32 data, mask, ret = 1; 1566 void __iomem *addr; 1567 1568 debug_enter(); 1569 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", 1570 utmi_index); 1571 /* Power UP UTMI PHY */ 1572 reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, 1573 UTMI_PHY_CFG_PU_MASK); 1574 /* Disable Test UTMI select */ 1575 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, 1576 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, 1577 UTMI_CTRL_STATUS0_TEST_SEL_MASK); 1578 1579 debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); 1580 addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; 1581 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; 1582 mask = data; 1583 data = polling_with_timeout(addr, data, mask, 100); 1584 if (data != 0) { 1585 error("Impedance calibration is not done\n"); 1586 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1587 ret = 0; 1588 } 1589 1590 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; 1591 mask = data; 1592 data = polling_with_timeout(addr, data, mask, 100); 1593 if (data != 0) { 1594 error("PLL calibration is not done\n"); 1595 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1596 ret = 0; 1597 } 1598 1599 addr = utmi_base_addr + UTMI_PLL_CTRL_REG; 1600 data = UTMI_PLL_CTRL_PLL_RDY_MASK; 1601 mask = data; 1602 data = polling_with_timeout(addr, data, mask, 100); 1603 if (data != 0) { 1604 error("PLL is not ready\n"); 1605 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1606 ret = 0; 1607 } 1608 1609 if (ret) 1610 debug("Passed\n"); 1611 else 1612 debug("\n"); 1613 1614 debug_exit(); 1615 return ret; 1616 } 1617 1618 /* 1619 * comphy_utmi_phy_init initialize the UTMI PHY 1620 * the init split in 3 parts: 1621 * 1. Power down transceiver and PLL 1622 * 2. UTMI PHY configure 1623 * 3. Powe up transceiver and PLL 1624 * Note: - Power down/up should be once for both UTMI PHYs 1625 * - comphy_dedicated_phys_init call this function if at least there is 1626 * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is 1627 * legal 1628 */ 1629 static void comphy_utmi_phy_init(u32 utmi_phy_count, 1630 struct utmi_phy_data *cp110_utmi_data) 1631 { 1632 u32 i; 1633 1634 debug_enter(); 1635 /* UTMI Power down */ 1636 for (i = 0; i < utmi_phy_count; i++) { 1637 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, 1638 cp110_utmi_data[i].usb_cfg_addr, 1639 cp110_utmi_data[i].utmi_cfg_addr, 1640 cp110_utmi_data[i].utmi_phy_port); 1641 } 1642 /* PLL Power down */ 1643 debug("stage: UTMI PHY power down PLL\n"); 1644 for (i = 0; i < utmi_phy_count; i++) { 1645 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1646 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1647 } 1648 /* UTMI configure */ 1649 for (i = 0; i < utmi_phy_count; i++) { 1650 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, 1651 cp110_utmi_data[i].usb_cfg_addr, 1652 cp110_utmi_data[i].utmi_cfg_addr, 1653 cp110_utmi_data[i].utmi_phy_port); 1654 } 1655 /* UTMI Power up */ 1656 for (i = 0; i < utmi_phy_count; i++) { 1657 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, 1658 cp110_utmi_data[i].usb_cfg_addr, 1659 cp110_utmi_data[i].utmi_cfg_addr, 1660 cp110_utmi_data[i].utmi_phy_port)) { 1661 error("Failed to initialize UTMI PHY %d\n", i); 1662 continue; 1663 } 1664 printf("UTMI PHY %d initialized to ", i); 1665 if (cp110_utmi_data[i].utmi_phy_port == 1666 UTMI_PHY_TO_USB3_DEVICE0) 1667 printf("USB Device\n"); 1668 else 1669 printf("USB Host%d\n", 1670 cp110_utmi_data[i].utmi_phy_port); 1671 } 1672 /* PLL Power up */ 1673 debug("stage: UTMI PHY power up PLL\n"); 1674 for (i = 0; i < utmi_phy_count; i++) { 1675 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1676 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1677 } 1678 1679 debug_exit(); 1680 return; 1681 } 1682 1683 /* 1684 * comphy_dedicated_phys_init initialize the dedicated PHYs 1685 * - not muxed SerDes lanes e.g. UTMI PHY 1686 */ 1687 void comphy_dedicated_phys_init(void) 1688 { 1689 struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; 1690 int node; 1691 int i; 1692 1693 debug_enter(); 1694 debug("Initialize USB UTMI PHYs\n"); 1695 1696 /* Find the UTMI phy node in device tree and go over them */ 1697 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1698 "marvell,mvebu-utmi-2.6.0"); 1699 1700 i = 0; 1701 while (node > 0) { 1702 /* get base address of UTMI phy */ 1703 cp110_utmi_data[i].utmi_base_addr = 1704 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1705 gd->fdt_blob, node, "reg", 0, NULL, true); 1706 if (cp110_utmi_data[i].utmi_base_addr == NULL) { 1707 error("UTMI PHY base address is invalid\n"); 1708 i++; 1709 continue; 1710 } 1711 1712 /* get usb config address */ 1713 cp110_utmi_data[i].usb_cfg_addr = 1714 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1715 gd->fdt_blob, node, "reg", 1, NULL, true); 1716 if (cp110_utmi_data[i].usb_cfg_addr == NULL) { 1717 error("UTMI PHY base address is invalid\n"); 1718 i++; 1719 continue; 1720 } 1721 1722 /* get UTMI config address */ 1723 cp110_utmi_data[i].utmi_cfg_addr = 1724 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1725 gd->fdt_blob, node, "reg", 2, NULL, true); 1726 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { 1727 error("UTMI PHY base address is invalid\n"); 1728 i++; 1729 continue; 1730 } 1731 1732 /* 1733 * get the port number (to check if the utmi connected to 1734 * host/device) 1735 */ 1736 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( 1737 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); 1738 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { 1739 error("UTMI PHY port type is invalid\n"); 1740 i++; 1741 continue; 1742 } 1743 1744 node = fdt_node_offset_by_compatible( 1745 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); 1746 i++; 1747 } 1748 1749 if (i > 0) 1750 comphy_utmi_phy_init(i, cp110_utmi_data); 1751 1752 debug_exit(); 1753 } 1754 1755 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1756 struct comphy_map *serdes_map) 1757 { 1758 void __iomem *comphy_base_addr; 1759 struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; 1760 struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; 1761 u32 lane, comphy_max_count; 1762 1763 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1764 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1765 1766 /* 1767 * Copy the SerDes map configuration for PIPE map and PHY map 1768 * the comphy_mux_init modify the type of the lane if the type 1769 * is not valid because we have 2 selectores run the 1770 * comphy_mux_init twice and after that update the original 1771 * serdes_map 1772 */ 1773 for (lane = 0; lane < comphy_max_count; lane++) { 1774 comphy_map_pipe_data[lane].type = serdes_map[lane].type; 1775 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; 1776 comphy_map_phy_data[lane].type = serdes_map[lane].type; 1777 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; 1778 } 1779 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; 1780 comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, 1781 comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); 1782 1783 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; 1784 comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, 1785 comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); 1786 /* Fix the type after check the PHY and PIPE configuration */ 1787 for (lane = 0; lane < comphy_max_count; lane++) { 1788 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && 1789 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) 1790 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; 1791 } 1792 } 1793 1794 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1795 struct comphy_map *serdes_map) 1796 { 1797 struct comphy_map *ptr_comphy_map; 1798 void __iomem *comphy_base_addr, *hpipe_base_addr; 1799 u32 comphy_max_count, lane, ret = 0; 1800 u32 pcie_width = 0; 1801 1802 debug_enter(); 1803 1804 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1805 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1806 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; 1807 1808 /* Config Comphy mux configuration */ 1809 comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); 1810 1811 /* Check if the first 4 lanes configured as By-4 */ 1812 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; 1813 lane++, ptr_comphy_map++) { 1814 if (ptr_comphy_map->type != PHY_TYPE_PEX0) 1815 break; 1816 pcie_width++; 1817 } 1818 1819 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; 1820 lane++, ptr_comphy_map++) { 1821 debug("Initialize serdes number %d\n", lane); 1822 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); 1823 if (lane == 4) { 1824 /* 1825 * PCIe lanes above the first 4 lanes, can be only 1826 * by1 1827 */ 1828 pcie_width = 1; 1829 } 1830 switch (ptr_comphy_map->type) { 1831 case PHY_TYPE_UNCONNECTED: 1832 case PHY_TYPE_IGNORE: 1833 continue; 1834 break; 1835 case PHY_TYPE_PEX0: 1836 case PHY_TYPE_PEX1: 1837 case PHY_TYPE_PEX2: 1838 case PHY_TYPE_PEX3: 1839 ret = comphy_pcie_power_up( 1840 lane, pcie_width, ptr_comphy_map->clk_src, 1841 serdes_map->end_point, 1842 hpipe_base_addr, comphy_base_addr); 1843 break; 1844 case PHY_TYPE_SATA0: 1845 case PHY_TYPE_SATA1: 1846 case PHY_TYPE_SATA2: 1847 case PHY_TYPE_SATA3: 1848 ret = comphy_sata_power_up( 1849 lane, hpipe_base_addr, comphy_base_addr, 1850 ptr_chip_cfg->comphy_index); 1851 break; 1852 case PHY_TYPE_USB3_HOST0: 1853 case PHY_TYPE_USB3_HOST1: 1854 case PHY_TYPE_USB3_DEVICE: 1855 ret = comphy_usb3_power_up(lane, hpipe_base_addr, 1856 comphy_base_addr); 1857 break; 1858 case PHY_TYPE_SGMII0: 1859 case PHY_TYPE_SGMII1: 1860 case PHY_TYPE_SGMII2: 1861 case PHY_TYPE_SGMII3: 1862 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { 1863 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", 1864 lane); 1865 ptr_comphy_map->speed = PHY_SPEED_1_25G; 1866 } 1867 ret = comphy_sgmii_power_up( 1868 lane, ptr_comphy_map->speed, hpipe_base_addr, 1869 comphy_base_addr); 1870 break; 1871 case PHY_TYPE_SFI: 1872 ret = comphy_sfi_power_up(lane, hpipe_base_addr, 1873 comphy_base_addr); 1874 break; 1875 case PHY_TYPE_RXAUI0: 1876 case PHY_TYPE_RXAUI1: 1877 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, 1878 comphy_base_addr); 1879 break; 1880 default: 1881 debug("Unknown SerDes type, skip initialize SerDes %d\n", 1882 lane); 1883 break; 1884 } 1885 if (ret == 0) { 1886 /* 1887 * If interface wans't initialized, set the lane to 1888 * PHY_TYPE_UNCONNECTED state. 1889 */ 1890 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; 1891 error("PLL is not locked - Failed to initialize lane %d\n", 1892 lane); 1893 } 1894 } 1895 1896 debug_exit(); 1897 return 0; 1898 } 1899