1 /* 2 * Copyright (C) 2015-2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "comphy.h" 14 #include "comphy_hpipe.h" 15 #include "sata.h" 16 #include "utmi_phy.h" 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define SD_ADDR(base, lane) (base + 0x1000 * lane) 21 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) 22 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) 23 24 struct utmi_phy_data { 25 void __iomem *utmi_base_addr; 26 void __iomem *usb_cfg_addr; 27 void __iomem *utmi_cfg_addr; 28 u32 utmi_phy_port; 29 }; 30 31 /* 32 * For CP-110 we have 2 Selector registers "PHY Selectors", 33 * and "PIPE Selectors". 34 * PIPE selector include USB and PCIe options. 35 * PHY selector include the Ethernet and SATA options, every Ethernet 36 * option has different options, for example: serdes lane2 had option 37 * Eth_port_0 that include (SGMII0, RXAUI0, SFI) 38 */ 39 struct comphy_mux_data cp110_comphy_phy_mux_data[] = { 40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ 41 {PHY_TYPE_SATA1, 0x4} } }, 42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ 43 {PHY_TYPE_SATA0, 0x4} } }, 44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ 45 {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, 46 {PHY_TYPE_SATA0, 0x4} } }, 47 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ 48 {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, 49 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ 50 {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, 51 {PHY_TYPE_SGMII1, 0x1} } }, 52 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ 53 {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, 54 }; 55 56 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { 57 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ 58 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ 59 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, 60 {PHY_TYPE_PEX0, 0x4} } }, 61 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ 62 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 63 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ 64 {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, 65 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ 66 {PHY_TYPE_USB3_HOST1, 0x1}, 67 {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, 68 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ 69 }; 70 71 static u32 polling_with_timeout(void __iomem *addr, u32 val, 72 u32 mask, unsigned long usec_timout) 73 { 74 u32 data; 75 76 do { 77 udelay(1); 78 data = readl(addr) & mask; 79 } while (data != val && --usec_timout > 0); 80 81 if (usec_timout == 0) 82 return data; 83 84 return 0; 85 } 86 87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, 88 bool is_end_point, void __iomem *hpipe_base, 89 void __iomem *comphy_base) 90 { 91 u32 mask, data, ret = 1; 92 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 93 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 94 void __iomem *addr; 95 u32 pcie_clk = 0; /* set input by default */ 96 97 debug_enter(); 98 99 /* 100 * ToDo: 101 * Add SAR (Sample-At-Reset) configuration for the PCIe clock 102 * direction. SAR code is currently not ported from Marvell 103 * U-Boot to mainline version. 104 * 105 * SerDes Lane 4/5 got the PCIe ref-clock #1, 106 * and SerDes Lane 0 got PCIe ref-clock #0 107 */ 108 debug("PCIe clock = %x\n", pcie_clk); 109 debug("PCIe RC = %d\n", !is_end_point); 110 debug("PCIe width = %d\n", pcie_width); 111 112 /* enable PCIe by4 and by2 */ 113 if (lane == 0) { 114 if (pcie_width == 4) { 115 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 116 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, 117 COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); 118 } else if (pcie_width == 2) { 119 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 120 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, 121 COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); 122 } 123 } 124 125 /* 126 * If PCIe clock is output and clock source from SerDes lane 5, 127 * we need to configure the clock-source MUX. 128 * By default, the clock source is from lane 4 129 */ 130 if (pcie_clk && clk_src && (lane == 5)) { 131 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, 132 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, 133 DFX_DEV_GEN_PCIE_CLK_SRC_MASK); 134 } 135 136 debug("stage: RFU configurations - hard reset comphy\n"); 137 /* RFU configurations - hard reset comphy */ 138 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 139 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 140 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 141 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 142 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 143 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 144 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 145 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 146 mask |= COMMON_PHY_PHY_MODE_MASK; 147 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; 148 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 149 150 /* release from hard reset */ 151 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 152 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 153 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 154 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 155 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 156 157 /* Wait 1ms - until band gap and ref clock ready */ 158 mdelay(1); 159 /* Start comphy Configuration */ 160 debug("stage: Comphy configuration\n"); 161 /* Set PIPE soft reset */ 162 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 163 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 164 /* Set PHY datapath width mode for V0 */ 165 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 166 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 167 /* Set Data bus width USB mode for V0 */ 168 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 169 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 170 /* Set CORE_CLK output frequency for 250Mhz */ 171 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 172 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 173 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 174 /* Set PLL ready delay for 0x2 */ 175 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; 176 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; 177 if (pcie_width != 1) { 178 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; 179 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; 180 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; 181 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; 182 } 183 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); 184 185 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ 186 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; 187 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; 188 if (pcie_width != 1) { 189 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; 190 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; 191 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; 192 if (lane == 0) { 193 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; 194 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; 195 } else if (lane == (pcie_width - 1)) { 196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; 197 } 198 } 199 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); 200 /* Config update polarity equalization */ 201 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, 202 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, 203 HPIPE_CFG_UPDATE_POLARITY_MASK); 204 /* Set PIPE version 4 to mode enable */ 205 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, 206 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, 207 HPIPE_DFE_CTRL_28_PIPE4_MASK); 208 /* TODO: check if pcie clock is output/input - for bringup use input*/ 209 /* Enable PIN clock 100M_125M */ 210 mask = 0; 211 data = 0; 212 /* Only if clock is output, configure the clock-source mux */ 213 if (pcie_clk) { 214 mask |= HPIPE_MISC_CLK100M_125M_MASK; 215 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; 216 } 217 /* 218 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz 219 * clock 220 */ 221 mask |= HPIPE_MISC_TXDCLK_2X_MASK; 222 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; 223 /* Enable 500MHz Clock */ 224 mask |= HPIPE_MISC_CLK500_EN_MASK; 225 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; 226 if (pcie_clk) { /* output */ 227 /* Set reference clock comes from group 1 */ 228 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 229 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 230 } else { 231 /* Set reference clock comes from group 2 */ 232 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 233 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; 234 } 235 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 236 if (pcie_clk) { /* output */ 237 /* Set reference frequcency select - 0x2 for 25MHz*/ 238 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 239 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 240 } else { 241 /* Set reference frequcency select - 0x0 for 100MHz*/ 242 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 243 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 244 } 245 /* Set PHY mode to PCIe */ 246 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 247 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 248 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 249 250 /* ref clock alignment */ 251 if (pcie_width != 1) { 252 mask = HPIPE_LANE_ALIGN_OFF_MASK; 253 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; 254 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); 255 } 256 257 /* 258 * Set the amount of time spent in the LoZ state - set for 0x7 only if 259 * the PCIe clock is output 260 */ 261 if (pcie_clk) { 262 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 263 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 264 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 265 } 266 267 /* Set Maximal PHY Generation Setting(8Gbps) */ 268 mask = HPIPE_INTERFACE_GEN_MAX_MASK; 269 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; 270 /* Set Link Train Mode (Tx training control pins are used) */ 271 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; 272 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; 273 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); 274 275 /* Set Idle_sync enable */ 276 mask = HPIPE_PCIE_IDLE_SYNC_MASK; 277 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; 278 /* Select bits for PCIE Gen3(32bit) */ 279 mask |= HPIPE_PCIE_SEL_BITS_MASK; 280 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; 281 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); 282 283 /* Enable Tx_adapt_g1 */ 284 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; 285 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; 286 /* Enable Tx_adapt_gn1 */ 287 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; 288 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; 289 /* Disable Tx_adapt_g0 */ 290 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; 291 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 292 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 293 294 /* Set reg_tx_train_chk_init */ 295 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; 296 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; 297 /* Enable TX_COE_FM_PIN_PCIE3_EN */ 298 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; 299 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; 300 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); 301 302 debug("stage: TRx training parameters\n"); 303 /* Set Preset sweep configurations */ 304 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; 305 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; 306 307 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; 308 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; 309 310 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; 311 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; 312 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); 313 314 /* Tx train start configuration */ 315 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; 316 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; 317 318 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; 319 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; 320 321 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; 322 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; 323 324 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; 325 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; 326 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); 327 328 /* Enable Tx train P2P */ 329 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; 330 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; 331 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); 332 333 /* Configure Tx train timeout */ 334 mask = HPIPE_TRX_TRAIN_TIMER_MASK; 335 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; 336 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); 337 338 /* Disable G0/G1/GN1 adaptation */ 339 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK 340 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; 341 data = 0; 342 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); 343 344 /* Disable DTL frequency loop */ 345 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 346 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 347 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 348 349 /* Configure G3 DFE */ 350 mask = HPIPE_G3_DFE_RES_MASK; 351 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; 352 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 353 354 /* Force DFE resolution (use GEN table value) */ 355 mask = HPIPE_DFE_RES_FORCE_MASK; 356 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 357 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 358 359 /* Configure initial and final coefficient value for receiver */ 360 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 361 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 362 363 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 364 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 365 366 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 367 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 368 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 369 370 /* Trigger sampler enable pulse */ 371 mask = HPIPE_SMAPLER_MASK; 372 data = 0x1 << HPIPE_SMAPLER_OFFSET; 373 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 374 udelay(5); 375 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); 376 377 /* FFE resistor tuning for different bandwidth */ 378 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 379 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 380 381 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 382 data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 383 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 384 385 if (!is_end_point) { 386 /* Set phy in root complex mode */ 387 mask = HPIPE_CFG_PHY_RC_EP_MASK; 388 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; 389 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); 390 } 391 392 debug("stage: Comphy power up\n"); 393 394 /* 395 * For PCIe by4 or by2 - release from reset only after finish to 396 * configure all lanes 397 */ 398 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { 399 u32 i, start_lane, end_lane; 400 401 if (pcie_width != 1) { 402 /* allows writing to all lanes in one write */ 403 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 404 0x0 << 405 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 406 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 407 start_lane = 0; 408 end_lane = pcie_width; 409 410 /* 411 * Release from PIPE soft reset 412 * for PCIe by4 or by2 - release from soft reset 413 * all lanes - can't use read modify write 414 */ 415 reg_set(HPIPE_ADDR(hpipe_base, 0) + 416 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); 417 } else { 418 start_lane = lane; 419 end_lane = lane + 1; 420 421 /* 422 * Release from PIPE soft reset 423 * for PCIe by4 or by2 - release from soft reset 424 * all lanes 425 */ 426 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 427 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 428 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 429 } 430 431 432 if (pcie_width != 1) { 433 /* disable writing to all lanes with one write */ 434 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 435 0x3210 << 436 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, 437 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); 438 } 439 440 debug("stage: Check PLL\n"); 441 /* Read lane status */ 442 for (i = start_lane; i < end_lane; i++) { 443 addr = HPIPE_ADDR(hpipe_base, i) + 444 HPIPE_LANE_STATUS1_REG; 445 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 446 mask = data; 447 data = polling_with_timeout(addr, data, mask, 15000); 448 if (data != 0) { 449 debug("Read from reg = %p - value = 0x%x\n", 450 hpipe_addr + HPIPE_LANE_STATUS1_REG, 451 data); 452 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 453 ret = 0; 454 } 455 } 456 } 457 458 debug_exit(); 459 return ret; 460 } 461 462 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, 463 void __iomem *comphy_base) 464 { 465 u32 mask, data, ret = 1; 466 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 467 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 468 void __iomem *addr; 469 470 debug_enter(); 471 debug("stage: RFU configurations - hard reset comphy\n"); 472 /* RFU configurations - hard reset comphy */ 473 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 474 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 475 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 476 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 477 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 478 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 479 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 480 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 481 mask |= COMMON_PHY_PHY_MODE_MASK; 482 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; 483 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 484 485 /* release from hard reset */ 486 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 487 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 488 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 489 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 490 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 491 492 /* Wait 1ms - until band gap and ref clock ready */ 493 mdelay(1); 494 495 /* Start comphy Configuration */ 496 debug("stage: Comphy configuration\n"); 497 /* Set PIPE soft reset */ 498 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; 499 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; 500 /* Set PHY datapath width mode for V0 */ 501 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; 502 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; 503 /* Set Data bus width USB mode for V0 */ 504 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; 505 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; 506 /* Set CORE_CLK output frequency for 250Mhz */ 507 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; 508 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; 509 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); 510 /* Set PLL ready delay for 0x2 */ 511 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, 512 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, 513 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); 514 /* Set reference clock to come from group 1 - 25Mhz */ 515 reg_set(hpipe_addr + HPIPE_MISC_REG, 516 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 517 HPIPE_MISC_REFCLK_SEL_MASK); 518 /* Set reference frequcency select - 0x2 */ 519 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 520 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 521 /* Set PHY mode to USB - 0x5 */ 522 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 523 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 524 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 525 /* Set the amount of time spent in the LoZ state - set for 0x7 */ 526 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, 527 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, 528 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); 529 /* Set max PHY generation setting - 5Gbps */ 530 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 531 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 532 HPIPE_INTERFACE_GEN_MAX_MASK); 533 /* Set select data width 20Bit (SEL_BITS[2:0]) */ 534 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 535 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, 536 HPIPE_LOOPBACK_SEL_MASK); 537 /* select de-emphasize 3.5db */ 538 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, 539 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, 540 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); 541 /* override tx margining from the MAC */ 542 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, 543 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, 544 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); 545 546 /* Start analog paramters from ETP(HW) */ 547 debug("stage: Analog paramters from ETP(HW)\n"); 548 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ 549 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; 550 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; 551 /* Set Override PHY DFE control pins for 0x1 */ 552 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; 553 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; 554 /* Set Spread Spectrum Clock Enable fot 0x1 */ 555 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; 556 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; 557 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); 558 /* End of analog parameters */ 559 560 debug("stage: Comphy power up\n"); 561 /* Release from PIPE soft reset */ 562 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, 563 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, 564 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); 565 566 /* wait 15ms - for comphy calibration done */ 567 debug("stage: Check PLL\n"); 568 /* Read lane status */ 569 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; 570 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; 571 mask = data; 572 data = polling_with_timeout(addr, data, mask, 15000); 573 if (data != 0) { 574 debug("Read from reg = %p - value = 0x%x\n", 575 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 576 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); 577 ret = 0; 578 } 579 580 debug_exit(); 581 return ret; 582 } 583 584 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, 585 void __iomem *comphy_base, int comphy_index) 586 { 587 u32 mask, data, i, ret = 1; 588 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 589 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 590 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 591 void __iomem *addr; 592 void __iomem *sata_base = NULL; 593 int sata_node = -1; /* Set to -1 in order to read the first sata node */ 594 595 debug_enter(); 596 597 /* 598 * Assumption - each CP has only one SATA controller 599 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 600 * will return the first node always. 601 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible 602 * must be called again (according to the CP id) 603 */ 604 for (i = 0; i < (comphy_index + 1); i++) 605 sata_node = fdt_node_offset_by_compatible( 606 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); 607 608 if (sata_node == 0) { 609 error("SATA node not found in FDT\n"); 610 return 0; 611 } 612 613 sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( 614 gd->fdt_blob, sata_node, "reg", 0, NULL, true); 615 if (sata_base == NULL) { 616 error("SATA address not found in FDT\n"); 617 return 0; 618 } 619 620 debug("SATA address found in FDT %p\n", sata_base); 621 622 debug("stage: MAC configuration - power down comphy\n"); 623 /* 624 * MAC configuration powe down comphy use indirect address for 625 * vendor spesific SATA control register 626 */ 627 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 628 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 629 SATA3_VENDOR_ADDR_MASK); 630 /* SATA 0 power down */ 631 mask = SATA3_CTRL_SATA0_PD_MASK; 632 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; 633 /* SATA 1 power down */ 634 mask |= SATA3_CTRL_SATA1_PD_MASK; 635 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; 636 /* SATA SSU disable */ 637 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 638 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 639 /* SATA port 1 disable */ 640 mask |= SATA3_CTRL_SATA_SSU_MASK; 641 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; 642 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 643 644 debug("stage: RFU configurations - hard reset comphy\n"); 645 /* RFU configurations - hard reset comphy */ 646 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 647 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 648 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 649 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 650 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; 651 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; 652 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; 653 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; 654 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 655 656 /* Set select data width 40Bit - SATA mode only */ 657 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, 658 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, 659 COMMON_PHY_CFG6_IF_40_SEL_MASK); 660 661 /* release from hard reset in SD external */ 662 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 663 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 664 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 665 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 666 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 667 668 /* Wait 1ms - until band gap and ref clock ready */ 669 mdelay(1); 670 671 debug("stage: Comphy configuration\n"); 672 /* Start comphy Configuration */ 673 /* Set reference clock to comes from group 1 - choose 25Mhz */ 674 reg_set(hpipe_addr + HPIPE_MISC_REG, 675 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 676 HPIPE_MISC_REFCLK_SEL_MASK); 677 /* Reference frequency select set 1 (for SATA = 25Mhz) */ 678 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 679 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 680 /* PHY mode select (set SATA = 0x0 */ 681 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 682 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 683 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 684 /* Set max PHY generation setting - 6Gbps */ 685 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, 686 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, 687 HPIPE_INTERFACE_GEN_MAX_MASK); 688 /* Set select data width 40Bit (SEL_BITS[2:0]) */ 689 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 690 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 691 692 debug("stage: Analog paramters from ETP(HW)\n"); 693 /* Set analog parameters from ETP(HW) */ 694 /* G1 settings */ 695 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 696 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 697 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 698 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 699 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; 700 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; 701 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; 702 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; 703 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; 704 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; 705 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 706 707 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; 708 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; 709 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; 710 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; 711 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; 712 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; 713 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; 714 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; 715 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; 716 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; 717 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 718 719 /* G2 settings */ 720 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; 721 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; 722 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; 723 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; 724 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; 725 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; 726 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; 727 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; 728 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; 729 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; 730 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); 731 732 /* G3 settings */ 733 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; 734 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; 735 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; 736 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; 737 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; 738 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; 739 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; 740 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; 741 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; 742 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; 743 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; 744 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; 745 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; 746 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; 747 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); 748 749 /* DTL Control */ 750 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; 751 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; 752 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; 753 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; 754 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 755 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 756 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; 757 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; 758 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; 759 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; 760 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; 761 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; 762 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; 763 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; 764 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 765 766 /* Trigger sampler enable pulse (by toggleing the bit) */ 767 mask = HPIPE_SMAPLER_MASK; 768 data = 0x1 << HPIPE_SMAPLER_OFFSET; 769 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 770 mask = HPIPE_SMAPLER_MASK; 771 data = 0x0 << HPIPE_SMAPLER_OFFSET; 772 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 773 774 /* VDD Calibration Control 3 */ 775 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; 776 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; 777 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); 778 779 /* DFE Resolution Control */ 780 mask = HPIPE_DFE_RES_FORCE_MASK; 781 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 782 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 783 784 /* DFE F3-F5 Coefficient Control */ 785 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 786 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 787 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 788 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 789 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 790 791 /* G3 Setting 3 */ 792 mask = HPIPE_G3_FFE_CAP_SEL_MASK; 793 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; 794 mask |= HPIPE_G3_FFE_RES_SEL_MASK; 795 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; 796 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; 797 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; 798 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; 799 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; 800 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; 801 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; 802 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); 803 804 /* G3 Setting 4 */ 805 mask = HPIPE_G3_DFE_RES_MASK; 806 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; 807 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); 808 809 /* Offset Phase Control */ 810 mask = HPIPE_OS_PH_OFFSET_MASK; 811 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; 812 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; 813 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; 814 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 815 mask = HPIPE_OS_PH_VALID_MASK; 816 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; 817 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 818 mask = HPIPE_OS_PH_VALID_MASK; 819 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; 820 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); 821 822 /* Set G1 TX amplitude and TX post emphasis value */ 823 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 824 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 825 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; 826 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; 827 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 828 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 829 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; 830 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; 831 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 832 833 /* Set G2 TX amplitude and TX post emphasis value */ 834 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; 835 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; 836 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; 837 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; 838 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; 839 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; 840 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; 841 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; 842 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); 843 844 /* Set G3 TX amplitude and TX post emphasis value */ 845 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; 846 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; 847 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; 848 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; 849 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; 850 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; 851 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; 852 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; 853 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; 854 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; 855 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; 856 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; 857 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); 858 859 /* SERDES External Configuration 2 register */ 860 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; 861 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; 862 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 863 864 /* DFE reset sequence */ 865 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 866 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 867 HPIPE_PWR_CTR_RST_DFE_MASK); 868 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 869 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, 870 HPIPE_PWR_CTR_RST_DFE_MASK); 871 /* SW reset for interupt logic */ 872 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 873 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 874 HPIPE_PWR_CTR_SFT_RST_MASK); 875 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, 876 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, 877 HPIPE_PWR_CTR_SFT_RST_MASK); 878 879 debug("stage: Comphy power up\n"); 880 /* 881 * MAC configuration power up comphy - power up PLL/TX/RX 882 * use indirect address for vendor spesific SATA control register 883 */ 884 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 885 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, 886 SATA3_VENDOR_ADDR_MASK); 887 /* SATA 0 power up */ 888 mask = SATA3_CTRL_SATA0_PD_MASK; 889 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; 890 /* SATA 1 power up */ 891 mask |= SATA3_CTRL_SATA1_PD_MASK; 892 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; 893 /* SATA SSU enable */ 894 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; 895 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; 896 /* SATA port 1 enable */ 897 mask |= SATA3_CTRL_SATA_SSU_MASK; 898 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; 899 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); 900 901 /* MBUS request size and interface select register */ 902 reg_set(sata_base + SATA3_VENDOR_ADDRESS, 903 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, 904 SATA3_VENDOR_ADDR_MASK); 905 /* Mbus regret enable */ 906 reg_set(sata_base + SATA3_VENDOR_DATA, 907 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); 908 909 debug("stage: Check PLL\n"); 910 911 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 912 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & 913 SD_EXTERNAL_STATUS0_PLL_RX_MASK; 914 mask = data; 915 data = polling_with_timeout(addr, data, mask, 15000); 916 if (data != 0) { 917 debug("Read from reg = %p - value = 0x%x\n", 918 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); 919 error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", 920 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), 921 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); 922 ret = 0; 923 } 924 925 debug_exit(); 926 return ret; 927 } 928 929 static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, 930 void __iomem *hpipe_base, 931 void __iomem *comphy_base) 932 { 933 u32 mask, data, ret = 1; 934 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 935 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 936 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 937 void __iomem *addr; 938 939 debug_enter(); 940 debug("stage: RFU configurations - hard reset comphy\n"); 941 /* RFU configurations - hard reset comphy */ 942 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 943 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 944 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 945 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 946 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 947 948 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 949 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 950 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 951 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 952 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 953 if (sgmii_speed == PHY_SPEED_1_25G) { 954 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 955 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 956 } else { 957 /* 3.125G */ 958 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 959 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 960 } 961 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 962 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 963 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 964 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 965 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 966 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 967 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 968 969 /* release from hard reset */ 970 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 971 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 972 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 973 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 974 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 975 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 976 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 977 978 /* release from hard reset */ 979 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 980 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 981 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 982 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 983 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 984 985 986 /* Wait 1ms - until band gap and ref clock ready */ 987 mdelay(1); 988 989 /* Start comphy Configuration */ 990 debug("stage: Comphy configuration\n"); 991 /* set reference clock */ 992 mask = HPIPE_MISC_REFCLK_SEL_MASK; 993 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 994 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 995 /* Power and PLL Control */ 996 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 997 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 998 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 999 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1000 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1001 /* Loopback register */ 1002 mask = HPIPE_LOOPBACK_SEL_MASK; 1003 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1004 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1005 /* rx control 1 */ 1006 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1007 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1008 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1009 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1010 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1011 /* DTL Control */ 1012 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1013 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1014 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1015 1016 /* Set analog paramters from ETP(HW) - for now use the default datas */ 1017 debug("stage: Analog paramters from ETP(HW)\n"); 1018 1019 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1020 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1021 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1022 1023 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1024 /* SERDES External Configuration */ 1025 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1026 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1027 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1028 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1029 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1030 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1031 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1032 1033 /* check PLL rx & tx ready */ 1034 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1035 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1036 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1037 mask = data; 1038 data = polling_with_timeout(addr, data, mask, 15000); 1039 if (data != 0) { 1040 debug("Read from reg = %p - value = 0x%x\n", 1041 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1042 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1043 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1044 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1045 ret = 0; 1046 } 1047 1048 /* RX init */ 1049 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1050 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1051 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1052 1053 /* check that RX init done */ 1054 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1055 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1056 mask = data; 1057 data = polling_with_timeout(addr, data, mask, 100); 1058 if (data != 0) { 1059 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1060 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1061 ret = 0; 1062 } 1063 1064 debug("stage: RF Reset\n"); 1065 /* RF Reset */ 1066 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1067 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1068 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1069 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1070 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1071 1072 debug_exit(); 1073 return ret; 1074 } 1075 1076 static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, 1077 void __iomem *comphy_base, u32 speed) 1078 { 1079 u32 mask, data, ret = 1; 1080 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1081 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1082 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1083 void __iomem *addr; 1084 1085 debug_enter(); 1086 debug("stage: RFU configurations - hard reset comphy\n"); 1087 /* RFU configurations - hard reset comphy */ 1088 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1089 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1090 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1091 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1092 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1093 1094 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1095 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1096 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1097 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1098 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1099 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1100 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1101 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1102 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1103 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1104 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1105 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1106 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1107 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1108 1109 /* release from hard reset */ 1110 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1111 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1112 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1113 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1114 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1115 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1116 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1117 1118 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1119 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1120 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1121 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1122 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1123 1124 1125 /* Wait 1ms - until band gap and ref clock ready */ 1126 mdelay(1); 1127 1128 /* Start comphy Configuration */ 1129 debug("stage: Comphy configuration\n"); 1130 /* set reference clock */ 1131 mask = HPIPE_MISC_ICP_FORCE_MASK; 1132 data = (speed == PHY_SPEED_5_15625G) ? 1133 (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : 1134 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); 1135 mask |= HPIPE_MISC_REFCLK_SEL_MASK; 1136 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; 1137 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); 1138 /* Power and PLL Control */ 1139 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1140 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1141 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1142 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1143 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1144 /* Loopback register */ 1145 mask = HPIPE_LOOPBACK_SEL_MASK; 1146 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; 1147 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); 1148 /* rx control 1 */ 1149 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1150 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1151 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1152 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1153 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1154 /* DTL Control */ 1155 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; 1156 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; 1157 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); 1158 1159 /* Transmitter/Receiver Speed Divider Force */ 1160 if (speed == PHY_SPEED_5_15625G) { 1161 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; 1162 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; 1163 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; 1164 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; 1165 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; 1166 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; 1167 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; 1168 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; 1169 } else { 1170 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; 1171 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; 1172 } 1173 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); 1174 1175 /* Set analog paramters from ETP(HW) */ 1176 debug("stage: Analog paramters from ETP(HW)\n"); 1177 /* SERDES External Configuration 2 */ 1178 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; 1179 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; 1180 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); 1181 /* 0x7-DFE Resolution control */ 1182 mask = HPIPE_DFE_RES_FORCE_MASK; 1183 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; 1184 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); 1185 /* 0xd-G1_Setting_0 */ 1186 if (speed == PHY_SPEED_5_15625G) { 1187 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1188 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1189 } else { 1190 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; 1191 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; 1192 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; 1193 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; 1194 } 1195 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); 1196 /* Genration 1 setting 2 (G1_Setting_2) */ 1197 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; 1198 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; 1199 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; 1200 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; 1201 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); 1202 /* Transmitter Slew Rate Control register (tx_reg1) */ 1203 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; 1204 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; 1205 mask |= HPIPE_TX_REG1_SLC_EN_MASK; 1206 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; 1207 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); 1208 /* Impedance Calibration Control register (cal_reg1) */ 1209 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; 1210 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1211 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; 1212 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; 1213 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); 1214 /* Generation 1 Setting 5 (g1_setting_5) */ 1215 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; 1216 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; 1217 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); 1218 /* 0xE-G1_Setting_1 */ 1219 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1220 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1221 if (speed == PHY_SPEED_5_15625G) { 1222 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1223 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1224 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1225 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1226 } else { 1227 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1228 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1229 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1230 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1231 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; 1232 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; 1233 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; 1234 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; 1235 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; 1236 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; 1237 } 1238 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1239 1240 /* 0xA-DFE_Reg3 */ 1241 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1242 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1243 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1244 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1245 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1246 1247 /* 0x111-G1_Setting_4 */ 1248 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1249 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1250 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1251 /* Genration 1 setting 3 (G1_Setting_3) */ 1252 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; 1253 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; 1254 if (speed == PHY_SPEED_5_15625G) { 1255 /* Force FFE (Feed Forward Equalization) to 5G */ 1256 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; 1257 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; 1258 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; 1259 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; 1260 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; 1261 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; 1262 } 1263 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); 1264 1265 /* Connfigure RX training timer */ 1266 mask = HPIPE_RX_TRAIN_TIMER_MASK; 1267 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; 1268 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); 1269 1270 /* Enable TX train peak to peak hold */ 1271 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; 1272 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; 1273 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); 1274 1275 /* Configure TX preset index */ 1276 mask = HPIPE_TX_PRESET_INDEX_MASK; 1277 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; 1278 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); 1279 1280 /* Disable pattern lock lost timeout */ 1281 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; 1282 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; 1283 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); 1284 1285 /* Configure TX training pattern and TX training 16bit auto */ 1286 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; 1287 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; 1288 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; 1289 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; 1290 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); 1291 1292 /* Configure Training patten number */ 1293 mask = HPIPE_TRAIN_PAT_NUM_MASK; 1294 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; 1295 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); 1296 1297 /* Configure differencial manchester encoter to ethernet mode */ 1298 mask = HPIPE_DME_ETHERNET_MODE_MASK; 1299 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; 1300 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); 1301 1302 /* Configure VDD Continuous Calibration */ 1303 mask = HPIPE_CAL_VDD_CONT_MODE_MASK; 1304 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; 1305 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); 1306 1307 /* Trigger sampler enable pulse (by toggleing the bit) */ 1308 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; 1309 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; 1310 mask |= HPIPE_SMAPLER_MASK; 1311 data |= 0x1 << HPIPE_SMAPLER_OFFSET; 1312 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 1313 mask = HPIPE_SMAPLER_MASK; 1314 data = 0x0 << HPIPE_SMAPLER_OFFSET; 1315 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); 1316 1317 /* Set External RX Regulator Control */ 1318 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; 1319 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; 1320 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); 1321 1322 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1323 /* SERDES External Configuration */ 1324 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1325 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1326 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1327 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1328 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1329 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1330 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1331 1332 1333 /* check PLL rx & tx ready */ 1334 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1335 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1336 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1337 mask = data; 1338 data = polling_with_timeout(addr, data, mask, 15000); 1339 if (data != 0) { 1340 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1341 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1342 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1343 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1344 ret = 0; 1345 } 1346 1347 /* RX init */ 1348 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1349 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1350 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1351 1352 1353 /* check that RX init done */ 1354 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1355 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1356 mask = data; 1357 data = polling_with_timeout(addr, data, mask, 100); 1358 if (data != 0) { 1359 debug("Read from reg = %p - value = 0x%x\n", 1360 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1361 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1362 ret = 0; 1363 } 1364 1365 debug("stage: RF Reset\n"); 1366 /* RF Reset */ 1367 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1368 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1369 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1370 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1371 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1372 1373 debug_exit(); 1374 return ret; 1375 } 1376 1377 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, 1378 void __iomem *comphy_base) 1379 { 1380 u32 mask, data, ret = 1; 1381 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); 1382 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); 1383 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); 1384 void __iomem *addr; 1385 1386 debug_enter(); 1387 debug("stage: RFU configurations - hard reset comphy\n"); 1388 /* RFU configurations - hard reset comphy */ 1389 mask = COMMON_PHY_CFG1_PWR_UP_MASK; 1390 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; 1391 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; 1392 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; 1393 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); 1394 1395 if (lane == 2) { 1396 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1397 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, 1398 COMMON_PHY_SD_CTRL1_RXAUI0_MASK); 1399 } 1400 if (lane == 4) { 1401 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, 1402 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, 1403 COMMON_PHY_SD_CTRL1_RXAUI1_MASK); 1404 } 1405 1406 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ 1407 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1408 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1409 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; 1410 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; 1411 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; 1412 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; 1413 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1414 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1415 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1416 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1417 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; 1418 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; 1419 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; 1420 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; 1421 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1422 1423 /* release from hard reset */ 1424 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1425 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1426 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1427 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1428 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1429 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1430 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1431 1432 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; 1433 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; 1434 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; 1435 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; 1436 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1437 1438 /* Wait 1ms - until band gap and ref clock ready */ 1439 mdelay(1); 1440 1441 /* Start comphy Configuration */ 1442 debug("stage: Comphy configuration\n"); 1443 /* set reference clock */ 1444 reg_set(hpipe_addr + HPIPE_MISC_REG, 1445 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, 1446 HPIPE_MISC_REFCLK_SEL_MASK); 1447 /* Power and PLL Control */ 1448 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; 1449 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; 1450 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; 1451 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; 1452 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); 1453 /* Loopback register */ 1454 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 1455 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); 1456 /* rx control 1 */ 1457 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; 1458 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; 1459 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; 1460 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; 1461 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); 1462 /* DTL Control */ 1463 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, 1464 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, 1465 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); 1466 1467 /* Set analog paramters from ETP(HW) */ 1468 debug("stage: Analog paramters from ETP(HW)\n"); 1469 /* SERDES External Configuration 2 */ 1470 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 1471 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, 1472 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); 1473 /* 0x7-DFE Resolution control */ 1474 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, 1475 HPIPE_DFE_RES_FORCE_MASK); 1476 /* 0xd-G1_Setting_0 */ 1477 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, 1478 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, 1479 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); 1480 /* 0xE-G1_Setting_1 */ 1481 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; 1482 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; 1483 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; 1484 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; 1485 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; 1486 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; 1487 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); 1488 /* 0xA-DFE_Reg3 */ 1489 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; 1490 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; 1491 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; 1492 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; 1493 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); 1494 1495 /* 0x111-G1_Setting_4 */ 1496 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; 1497 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; 1498 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); 1499 1500 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); 1501 /* SERDES External Configuration */ 1502 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; 1503 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; 1504 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; 1505 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; 1506 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; 1507 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; 1508 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); 1509 1510 1511 /* check PLL rx & tx ready */ 1512 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1513 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | 1514 SD_EXTERNAL_STATUS0_PLL_TX_MASK; 1515 mask = data; 1516 data = polling_with_timeout(addr, data, mask, 15000); 1517 if (data != 0) { 1518 debug("Read from reg = %p - value = 0x%x\n", 1519 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1520 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", 1521 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), 1522 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); 1523 ret = 0; 1524 } 1525 1526 /* RX init */ 1527 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, 1528 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, 1529 SD_EXTERNAL_CONFIG1_RX_INIT_MASK); 1530 1531 /* check that RX init done */ 1532 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; 1533 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; 1534 mask = data; 1535 data = polling_with_timeout(addr, data, mask, 100); 1536 if (data != 0) { 1537 debug("Read from reg = %p - value = 0x%x\n", 1538 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); 1539 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); 1540 ret = 0; 1541 } 1542 1543 debug("stage: RF Reset\n"); 1544 /* RF Reset */ 1545 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; 1546 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; 1547 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; 1548 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; 1549 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); 1550 1551 debug_exit(); 1552 return ret; 1553 } 1554 1555 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, 1556 void __iomem *usb_cfg_addr, 1557 void __iomem *utmi_cfg_addr, 1558 u32 utmi_phy_port) 1559 { 1560 u32 mask, data; 1561 1562 debug_enter(); 1563 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", 1564 utmi_index); 1565 /* Power down UTMI PHY */ 1566 reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, 1567 UTMI_PHY_CFG_PU_MASK); 1568 1569 /* 1570 * If UTMI connected to USB Device, configure mux prior to PHY init 1571 * (Device can be connected to UTMI0 or to UTMI1) 1572 */ 1573 if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { 1574 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", 1575 utmi_index); 1576 /* USB3 Device UTMI enable */ 1577 mask = UTMI_USB_CFG_DEVICE_EN_MASK; 1578 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; 1579 /* USB3 Device UTMI MUX */ 1580 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; 1581 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; 1582 reg_set(usb_cfg_addr, data, mask); 1583 } 1584 1585 /* Set Test suspendm mode */ 1586 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; 1587 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; 1588 /* Enable Test UTMI select */ 1589 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; 1590 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; 1591 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); 1592 1593 /* Wait for UTMI power down */ 1594 mdelay(1); 1595 1596 debug_exit(); 1597 return; 1598 } 1599 1600 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, 1601 void __iomem *usb_cfg_addr, 1602 void __iomem *utmi_cfg_addr, 1603 u32 utmi_phy_port) 1604 { 1605 u32 mask, data; 1606 1607 debug_exit(); 1608 debug("stage: Configure UTMI PHY %d registers\n", utmi_index); 1609 /* Reference Clock Divider Select */ 1610 mask = UTMI_PLL_CTRL_REFDIV_MASK; 1611 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; 1612 /* Feedback Clock Divider Select - 90 for 25Mhz*/ 1613 mask |= UTMI_PLL_CTRL_FBDIV_MASK; 1614 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; 1615 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ 1616 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; 1617 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; 1618 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); 1619 1620 /* Impedance Calibration Threshold Setting */ 1621 reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, 1622 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, 1623 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); 1624 1625 /* Set LS TX driver strength coarse control */ 1626 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; 1627 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; 1628 /* Set LS TX driver fine adjustment */ 1629 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; 1630 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; 1631 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); 1632 1633 /* Enable SQ */ 1634 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; 1635 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; 1636 /* Enable analog squelch detect */ 1637 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; 1638 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; 1639 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); 1640 1641 /* Set External squelch calibration number */ 1642 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; 1643 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; 1644 /* Enable the External squelch calibration */ 1645 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; 1646 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; 1647 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); 1648 1649 /* Set Control VDAT Reference Voltage - 0.325V */ 1650 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; 1651 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; 1652 /* Set Control VSRC Reference Voltage - 0.6V */ 1653 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; 1654 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; 1655 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); 1656 1657 debug_exit(); 1658 return; 1659 } 1660 1661 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, 1662 void __iomem *usb_cfg_addr, 1663 void __iomem *utmi_cfg_addr, u32 utmi_phy_port) 1664 { 1665 u32 data, mask, ret = 1; 1666 void __iomem *addr; 1667 1668 debug_enter(); 1669 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", 1670 utmi_index); 1671 /* Power UP UTMI PHY */ 1672 reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, 1673 UTMI_PHY_CFG_PU_MASK); 1674 /* Disable Test UTMI select */ 1675 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, 1676 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, 1677 UTMI_CTRL_STATUS0_TEST_SEL_MASK); 1678 1679 debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); 1680 addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; 1681 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; 1682 mask = data; 1683 data = polling_with_timeout(addr, data, mask, 100); 1684 if (data != 0) { 1685 error("Impedance calibration is not done\n"); 1686 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1687 ret = 0; 1688 } 1689 1690 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; 1691 mask = data; 1692 data = polling_with_timeout(addr, data, mask, 100); 1693 if (data != 0) { 1694 error("PLL calibration is not done\n"); 1695 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1696 ret = 0; 1697 } 1698 1699 addr = utmi_base_addr + UTMI_PLL_CTRL_REG; 1700 data = UTMI_PLL_CTRL_PLL_RDY_MASK; 1701 mask = data; 1702 data = polling_with_timeout(addr, data, mask, 100); 1703 if (data != 0) { 1704 error("PLL is not ready\n"); 1705 debug("Read from reg = %p - value = 0x%x\n", addr, data); 1706 ret = 0; 1707 } 1708 1709 if (ret) 1710 debug("Passed\n"); 1711 else 1712 debug("\n"); 1713 1714 debug_exit(); 1715 return ret; 1716 } 1717 1718 /* 1719 * comphy_utmi_phy_init initialize the UTMI PHY 1720 * the init split in 3 parts: 1721 * 1. Power down transceiver and PLL 1722 * 2. UTMI PHY configure 1723 * 3. Powe up transceiver and PLL 1724 * Note: - Power down/up should be once for both UTMI PHYs 1725 * - comphy_dedicated_phys_init call this function if at least there is 1726 * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is 1727 * legal 1728 */ 1729 static void comphy_utmi_phy_init(u32 utmi_phy_count, 1730 struct utmi_phy_data *cp110_utmi_data) 1731 { 1732 u32 i; 1733 1734 debug_enter(); 1735 /* UTMI Power down */ 1736 for (i = 0; i < utmi_phy_count; i++) { 1737 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, 1738 cp110_utmi_data[i].usb_cfg_addr, 1739 cp110_utmi_data[i].utmi_cfg_addr, 1740 cp110_utmi_data[i].utmi_phy_port); 1741 } 1742 /* PLL Power down */ 1743 debug("stage: UTMI PHY power down PLL\n"); 1744 for (i = 0; i < utmi_phy_count; i++) { 1745 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1746 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1747 } 1748 /* UTMI configure */ 1749 for (i = 0; i < utmi_phy_count; i++) { 1750 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, 1751 cp110_utmi_data[i].usb_cfg_addr, 1752 cp110_utmi_data[i].utmi_cfg_addr, 1753 cp110_utmi_data[i].utmi_phy_port); 1754 } 1755 /* UTMI Power up */ 1756 for (i = 0; i < utmi_phy_count; i++) { 1757 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, 1758 cp110_utmi_data[i].usb_cfg_addr, 1759 cp110_utmi_data[i].utmi_cfg_addr, 1760 cp110_utmi_data[i].utmi_phy_port)) { 1761 error("Failed to initialize UTMI PHY %d\n", i); 1762 continue; 1763 } 1764 printf("UTMI PHY %d initialized to ", i); 1765 if (cp110_utmi_data[i].utmi_phy_port == 1766 UTMI_PHY_TO_USB3_DEVICE0) 1767 printf("USB Device\n"); 1768 else 1769 printf("USB Host%d\n", 1770 cp110_utmi_data[i].utmi_phy_port); 1771 } 1772 /* PLL Power up */ 1773 debug("stage: UTMI PHY power up PLL\n"); 1774 for (i = 0; i < utmi_phy_count; i++) { 1775 reg_set(cp110_utmi_data[i].usb_cfg_addr, 1776 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); 1777 } 1778 1779 debug_exit(); 1780 return; 1781 } 1782 1783 /* 1784 * comphy_dedicated_phys_init initialize the dedicated PHYs 1785 * - not muxed SerDes lanes e.g. UTMI PHY 1786 */ 1787 void comphy_dedicated_phys_init(void) 1788 { 1789 struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; 1790 int node; 1791 int i; 1792 1793 debug_enter(); 1794 debug("Initialize USB UTMI PHYs\n"); 1795 1796 /* Find the UTMI phy node in device tree and go over them */ 1797 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1798 "marvell,mvebu-utmi-2.6.0"); 1799 1800 i = 0; 1801 while (node > 0) { 1802 /* get base address of UTMI phy */ 1803 cp110_utmi_data[i].utmi_base_addr = 1804 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1805 gd->fdt_blob, node, "reg", 0, NULL, true); 1806 if (cp110_utmi_data[i].utmi_base_addr == NULL) { 1807 error("UTMI PHY base address is invalid\n"); 1808 i++; 1809 continue; 1810 } 1811 1812 /* get usb config address */ 1813 cp110_utmi_data[i].usb_cfg_addr = 1814 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1815 gd->fdt_blob, node, "reg", 1, NULL, true); 1816 if (cp110_utmi_data[i].usb_cfg_addr == NULL) { 1817 error("UTMI PHY base address is invalid\n"); 1818 i++; 1819 continue; 1820 } 1821 1822 /* get UTMI config address */ 1823 cp110_utmi_data[i].utmi_cfg_addr = 1824 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1825 gd->fdt_blob, node, "reg", 2, NULL, true); 1826 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { 1827 error("UTMI PHY base address is invalid\n"); 1828 i++; 1829 continue; 1830 } 1831 1832 /* 1833 * get the port number (to check if the utmi connected to 1834 * host/device) 1835 */ 1836 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( 1837 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); 1838 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { 1839 error("UTMI PHY port type is invalid\n"); 1840 i++; 1841 continue; 1842 } 1843 1844 node = fdt_node_offset_by_compatible( 1845 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); 1846 i++; 1847 } 1848 1849 if (i > 0) 1850 comphy_utmi_phy_init(i, cp110_utmi_data); 1851 1852 debug_exit(); 1853 } 1854 1855 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1856 struct comphy_map *serdes_map) 1857 { 1858 void __iomem *comphy_base_addr; 1859 struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; 1860 struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; 1861 u32 lane, comphy_max_count; 1862 1863 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1864 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1865 1866 /* 1867 * Copy the SerDes map configuration for PIPE map and PHY map 1868 * the comphy_mux_init modify the type of the lane if the type 1869 * is not valid because we have 2 selectores run the 1870 * comphy_mux_init twice and after that update the original 1871 * serdes_map 1872 */ 1873 for (lane = 0; lane < comphy_max_count; lane++) { 1874 comphy_map_pipe_data[lane].type = serdes_map[lane].type; 1875 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; 1876 comphy_map_phy_data[lane].type = serdes_map[lane].type; 1877 comphy_map_phy_data[lane].speed = serdes_map[lane].speed; 1878 } 1879 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; 1880 comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, 1881 comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); 1882 1883 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; 1884 comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, 1885 comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); 1886 /* Fix the type after check the PHY and PIPE configuration */ 1887 for (lane = 0; lane < comphy_max_count; lane++) { 1888 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && 1889 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) 1890 serdes_map[lane].type = PHY_TYPE_UNCONNECTED; 1891 } 1892 } 1893 1894 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, 1895 struct comphy_map *serdes_map) 1896 { 1897 struct comphy_map *ptr_comphy_map; 1898 void __iomem *comphy_base_addr, *hpipe_base_addr; 1899 u32 comphy_max_count, lane, ret = 0; 1900 u32 pcie_width = 0; 1901 1902 debug_enter(); 1903 1904 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; 1905 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; 1906 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; 1907 1908 /* Config Comphy mux configuration */ 1909 comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); 1910 1911 /* Check if the first 4 lanes configured as By-4 */ 1912 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; 1913 lane++, ptr_comphy_map++) { 1914 if (ptr_comphy_map->type != PHY_TYPE_PEX0) 1915 break; 1916 pcie_width++; 1917 } 1918 1919 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; 1920 lane++, ptr_comphy_map++) { 1921 debug("Initialize serdes number %d\n", lane); 1922 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); 1923 if (lane == 4) { 1924 /* 1925 * PCIe lanes above the first 4 lanes, can be only 1926 * by1 1927 */ 1928 pcie_width = 1; 1929 } 1930 switch (ptr_comphy_map->type) { 1931 case PHY_TYPE_UNCONNECTED: 1932 case PHY_TYPE_IGNORE: 1933 continue; 1934 break; 1935 case PHY_TYPE_PEX0: 1936 case PHY_TYPE_PEX1: 1937 case PHY_TYPE_PEX2: 1938 case PHY_TYPE_PEX3: 1939 ret = comphy_pcie_power_up( 1940 lane, pcie_width, ptr_comphy_map->clk_src, 1941 serdes_map->end_point, 1942 hpipe_base_addr, comphy_base_addr); 1943 break; 1944 case PHY_TYPE_SATA0: 1945 case PHY_TYPE_SATA1: 1946 case PHY_TYPE_SATA2: 1947 case PHY_TYPE_SATA3: 1948 ret = comphy_sata_power_up( 1949 lane, hpipe_base_addr, comphy_base_addr, 1950 ptr_chip_cfg->comphy_index); 1951 break; 1952 case PHY_TYPE_USB3_HOST0: 1953 case PHY_TYPE_USB3_HOST1: 1954 case PHY_TYPE_USB3_DEVICE: 1955 ret = comphy_usb3_power_up(lane, hpipe_base_addr, 1956 comphy_base_addr); 1957 break; 1958 case PHY_TYPE_SGMII0: 1959 case PHY_TYPE_SGMII1: 1960 case PHY_TYPE_SGMII2: 1961 case PHY_TYPE_SGMII3: 1962 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { 1963 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", 1964 lane); 1965 ptr_comphy_map->speed = PHY_SPEED_1_25G; 1966 } 1967 ret = comphy_sgmii_power_up( 1968 lane, ptr_comphy_map->speed, hpipe_base_addr, 1969 comphy_base_addr); 1970 break; 1971 case PHY_TYPE_SFI: 1972 ret = comphy_sfi_power_up(lane, hpipe_base_addr, 1973 comphy_base_addr, 1974 ptr_comphy_map->speed); 1975 break; 1976 case PHY_TYPE_RXAUI0: 1977 case PHY_TYPE_RXAUI1: 1978 ret = comphy_rxauii_power_up(lane, hpipe_base_addr, 1979 comphy_base_addr); 1980 break; 1981 default: 1982 debug("Unknown SerDes type, skip initialize SerDes %d\n", 1983 lane); 1984 break; 1985 } 1986 if (ret == 0) { 1987 /* 1988 * If interface wans't initialized, set the lane to 1989 * PHY_TYPE_UNCONNECTED state. 1990 */ 1991 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; 1992 error("PLL is not locked - Failed to initialize lane %d\n", 1993 lane); 1994 } 1995 } 1996 1997 debug_exit(); 1998 return 0; 1999 } 2000