1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define DEBUG 14 #define pr_fmt(fmt) "tegra-pcie: " fmt 15 16 #include <common.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 /* Default value provided by HW engineering is 0xfa5c */ 158 #define PADS_REFCLK_CFG_VALUE \ 159 ( \ 160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ 161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ 162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ 163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ 164 ) 165 166 #define RP_VEND_XP 0x00000F00 167 #define RP_VEND_XP_DL_UP (1 << 30) 168 169 #define RP_VEND_CTL2 0x00000FA8 170 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 171 172 #define RP_PRIV_MISC 0x00000FE0 173 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 174 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 175 176 #define RP_LINK_CONTROL_STATUS 0x00000090 177 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 178 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 179 180 struct tegra_pcie; 181 182 struct tegra_pcie_port { 183 struct tegra_pcie *pcie; 184 185 struct fdt_resource regs; 186 unsigned int num_lanes; 187 unsigned int index; 188 189 struct list_head list; 190 }; 191 192 struct tegra_pcie_soc { 193 unsigned int num_ports; 194 unsigned long pads_pll_ctl; 195 unsigned long tx_ref_sel; 196 bool has_pex_clkreq_en; 197 bool has_pex_bias_ctrl; 198 bool has_cml_clk; 199 bool has_gen2; 200 bool force_pca_enable; 201 }; 202 203 struct tegra_pcie { 204 struct pci_controller hose; 205 206 struct fdt_resource pads; 207 struct fdt_resource afi; 208 struct fdt_resource cs; 209 210 struct fdt_resource prefetch; 211 struct fdt_resource mem; 212 struct fdt_resource io; 213 214 struct list_head ports; 215 unsigned long xbar; 216 217 const struct tegra_pcie_soc *soc; 218 struct tegra_xusb_phy *phy; 219 }; 220 221 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) 222 { 223 return container_of(hose, struct tegra_pcie, hose); 224 } 225 226 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 227 unsigned long offset) 228 { 229 writel(value, pcie->afi.start + offset); 230 } 231 232 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 233 { 234 return readl(pcie->afi.start + offset); 235 } 236 237 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 238 unsigned long offset) 239 { 240 writel(value, pcie->pads.start + offset); 241 } 242 243 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 244 { 245 return readl(pcie->pads.start + offset); 246 } 247 248 static unsigned long rp_readl(struct tegra_pcie_port *port, 249 unsigned long offset) 250 { 251 return readl(port->regs.start + offset); 252 } 253 254 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 255 unsigned long offset) 256 { 257 writel(value, port->regs.start + offset); 258 } 259 260 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 261 { 262 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 263 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 264 (where & 0xfc); 265 } 266 267 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 268 int where, unsigned long *address) 269 { 270 unsigned int bus = PCI_BUS(bdf); 271 272 if (bus == 0) { 273 unsigned int dev = PCI_DEV(bdf); 274 struct tegra_pcie_port *port; 275 276 list_for_each_entry(port, &pcie->ports, list) { 277 if (port->index + 1 == dev) { 278 *address = port->regs.start + (where & ~3); 279 return 0; 280 } 281 } 282 } else { 283 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 284 return 0; 285 } 286 287 return -1; 288 } 289 290 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, 291 int where, u32 *value) 292 { 293 struct tegra_pcie *pcie = to_tegra_pcie(hose); 294 unsigned long address; 295 int err; 296 297 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 298 if (err < 0) { 299 *value = 0xffffffff; 300 return 1; 301 } 302 303 *value = readl(address); 304 305 /* fixup root port class */ 306 if (PCI_BUS(bdf) == 0) { 307 if (where == PCI_CLASS_REVISION) { 308 *value &= ~0x00ff0000; 309 *value |= PCI_CLASS_BRIDGE_PCI << 16; 310 } 311 } 312 313 return 0; 314 } 315 316 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, 317 int where, u32 value) 318 { 319 struct tegra_pcie *pcie = to_tegra_pcie(hose); 320 unsigned long address; 321 int err; 322 323 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 324 if (err < 0) 325 return 1; 326 327 writel(value, address); 328 329 return 0; 330 } 331 332 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 333 struct tegra_pcie_port *port) 334 { 335 const u32 *addr; 336 int len; 337 338 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 339 if (!addr) { 340 error("property \"assigned-addresses\" not found"); 341 return -FDT_ERR_NOTFOUND; 342 } 343 344 port->regs.start = fdt32_to_cpu(addr[2]); 345 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 346 347 return 0; 348 } 349 350 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 351 unsigned long *xbar) 352 { 353 enum fdt_compat_id id = fdtdec_lookup(fdt, node); 354 355 switch (id) { 356 case COMPAT_NVIDIA_TEGRA20_PCIE: 357 switch (lanes) { 358 case 0x00000004: 359 debug("single-mode configuration\n"); 360 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 361 return 0; 362 363 case 0x00000202: 364 debug("dual-mode configuration\n"); 365 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 366 return 0; 367 } 368 break; 369 370 case COMPAT_NVIDIA_TEGRA30_PCIE: 371 switch (lanes) { 372 case 0x00000204: 373 debug("4x1, 2x1 configuration\n"); 374 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 375 return 0; 376 377 case 0x00020202: 378 debug("2x3 configuration\n"); 379 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 380 return 0; 381 382 case 0x00010104: 383 debug("4x1, 1x2 configuration\n"); 384 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 385 return 0; 386 } 387 break; 388 389 case COMPAT_NVIDIA_TEGRA124_PCIE: 390 switch (lanes) { 391 case 0x0000104: 392 debug("4x1, 1x1 configuration\n"); 393 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 394 return 0; 395 396 case 0x0000102: 397 debug("2x1, 1x1 configuration\n"); 398 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 399 return 0; 400 } 401 break; 402 403 default: 404 break; 405 } 406 407 return -FDT_ERR_NOTFOUND; 408 } 409 410 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, 411 struct tegra_pcie *pcie) 412 { 413 int parent, na_parent, na_pcie, ns_pcie; 414 const u32 *ptr, *end; 415 int len; 416 417 parent = fdt_parent_offset(fdt, node); 418 if (parent < 0) { 419 error("Can't find PCI parent node\n"); 420 return -FDT_ERR_NOTFOUND; 421 } 422 423 na_parent = fdt_address_cells(fdt, parent); 424 if (na_parent < 1) { 425 error("bad #address-cells for PCIE parent\n"); 426 return -FDT_ERR_NOTFOUND; 427 } 428 429 na_pcie = fdt_address_cells(fdt, node); 430 if (na_pcie < 1) { 431 error("bad #address-cells for PCIE\n"); 432 return -FDT_ERR_NOTFOUND; 433 } 434 435 ns_pcie = fdt_size_cells(fdt, node); 436 if (ns_pcie < 1) { 437 error("bad #size-cells for PCIE\n"); 438 return -FDT_ERR_NOTFOUND; 439 } 440 441 ptr = fdt_getprop(fdt, node, "ranges", &len); 442 if (!ptr) { 443 error("missing \"ranges\" property"); 444 return -FDT_ERR_NOTFOUND; 445 } 446 447 end = ptr + len / 4; 448 449 while (ptr < end) { 450 struct fdt_resource *res = NULL; 451 u32 space = fdt32_to_cpu(*ptr); 452 453 switch ((space >> 24) & 0x3) { 454 case 0x01: 455 res = &pcie->io; 456 break; 457 458 case 0x02: /* 32 bit */ 459 case 0x03: /* 64 bit */ 460 if (space & (1 << 30)) 461 res = &pcie->prefetch; 462 else 463 res = &pcie->mem; 464 465 break; 466 } 467 468 if (res) { 469 int start_low = na_pcie + (na_parent - 1); 470 int size_low = na_pcie + na_parent + (ns_pcie - 1); 471 res->start = fdt32_to_cpu(ptr[start_low]); 472 res->end = res->start + fdt32_to_cpu(ptr[size_low]); 473 } 474 475 ptr += na_pcie + na_parent + ns_pcie; 476 } 477 478 debug("PCI regions:\n"); 479 debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end); 480 debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start, 481 &pcie->mem.end); 482 debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start, 483 &pcie->prefetch.end); 484 485 return 0; 486 } 487 488 static int tegra_pcie_parse_port_info(const void *fdt, int node, 489 unsigned int *index, 490 unsigned int *lanes) 491 { 492 struct fdt_pci_addr addr; 493 int err; 494 495 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 496 if (err < 0) { 497 error("failed to parse \"nvidia,num-lanes\" property"); 498 return err; 499 } 500 501 *lanes = err; 502 503 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); 504 if (err < 0) { 505 error("failed to parse \"reg\" property"); 506 return err; 507 } 508 509 *index = PCI_DEV(addr.phys_hi) - 1; 510 511 return 0; 512 } 513 514 static int tegra_pcie_parse_dt(const void *fdt, int node, 515 struct tegra_pcie *pcie) 516 { 517 int err, subnode; 518 u32 lanes = 0; 519 520 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 521 &pcie->pads); 522 if (err < 0) { 523 error("resource \"pads\" not found"); 524 return err; 525 } 526 527 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 528 &pcie->afi); 529 if (err < 0) { 530 error("resource \"afi\" not found"); 531 return err; 532 } 533 534 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 535 &pcie->cs); 536 if (err < 0) { 537 error("resource \"cs\" not found"); 538 return err; 539 } 540 541 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 542 if (pcie->phy) { 543 err = tegra_xusb_phy_prepare(pcie->phy); 544 if (err < 0) { 545 error("failed to prepare PHY: %d", err); 546 return err; 547 } 548 } 549 550 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); 551 if (err < 0) { 552 error("failed to parse \"ranges\" property"); 553 return err; 554 } 555 556 fdt_for_each_subnode(fdt, subnode, node) { 557 unsigned int index = 0, num_lanes = 0; 558 struct tegra_pcie_port *port; 559 560 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 561 &num_lanes); 562 if (err < 0) { 563 error("failed to obtain root port info"); 564 continue; 565 } 566 567 lanes |= num_lanes << (index << 3); 568 569 if (!fdtdec_get_is_enabled(fdt, subnode)) 570 continue; 571 572 port = malloc(sizeof(*port)); 573 if (!port) 574 continue; 575 576 memset(port, 0, sizeof(*port)); 577 port->num_lanes = num_lanes; 578 port->index = index; 579 580 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 581 if (err < 0) { 582 free(port); 583 continue; 584 } 585 586 list_add_tail(&port->list, &pcie->ports); 587 port->pcie = pcie; 588 } 589 590 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); 591 if (err < 0) { 592 error("invalid lane configuration"); 593 return err; 594 } 595 596 return 0; 597 } 598 599 int __weak tegra_pcie_board_init(void) 600 { 601 return 0; 602 } 603 604 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 605 { 606 const struct tegra_pcie_soc *soc = pcie->soc; 607 unsigned long value; 608 int err; 609 610 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 611 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 612 reset_set_enable(PERIPH_ID_AFI, 1); 613 reset_set_enable(PERIPH_ID_PCIE, 1); 614 615 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 616 if (err < 0) { 617 error("failed to power off PCIe partition: %d", err); 618 return err; 619 } 620 621 tegra_pcie_board_init(); 622 623 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 624 PERIPH_ID_PCIE); 625 if (err < 0) { 626 error("failed to power up PCIe partition: %d", err); 627 return err; 628 } 629 630 /* take AFI controller out of reset */ 631 reset_set_enable(PERIPH_ID_AFI, 0); 632 633 /* enable AFI clock */ 634 clock_enable(PERIPH_ID_AFI); 635 636 if (soc->has_cml_clk) { 637 /* enable CML clock */ 638 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 639 value |= (1 << 0); 640 value &= ~(1 << 1); 641 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 642 } 643 644 err = tegra_plle_enable(); 645 if (err < 0) { 646 error("failed to enable PLLE: %d\n", err); 647 return err; 648 } 649 650 return 0; 651 } 652 653 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 654 { 655 const struct tegra_pcie_soc *soc = pcie->soc; 656 unsigned long start = get_timer(0); 657 u32 value; 658 659 while (get_timer(start) < timeout) { 660 value = pads_readl(pcie, soc->pads_pll_ctl); 661 if (value & PADS_PLL_CTL_LOCKDET) 662 return 0; 663 } 664 665 return -ETIMEDOUT; 666 } 667 668 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 669 { 670 const struct tegra_pcie_soc *soc = pcie->soc; 671 u32 value; 672 int err; 673 674 /* initialize internal PHY, enable up to 16 PCIe lanes */ 675 pads_writel(pcie, 0, PADS_CTL_SEL); 676 677 /* override IDDQ to 1 on all 4 lanes */ 678 value = pads_readl(pcie, PADS_CTL); 679 value |= PADS_CTL_IDDQ_1L; 680 pads_writel(pcie, value, PADS_CTL); 681 682 /* 683 * Set up PHY PLL inputs select PLLE output as refclock, set TX 684 * ref sel to div10 (not div5). 685 */ 686 value = pads_readl(pcie, soc->pads_pll_ctl); 687 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 688 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 689 pads_writel(pcie, value, soc->pads_pll_ctl); 690 691 /* reset PLL */ 692 value = pads_readl(pcie, soc->pads_pll_ctl); 693 value &= ~PADS_PLL_CTL_RST_B4SM; 694 pads_writel(pcie, value, soc->pads_pll_ctl); 695 696 udelay(20); 697 698 /* take PLL out of reset */ 699 value = pads_readl(pcie, soc->pads_pll_ctl); 700 value |= PADS_PLL_CTL_RST_B4SM; 701 pads_writel(pcie, value, soc->pads_pll_ctl); 702 703 /* configure the reference clock driver */ 704 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); 705 pads_writel(pcie, value, PADS_REFCLK_CFG0); 706 707 if (soc->num_ports > 2) 708 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); 709 710 /* wait for the PLL to lock */ 711 err = tegra_pcie_pll_wait(pcie, 500); 712 if (err < 0) { 713 error("PLL failed to lock: %d", err); 714 return err; 715 } 716 717 /* turn off IDDQ override */ 718 value = pads_readl(pcie, PADS_CTL); 719 value &= ~PADS_CTL_IDDQ_1L; 720 pads_writel(pcie, value, PADS_CTL); 721 722 /* enable TX/RX data */ 723 value = pads_readl(pcie, PADS_CTL); 724 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 725 pads_writel(pcie, value, PADS_CTL); 726 727 return 0; 728 } 729 730 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 731 { 732 const struct tegra_pcie_soc *soc = pcie->soc; 733 struct tegra_pcie_port *port; 734 u32 value; 735 int err; 736 737 if (pcie->phy) { 738 value = afi_readl(pcie, AFI_PLLE_CONTROL); 739 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 740 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 741 afi_writel(pcie, value, AFI_PLLE_CONTROL); 742 } 743 744 if (soc->has_pex_bias_ctrl) 745 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 746 747 value = afi_readl(pcie, AFI_PCIE_CONFIG); 748 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 749 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 750 751 list_for_each_entry(port, &pcie->ports, list) 752 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 753 754 afi_writel(pcie, value, AFI_PCIE_CONFIG); 755 756 value = afi_readl(pcie, AFI_FUSE); 757 758 if (soc->has_gen2) 759 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 760 else 761 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 762 763 afi_writel(pcie, value, AFI_FUSE); 764 765 if (pcie->phy) 766 err = tegra_xusb_phy_enable(pcie->phy); 767 else 768 err = tegra_pcie_phy_enable(pcie); 769 770 if (err < 0) { 771 error("failed to power on PHY: %d\n", err); 772 return err; 773 } 774 775 /* take the PCIEXCLK logic out of reset */ 776 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 777 778 /* finally enable PCIe */ 779 value = afi_readl(pcie, AFI_CONFIGURATION); 780 value |= AFI_CONFIGURATION_EN_FPCI; 781 afi_writel(pcie, value, AFI_CONFIGURATION); 782 783 /* disable all interrupts */ 784 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 785 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 786 afi_writel(pcie, 0, AFI_INTR_MASK); 787 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 788 789 return 0; 790 } 791 792 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) 793 { 794 unsigned long fpci, axi, size; 795 796 /* BAR 0: type 1 extended configuration space */ 797 fpci = 0xfe100000; 798 size = fdt_resource_size(&pcie->cs); 799 axi = pcie->cs.start; 800 801 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 802 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 803 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 804 805 /* BAR 1: downstream I/O */ 806 fpci = 0xfdfc0000; 807 size = fdt_resource_size(&pcie->io); 808 axi = pcie->io.start; 809 810 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 811 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 812 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 813 814 /* BAR 2: prefetchable memory */ 815 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; 816 size = fdt_resource_size(&pcie->prefetch); 817 axi = pcie->prefetch.start; 818 819 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 820 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 821 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 822 823 /* BAR 3: non-prefetchable memory */ 824 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; 825 size = fdt_resource_size(&pcie->mem); 826 axi = pcie->mem.start; 827 828 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 829 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 830 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 831 832 /* NULL out the remaining BARs as they are not used */ 833 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 834 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 835 afi_writel(pcie, 0, AFI_FPCI_BAR4); 836 837 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 838 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 839 afi_writel(pcie, 0, AFI_FPCI_BAR5); 840 841 /* map all upstream transactions as uncached */ 842 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 843 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 844 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 845 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 846 847 /* MSI translations are setup only when needed */ 848 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 849 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 850 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 851 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 852 } 853 854 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 855 { 856 unsigned long ret = 0; 857 858 switch (port->index) { 859 case 0: 860 ret = AFI_PEX0_CTRL; 861 break; 862 863 case 1: 864 ret = AFI_PEX1_CTRL; 865 break; 866 867 case 2: 868 ret = AFI_PEX2_CTRL; 869 break; 870 } 871 872 return ret; 873 } 874 875 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 876 { 877 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 878 unsigned long value; 879 880 /* pulse reset signel */ 881 value = afi_readl(port->pcie, ctrl); 882 value &= ~AFI_PEX_CTRL_RST; 883 afi_writel(port->pcie, value, ctrl); 884 885 udelay(2000); 886 887 value = afi_readl(port->pcie, ctrl); 888 value |= AFI_PEX_CTRL_RST; 889 afi_writel(port->pcie, value, ctrl); 890 } 891 892 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 893 { 894 const struct tegra_pcie_soc *soc = port->pcie->soc; 895 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 896 unsigned long value; 897 898 /* enable reference clock */ 899 value = afi_readl(port->pcie, ctrl); 900 value |= AFI_PEX_CTRL_REFCLK_EN; 901 902 if (port->pcie->soc->has_pex_clkreq_en) 903 value |= AFI_PEX_CTRL_CLKREQ_EN; 904 905 value |= AFI_PEX_CTRL_OVERRIDE_EN; 906 907 afi_writel(port->pcie, value, ctrl); 908 909 tegra_pcie_port_reset(port); 910 911 if (soc->force_pca_enable) { 912 value = rp_readl(port, RP_VEND_CTL2); 913 value |= RP_VEND_CTL2_PCA_ENABLE; 914 rp_writel(port, value, RP_VEND_CTL2); 915 } 916 } 917 918 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 919 { 920 unsigned int retries = 3; 921 unsigned long value; 922 923 value = rp_readl(port, RP_PRIV_MISC); 924 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 925 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 926 rp_writel(port, value, RP_PRIV_MISC); 927 928 do { 929 unsigned int timeout = 200; 930 931 do { 932 value = rp_readl(port, RP_VEND_XP); 933 if (value & RP_VEND_XP_DL_UP) 934 break; 935 936 udelay(2000); 937 } while (--timeout); 938 939 if (!timeout) { 940 debug("link %u down, retrying\n", port->index); 941 goto retry; 942 } 943 944 timeout = 200; 945 946 do { 947 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 948 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 949 return true; 950 951 udelay(2000); 952 } while (--timeout); 953 954 retry: 955 tegra_pcie_port_reset(port); 956 } while (--retries); 957 958 return false; 959 } 960 961 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 962 { 963 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 964 unsigned long value; 965 966 /* assert port reset */ 967 value = afi_readl(port->pcie, ctrl); 968 value &= ~AFI_PEX_CTRL_RST; 969 afi_writel(port->pcie, value, ctrl); 970 971 /* disable reference clock */ 972 value = afi_readl(port->pcie, ctrl); 973 value &= ~AFI_PEX_CTRL_REFCLK_EN; 974 afi_writel(port->pcie, value, ctrl); 975 } 976 977 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 978 { 979 list_del(&port->list); 980 free(port); 981 } 982 983 static int tegra_pcie_enable(struct tegra_pcie *pcie) 984 { 985 struct tegra_pcie_port *port, *tmp; 986 987 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 988 debug("probing port %u, using %u lanes\n", port->index, 989 port->num_lanes); 990 991 tegra_pcie_port_enable(port); 992 993 if (tegra_pcie_port_check_link(port)) 994 continue; 995 996 debug("link %u down, ignoring\n", port->index); 997 998 tegra_pcie_port_disable(port); 999 tegra_pcie_port_free(port); 1000 } 1001 1002 return 0; 1003 } 1004 1005 static const struct tegra_pcie_soc tegra20_pcie_soc = { 1006 .num_ports = 2, 1007 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 1008 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 1009 .has_pex_clkreq_en = false, 1010 .has_pex_bias_ctrl = false, 1011 .has_cml_clk = false, 1012 .has_gen2 = false, 1013 .force_pca_enable = false, 1014 }; 1015 1016 static const struct tegra_pcie_soc tegra30_pcie_soc = { 1017 .num_ports = 3, 1018 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1019 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1020 .has_pex_clkreq_en = true, 1021 .has_pex_bias_ctrl = true, 1022 .has_cml_clk = true, 1023 .has_gen2 = false, 1024 .force_pca_enable = false, 1025 }; 1026 1027 static const struct tegra_pcie_soc tegra124_pcie_soc = { 1028 .num_ports = 2, 1029 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1030 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1031 .has_pex_clkreq_en = true, 1032 .has_pex_bias_ctrl = true, 1033 .has_cml_clk = true, 1034 .has_gen2 = true, 1035 .force_pca_enable = false, 1036 }; 1037 1038 static int process_nodes(const void *fdt, int nodes[], unsigned int count) 1039 { 1040 unsigned int i; 1041 uint64_t dram_end; 1042 uint32_t pci_dram_size; 1043 1044 /* Clip PCI-accessible DRAM to 32-bits */ 1045 dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size; 1046 if (dram_end > 0x100000000) 1047 dram_end = 0x100000000; 1048 pci_dram_size = dram_end - NV_PA_SDRAM_BASE; 1049 1050 for (i = 0; i < count; i++) { 1051 const struct tegra_pcie_soc *soc; 1052 struct tegra_pcie *pcie; 1053 enum fdt_compat_id id; 1054 int err; 1055 1056 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 1057 continue; 1058 1059 id = fdtdec_lookup(fdt, nodes[i]); 1060 switch (id) { 1061 case COMPAT_NVIDIA_TEGRA20_PCIE: 1062 soc = &tegra20_pcie_soc; 1063 break; 1064 1065 case COMPAT_NVIDIA_TEGRA30_PCIE: 1066 soc = &tegra30_pcie_soc; 1067 break; 1068 1069 case COMPAT_NVIDIA_TEGRA124_PCIE: 1070 soc = &tegra124_pcie_soc; 1071 break; 1072 1073 default: 1074 error("unsupported compatible: %s", 1075 fdtdec_get_compatible(id)); 1076 continue; 1077 } 1078 1079 pcie = malloc(sizeof(*pcie)); 1080 if (!pcie) { 1081 error("failed to allocate controller"); 1082 continue; 1083 } 1084 1085 memset(pcie, 0, sizeof(*pcie)); 1086 pcie->soc = soc; 1087 1088 INIT_LIST_HEAD(&pcie->ports); 1089 1090 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); 1091 if (err < 0) { 1092 free(pcie); 1093 continue; 1094 } 1095 1096 err = tegra_pcie_power_on(pcie); 1097 if (err < 0) { 1098 error("failed to power on"); 1099 continue; 1100 } 1101 1102 err = tegra_pcie_enable_controller(pcie); 1103 if (err < 0) { 1104 error("failed to enable controller"); 1105 continue; 1106 } 1107 1108 tegra_pcie_setup_translations(pcie); 1109 1110 err = tegra_pcie_enable(pcie); 1111 if (err < 0) { 1112 error("failed to enable PCIe"); 1113 continue; 1114 } 1115 1116 pcie->hose.first_busno = 0; 1117 pcie->hose.current_busno = 0; 1118 pcie->hose.last_busno = 0; 1119 1120 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, 1121 NV_PA_SDRAM_BASE, pci_dram_size, 1122 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 1123 1124 pci_set_region(&pcie->hose.regions[1], pcie->io.start, 1125 pcie->io.start, fdt_resource_size(&pcie->io), 1126 PCI_REGION_IO); 1127 1128 pci_set_region(&pcie->hose.regions[2], pcie->mem.start, 1129 pcie->mem.start, fdt_resource_size(&pcie->mem), 1130 PCI_REGION_MEM); 1131 1132 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, 1133 pcie->prefetch.start, 1134 fdt_resource_size(&pcie->prefetch), 1135 PCI_REGION_MEM | PCI_REGION_PREFETCH); 1136 1137 pcie->hose.region_count = 4; 1138 1139 pci_set_ops(&pcie->hose, 1140 pci_hose_read_config_byte_via_dword, 1141 pci_hose_read_config_word_via_dword, 1142 tegra_pcie_read_conf, 1143 pci_hose_write_config_byte_via_dword, 1144 pci_hose_write_config_word_via_dword, 1145 tegra_pcie_write_conf); 1146 1147 pci_register_hose(&pcie->hose); 1148 1149 #ifdef CONFIG_PCI_SCAN_SHOW 1150 printf("PCI: Enumerating devices...\n"); 1151 printf("---------------------------------------\n"); 1152 printf(" Device ID Description\n"); 1153 printf(" ------ -- -----------\n"); 1154 #endif 1155 1156 pcie->hose.last_busno = pci_hose_scan(&pcie->hose); 1157 } 1158 1159 return 0; 1160 } 1161 1162 void pci_init_board(void) 1163 { 1164 const void *fdt = gd->fdt_blob; 1165 int count, nodes[1]; 1166 1167 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1168 COMPAT_NVIDIA_TEGRA124_PCIE, 1169 nodes, ARRAY_SIZE(nodes)); 1170 if (process_nodes(fdt, nodes, count)) 1171 return; 1172 1173 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1174 COMPAT_NVIDIA_TEGRA30_PCIE, 1175 nodes, ARRAY_SIZE(nodes)); 1176 if (process_nodes(fdt, nodes, count)) 1177 return; 1178 1179 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1180 COMPAT_NVIDIA_TEGRA20_PCIE, 1181 nodes, ARRAY_SIZE(nodes)); 1182 if (process_nodes(fdt, nodes, count)) 1183 return; 1184 } 1185 1186 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 1187 { 1188 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) 1189 return 1; 1190 1191 return 0; 1192 } 1193