1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define pr_fmt(fmt) "tegra-pcie: " fmt 14 15 #include <common.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 #define RP_VEND_XP 0x00000F00 158 #define RP_VEND_XP_DL_UP (1 << 30) 159 160 #define RP_VEND_CTL2 0x00000FA8 161 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 162 163 #define RP_PRIV_MISC 0x00000FE0 164 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 165 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 166 167 #define RP_LINK_CONTROL_STATUS 0x00000090 168 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 169 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 170 171 enum tegra_pci_id { 172 TEGRA20_PCIE, 173 TEGRA30_PCIE, 174 TEGRA124_PCIE, 175 TEGRA210_PCIE, 176 }; 177 178 struct tegra_pcie_port { 179 struct tegra_pcie *pcie; 180 181 struct fdt_resource regs; 182 unsigned int num_lanes; 183 unsigned int index; 184 185 struct list_head list; 186 }; 187 188 struct tegra_pcie_soc { 189 unsigned int num_ports; 190 unsigned long pads_pll_ctl; 191 unsigned long tx_ref_sel; 192 u32 pads_refclk_cfg0; 193 u32 pads_refclk_cfg1; 194 bool has_pex_clkreq_en; 195 bool has_pex_bias_ctrl; 196 bool has_cml_clk; 197 bool has_gen2; 198 bool force_pca_enable; 199 }; 200 201 struct tegra_pcie { 202 struct pci_controller hose; 203 204 struct fdt_resource pads; 205 struct fdt_resource afi; 206 struct fdt_resource cs; 207 208 struct list_head ports; 209 unsigned long xbar; 210 211 const struct tegra_pcie_soc *soc; 212 struct tegra_xusb_phy *phy; 213 }; 214 215 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 216 unsigned long offset) 217 { 218 writel(value, pcie->afi.start + offset); 219 } 220 221 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 222 { 223 return readl(pcie->afi.start + offset); 224 } 225 226 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 227 unsigned long offset) 228 { 229 writel(value, pcie->pads.start + offset); 230 } 231 232 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 233 { 234 return readl(pcie->pads.start + offset); 235 } 236 237 static unsigned long rp_readl(struct tegra_pcie_port *port, 238 unsigned long offset) 239 { 240 return readl(port->regs.start + offset); 241 } 242 243 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 244 unsigned long offset) 245 { 246 writel(value, port->regs.start + offset); 247 } 248 249 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 250 { 251 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 252 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 253 (where & 0xfc); 254 } 255 256 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 257 int where, unsigned long *address) 258 { 259 unsigned int bus = PCI_BUS(bdf); 260 261 if (bus == 0) { 262 unsigned int dev = PCI_DEV(bdf); 263 struct tegra_pcie_port *port; 264 265 list_for_each_entry(port, &pcie->ports, list) { 266 if (port->index + 1 == dev) { 267 *address = port->regs.start + (where & ~3); 268 return 0; 269 } 270 } 271 return -EFAULT; 272 } else { 273 #ifdef CONFIG_TEGRA20 274 unsigned int dev = PCI_DEV(bdf); 275 if (dev != 0) 276 return -EFAULT; 277 #endif 278 279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 280 return 0; 281 } 282 } 283 284 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf, 285 uint offset, ulong *valuep, 286 enum pci_size_t size) 287 { 288 struct tegra_pcie *pcie = dev_get_priv(bus); 289 unsigned long address, value; 290 int err; 291 292 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 293 if (err < 0) { 294 value = 0xffffffff; 295 goto done; 296 } 297 298 value = readl(address); 299 300 #ifdef CONFIG_TEGRA20 301 /* fixup root port class */ 302 if (PCI_BUS(bdf) == 0) { 303 if ((offset & ~3) == PCI_CLASS_REVISION) { 304 value &= ~0x00ff0000; 305 value |= PCI_CLASS_BRIDGE_PCI << 16; 306 } 307 } 308 #endif 309 310 done: 311 *valuep = pci_conv_32_to_size(value, offset, size); 312 313 return 0; 314 } 315 316 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf, 317 uint offset, ulong value, 318 enum pci_size_t size) 319 { 320 struct tegra_pcie *pcie = dev_get_priv(bus); 321 unsigned long address; 322 ulong old; 323 int err; 324 325 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); 326 if (err < 0) 327 return 0; 328 329 old = readl(address); 330 value = pci_conv_size_to_32(old, value, offset, size); 331 writel(value, address); 332 333 return 0; 334 } 335 336 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 337 struct tegra_pcie_port *port) 338 { 339 const u32 *addr; 340 int len; 341 342 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 343 if (!addr) { 344 error("property \"assigned-addresses\" not found"); 345 return -FDT_ERR_NOTFOUND; 346 } 347 348 port->regs.start = fdt32_to_cpu(addr[2]); 349 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 350 351 return 0; 352 } 353 354 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 355 enum tegra_pci_id id, unsigned long *xbar) 356 { 357 switch (id) { 358 case TEGRA20_PCIE: 359 switch (lanes) { 360 case 0x00000004: 361 debug("single-mode configuration\n"); 362 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 363 return 0; 364 365 case 0x00000202: 366 debug("dual-mode configuration\n"); 367 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 368 return 0; 369 } 370 break; 371 case TEGRA30_PCIE: 372 switch (lanes) { 373 case 0x00000204: 374 debug("4x1, 2x1 configuration\n"); 375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 376 return 0; 377 378 case 0x00020202: 379 debug("2x3 configuration\n"); 380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 381 return 0; 382 383 case 0x00010104: 384 debug("4x1, 1x2 configuration\n"); 385 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 386 return 0; 387 } 388 break; 389 case TEGRA124_PCIE: 390 case TEGRA210_PCIE: 391 switch (lanes) { 392 case 0x0000104: 393 debug("4x1, 1x1 configuration\n"); 394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 395 return 0; 396 397 case 0x0000102: 398 debug("2x1, 1x1 configuration\n"); 399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 400 return 0; 401 } 402 break; 403 default: 404 break; 405 } 406 407 return -FDT_ERR_NOTFOUND; 408 } 409 410 static int tegra_pcie_parse_port_info(const void *fdt, int node, 411 unsigned int *index, 412 unsigned int *lanes) 413 { 414 struct fdt_pci_addr addr; 415 int err; 416 417 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 418 if (err < 0) { 419 error("failed to parse \"nvidia,num-lanes\" property"); 420 return err; 421 } 422 423 *lanes = err; 424 425 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); 426 if (err < 0) { 427 error("failed to parse \"reg\" property"); 428 return err; 429 } 430 431 *index = PCI_DEV(addr.phys_hi) - 1; 432 433 return 0; 434 } 435 436 int __weak tegra_pcie_board_init(void) 437 { 438 return 0; 439 } 440 441 static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, 442 struct tegra_pcie *pcie) 443 { 444 int err, subnode; 445 u32 lanes = 0; 446 447 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 448 &pcie->pads); 449 if (err < 0) { 450 error("resource \"pads\" not found"); 451 return err; 452 } 453 454 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 455 &pcie->afi); 456 if (err < 0) { 457 error("resource \"afi\" not found"); 458 return err; 459 } 460 461 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 462 &pcie->cs); 463 if (err < 0) { 464 error("resource \"cs\" not found"); 465 return err; 466 } 467 468 err = tegra_pcie_board_init(); 469 if (err < 0) { 470 error("tegra_pcie_board_init() failed: err=%d", err); 471 return err; 472 } 473 474 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 475 if (pcie->phy) { 476 err = tegra_xusb_phy_prepare(pcie->phy); 477 if (err < 0) { 478 error("failed to prepare PHY: %d", err); 479 return err; 480 } 481 } 482 483 fdt_for_each_subnode(fdt, subnode, node) { 484 unsigned int index = 0, num_lanes = 0; 485 struct tegra_pcie_port *port; 486 487 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 488 &num_lanes); 489 if (err < 0) { 490 error("failed to obtain root port info"); 491 continue; 492 } 493 494 lanes |= num_lanes << (index << 3); 495 496 if (!fdtdec_get_is_enabled(fdt, subnode)) 497 continue; 498 499 port = malloc(sizeof(*port)); 500 if (!port) 501 continue; 502 503 memset(port, 0, sizeof(*port)); 504 port->num_lanes = num_lanes; 505 port->index = index; 506 507 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 508 if (err < 0) { 509 free(port); 510 continue; 511 } 512 513 list_add_tail(&port->list, &pcie->ports); 514 port->pcie = pcie; 515 } 516 517 err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar); 518 if (err < 0) { 519 error("invalid lane configuration"); 520 return err; 521 } 522 523 return 0; 524 } 525 526 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 527 { 528 const struct tegra_pcie_soc *soc = pcie->soc; 529 unsigned long value; 530 int err; 531 532 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 533 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 534 reset_set_enable(PERIPH_ID_AFI, 1); 535 reset_set_enable(PERIPH_ID_PCIE, 1); 536 537 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 538 if (err < 0) { 539 error("failed to power off PCIe partition: %d", err); 540 return err; 541 } 542 543 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 544 PERIPH_ID_PCIE); 545 if (err < 0) { 546 error("failed to power up PCIe partition: %d", err); 547 return err; 548 } 549 550 /* take AFI controller out of reset */ 551 reset_set_enable(PERIPH_ID_AFI, 0); 552 553 /* enable AFI clock */ 554 clock_enable(PERIPH_ID_AFI); 555 556 if (soc->has_cml_clk) { 557 /* enable CML clock */ 558 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 559 value |= (1 << 0); 560 value &= ~(1 << 1); 561 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 562 } 563 564 err = tegra_plle_enable(); 565 if (err < 0) { 566 error("failed to enable PLLE: %d\n", err); 567 return err; 568 } 569 570 return 0; 571 } 572 573 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 574 { 575 const struct tegra_pcie_soc *soc = pcie->soc; 576 unsigned long start = get_timer(0); 577 u32 value; 578 579 while (get_timer(start) < timeout) { 580 value = pads_readl(pcie, soc->pads_pll_ctl); 581 if (value & PADS_PLL_CTL_LOCKDET) 582 return 0; 583 } 584 585 return -ETIMEDOUT; 586 } 587 588 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 589 { 590 const struct tegra_pcie_soc *soc = pcie->soc; 591 u32 value; 592 int err; 593 594 /* initialize internal PHY, enable up to 16 PCIe lanes */ 595 pads_writel(pcie, 0, PADS_CTL_SEL); 596 597 /* override IDDQ to 1 on all 4 lanes */ 598 value = pads_readl(pcie, PADS_CTL); 599 value |= PADS_CTL_IDDQ_1L; 600 pads_writel(pcie, value, PADS_CTL); 601 602 /* 603 * Set up PHY PLL inputs select PLLE output as refclock, set TX 604 * ref sel to div10 (not div5). 605 */ 606 value = pads_readl(pcie, soc->pads_pll_ctl); 607 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 608 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 609 pads_writel(pcie, value, soc->pads_pll_ctl); 610 611 /* reset PLL */ 612 value = pads_readl(pcie, soc->pads_pll_ctl); 613 value &= ~PADS_PLL_CTL_RST_B4SM; 614 pads_writel(pcie, value, soc->pads_pll_ctl); 615 616 udelay(20); 617 618 /* take PLL out of reset */ 619 value = pads_readl(pcie, soc->pads_pll_ctl); 620 value |= PADS_PLL_CTL_RST_B4SM; 621 pads_writel(pcie, value, soc->pads_pll_ctl); 622 623 /* configure the reference clock driver */ 624 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); 625 if (soc->num_ports > 2) 626 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); 627 628 /* wait for the PLL to lock */ 629 err = tegra_pcie_pll_wait(pcie, 500); 630 if (err < 0) { 631 error("PLL failed to lock: %d", err); 632 return err; 633 } 634 635 /* turn off IDDQ override */ 636 value = pads_readl(pcie, PADS_CTL); 637 value &= ~PADS_CTL_IDDQ_1L; 638 pads_writel(pcie, value, PADS_CTL); 639 640 /* enable TX/RX data */ 641 value = pads_readl(pcie, PADS_CTL); 642 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 643 pads_writel(pcie, value, PADS_CTL); 644 645 return 0; 646 } 647 648 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 649 { 650 const struct tegra_pcie_soc *soc = pcie->soc; 651 struct tegra_pcie_port *port; 652 u32 value; 653 int err; 654 655 if (pcie->phy) { 656 value = afi_readl(pcie, AFI_PLLE_CONTROL); 657 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 658 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 659 afi_writel(pcie, value, AFI_PLLE_CONTROL); 660 } 661 662 if (soc->has_pex_bias_ctrl) 663 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 664 665 value = afi_readl(pcie, AFI_PCIE_CONFIG); 666 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 667 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 668 669 list_for_each_entry(port, &pcie->ports, list) 670 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 671 672 afi_writel(pcie, value, AFI_PCIE_CONFIG); 673 674 value = afi_readl(pcie, AFI_FUSE); 675 676 if (soc->has_gen2) 677 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 678 else 679 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 680 681 afi_writel(pcie, value, AFI_FUSE); 682 683 if (pcie->phy) 684 err = tegra_xusb_phy_enable(pcie->phy); 685 else 686 err = tegra_pcie_phy_enable(pcie); 687 688 if (err < 0) { 689 error("failed to power on PHY: %d\n", err); 690 return err; 691 } 692 693 /* take the PCIEXCLK logic out of reset */ 694 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 695 696 /* finally enable PCIe */ 697 value = afi_readl(pcie, AFI_CONFIGURATION); 698 value |= AFI_CONFIGURATION_EN_FPCI; 699 afi_writel(pcie, value, AFI_CONFIGURATION); 700 701 /* disable all interrupts */ 702 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 703 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 704 afi_writel(pcie, 0, AFI_INTR_MASK); 705 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 706 707 return 0; 708 } 709 710 static int tegra_pcie_setup_translations(struct udevice *bus) 711 { 712 struct tegra_pcie *pcie = dev_get_priv(bus); 713 unsigned long fpci, axi, size; 714 struct pci_region *io, *mem, *pref; 715 int count; 716 717 /* BAR 0: type 1 extended configuration space */ 718 fpci = 0xfe100000; 719 size = fdt_resource_size(&pcie->cs); 720 axi = pcie->cs.start; 721 722 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 723 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 724 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 725 726 count = pci_get_regions(bus, &io, &mem, &pref); 727 if (count != 3) 728 return -EINVAL; 729 730 /* BAR 1: downstream I/O */ 731 fpci = 0xfdfc0000; 732 size = io->size; 733 axi = io->phys_start; 734 735 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 736 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 737 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 738 739 /* BAR 2: prefetchable memory */ 740 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 741 size = pref->size; 742 axi = pref->phys_start; 743 744 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 745 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 746 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 747 748 /* BAR 3: non-prefetchable memory */ 749 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1; 750 size = mem->size; 751 axi = mem->phys_start; 752 753 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 754 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 755 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 756 757 /* NULL out the remaining BARs as they are not used */ 758 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 759 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 760 afi_writel(pcie, 0, AFI_FPCI_BAR4); 761 762 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 763 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 764 afi_writel(pcie, 0, AFI_FPCI_BAR5); 765 766 /* map all upstream transactions as uncached */ 767 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 768 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 769 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 770 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 771 772 /* MSI translations are setup only when needed */ 773 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 774 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 775 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 776 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 777 778 return 0; 779 } 780 781 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 782 { 783 unsigned long ret = 0; 784 785 switch (port->index) { 786 case 0: 787 ret = AFI_PEX0_CTRL; 788 break; 789 790 case 1: 791 ret = AFI_PEX1_CTRL; 792 break; 793 794 case 2: 795 ret = AFI_PEX2_CTRL; 796 break; 797 } 798 799 return ret; 800 } 801 802 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 803 { 804 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 805 unsigned long value; 806 807 /* pulse reset signel */ 808 value = afi_readl(port->pcie, ctrl); 809 value &= ~AFI_PEX_CTRL_RST; 810 afi_writel(port->pcie, value, ctrl); 811 812 udelay(2000); 813 814 value = afi_readl(port->pcie, ctrl); 815 value |= AFI_PEX_CTRL_RST; 816 afi_writel(port->pcie, value, ctrl); 817 } 818 819 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 820 { 821 const struct tegra_pcie_soc *soc = port->pcie->soc; 822 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 823 unsigned long value; 824 825 /* enable reference clock */ 826 value = afi_readl(port->pcie, ctrl); 827 value |= AFI_PEX_CTRL_REFCLK_EN; 828 829 if (port->pcie->soc->has_pex_clkreq_en) 830 value |= AFI_PEX_CTRL_CLKREQ_EN; 831 832 value |= AFI_PEX_CTRL_OVERRIDE_EN; 833 834 afi_writel(port->pcie, value, ctrl); 835 836 tegra_pcie_port_reset(port); 837 838 if (soc->force_pca_enable) { 839 value = rp_readl(port, RP_VEND_CTL2); 840 value |= RP_VEND_CTL2_PCA_ENABLE; 841 rp_writel(port, value, RP_VEND_CTL2); 842 } 843 } 844 845 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 846 { 847 unsigned int retries = 3; 848 unsigned long value; 849 850 value = rp_readl(port, RP_PRIV_MISC); 851 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 852 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 853 rp_writel(port, value, RP_PRIV_MISC); 854 855 do { 856 unsigned int timeout = 200; 857 858 do { 859 value = rp_readl(port, RP_VEND_XP); 860 if (value & RP_VEND_XP_DL_UP) 861 break; 862 863 udelay(2000); 864 } while (--timeout); 865 866 if (!timeout) { 867 debug("link %u down, retrying\n", port->index); 868 goto retry; 869 } 870 871 timeout = 200; 872 873 do { 874 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 875 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 876 return true; 877 878 udelay(2000); 879 } while (--timeout); 880 881 retry: 882 tegra_pcie_port_reset(port); 883 } while (--retries); 884 885 return false; 886 } 887 888 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 889 { 890 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 891 unsigned long value; 892 893 /* assert port reset */ 894 value = afi_readl(port->pcie, ctrl); 895 value &= ~AFI_PEX_CTRL_RST; 896 afi_writel(port->pcie, value, ctrl); 897 898 /* disable reference clock */ 899 value = afi_readl(port->pcie, ctrl); 900 value &= ~AFI_PEX_CTRL_REFCLK_EN; 901 afi_writel(port->pcie, value, ctrl); 902 } 903 904 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 905 { 906 list_del(&port->list); 907 free(port); 908 } 909 910 static int tegra_pcie_enable(struct tegra_pcie *pcie) 911 { 912 struct tegra_pcie_port *port, *tmp; 913 914 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 915 debug("probing port %u, using %u lanes\n", port->index, 916 port->num_lanes); 917 918 tegra_pcie_port_enable(port); 919 920 if (tegra_pcie_port_check_link(port)) 921 continue; 922 923 debug("link %u down, ignoring\n", port->index); 924 925 tegra_pcie_port_disable(port); 926 tegra_pcie_port_free(port); 927 } 928 929 return 0; 930 } 931 932 static const struct tegra_pcie_soc pci_tegra_soc[] = { 933 [TEGRA20_PCIE] = { 934 .num_ports = 2, 935 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 936 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 937 .pads_refclk_cfg0 = 0xfa5cfa5c, 938 .has_pex_clkreq_en = false, 939 .has_pex_bias_ctrl = false, 940 .has_cml_clk = false, 941 .has_gen2 = false, 942 }, 943 [TEGRA30_PCIE] = { 944 .num_ports = 3, 945 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 946 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 947 .pads_refclk_cfg0 = 0xfa5cfa5c, 948 .pads_refclk_cfg1 = 0xfa5cfa5c, 949 .has_pex_clkreq_en = true, 950 .has_pex_bias_ctrl = true, 951 .has_cml_clk = true, 952 .has_gen2 = false, 953 }, 954 [TEGRA124_PCIE] = { 955 .num_ports = 2, 956 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 957 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 958 .pads_refclk_cfg0 = 0x44ac44ac, 959 .has_pex_clkreq_en = true, 960 .has_pex_bias_ctrl = true, 961 .has_cml_clk = true, 962 .has_gen2 = true, 963 }, 964 [TEGRA210_PCIE] = { 965 .num_ports = 2, 966 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 967 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 968 .pads_refclk_cfg0 = 0x90b890b8, 969 .has_pex_clkreq_en = true, 970 .has_pex_bias_ctrl = true, 971 .has_cml_clk = true, 972 .has_gen2 = true, 973 .force_pca_enable = true, 974 } 975 }; 976 977 static int pci_tegra_ofdata_to_platdata(struct udevice *dev) 978 { 979 struct tegra_pcie *pcie = dev_get_priv(dev); 980 enum tegra_pci_id id; 981 982 id = dev_get_driver_data(dev); 983 pcie->soc = &pci_tegra_soc[id]; 984 985 INIT_LIST_HEAD(&pcie->ports); 986 987 if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie)) 988 return -EINVAL; 989 990 return 0; 991 } 992 993 static int pci_tegra_probe(struct udevice *dev) 994 { 995 struct tegra_pcie *pcie = dev_get_priv(dev); 996 int err; 997 998 err = tegra_pcie_power_on(pcie); 999 if (err < 0) { 1000 error("failed to power on"); 1001 return err; 1002 } 1003 1004 err = tegra_pcie_enable_controller(pcie); 1005 if (err < 0) { 1006 error("failed to enable controller"); 1007 return err; 1008 } 1009 1010 err = tegra_pcie_setup_translations(dev); 1011 if (err < 0) { 1012 error("failed to decode ranges"); 1013 return err; 1014 } 1015 1016 err = tegra_pcie_enable(pcie); 1017 if (err < 0) { 1018 error("failed to enable PCIe"); 1019 return err; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static const struct dm_pci_ops pci_tegra_ops = { 1026 .read_config = pci_tegra_read_config, 1027 .write_config = pci_tegra_write_config, 1028 }; 1029 1030 static const struct udevice_id pci_tegra_ids[] = { 1031 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE }, 1032 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, 1033 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, 1034 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, 1035 { } 1036 }; 1037 1038 U_BOOT_DRIVER(pci_tegra) = { 1039 .name = "pci_tegra", 1040 .id = UCLASS_PCI, 1041 .of_match = pci_tegra_ids, 1042 .ops = &pci_tegra_ops, 1043 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata, 1044 .probe = pci_tegra_probe, 1045 .priv_auto_alloc_size = sizeof(struct tegra_pcie), 1046 }; 1047