1 /* 2 * Copyright (c) 2010, CompuLab, Ltd. 3 * Author: Mike Rapoport <mike@compulab.co.il> 4 * 5 * Based on NVIDIA PCIe driver 6 * Copyright (c) 2008-2009, NVIDIA Corporation. 7 * 8 * Copyright (c) 2013-2014, NVIDIA Corporation. 9 * 10 * SPDX-License-Identifier: GPL-2.0 11 */ 12 13 #define DEBUG 14 #define pr_fmt(fmt) "tegra-pcie: " fmt 15 16 #include <common.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <malloc.h> 20 #include <pci.h> 21 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include <asm/arch/clock.h> 26 #include <asm/arch/powergate.h> 27 #include <asm/arch-tegra/xusb-padctl.h> 28 29 #include <linux/list.h> 30 31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define AFI_AXI_BAR0_SZ 0x00 36 #define AFI_AXI_BAR1_SZ 0x04 37 #define AFI_AXI_BAR2_SZ 0x08 38 #define AFI_AXI_BAR3_SZ 0x0c 39 #define AFI_AXI_BAR4_SZ 0x10 40 #define AFI_AXI_BAR5_SZ 0x14 41 42 #define AFI_AXI_BAR0_START 0x18 43 #define AFI_AXI_BAR1_START 0x1c 44 #define AFI_AXI_BAR2_START 0x20 45 #define AFI_AXI_BAR3_START 0x24 46 #define AFI_AXI_BAR4_START 0x28 47 #define AFI_AXI_BAR5_START 0x2c 48 49 #define AFI_FPCI_BAR0 0x30 50 #define AFI_FPCI_BAR1 0x34 51 #define AFI_FPCI_BAR2 0x38 52 #define AFI_FPCI_BAR3 0x3c 53 #define AFI_FPCI_BAR4 0x40 54 #define AFI_FPCI_BAR5 0x44 55 56 #define AFI_CACHE_BAR0_SZ 0x48 57 #define AFI_CACHE_BAR0_ST 0x4c 58 #define AFI_CACHE_BAR1_SZ 0x50 59 #define AFI_CACHE_BAR1_ST 0x54 60 61 #define AFI_MSI_BAR_SZ 0x60 62 #define AFI_MSI_FPCI_BAR_ST 0x64 63 #define AFI_MSI_AXI_BAR_ST 0x68 64 65 #define AFI_CONFIGURATION 0xac 66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 67 68 #define AFI_FPCI_ERROR_MASKS 0xb0 69 70 #define AFI_INTR_MASK 0xb4 71 #define AFI_INTR_MASK_INT_MASK (1 << 0) 72 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 73 74 #define AFI_SM_INTR_ENABLE 0xc4 75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 83 84 #define AFI_AFI_INTR_ENABLE 0xc8 85 #define AFI_INTR_EN_INI_SLVERR (1 << 0) 86 #define AFI_INTR_EN_INI_DECERR (1 << 1) 87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2) 88 #define AFI_INTR_EN_TGT_DECERR (1 << 3) 89 #define AFI_INTR_EN_TGT_WRERR (1 << 4) 90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) 91 #define AFI_INTR_EN_AXI_DECERR (1 << 6) 92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) 93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) 94 95 #define AFI_PCIE_CONFIG 0x0f8 96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe 98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) 100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) 101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) 102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) 103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) 104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) 105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) 106 107 #define AFI_FUSE 0x104 108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 109 110 #define AFI_PEX0_CTRL 0x110 111 #define AFI_PEX1_CTRL 0x118 112 #define AFI_PEX2_CTRL 0x128 113 #define AFI_PEX_CTRL_RST (1 << 0) 114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 117 118 #define AFI_PLLE_CONTROL 0x160 119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 121 122 #define AFI_PEXBIAS_CTRL_0 0x168 123 124 #define PADS_CTL_SEL 0x0000009C 125 126 #define PADS_CTL 0x000000A0 127 #define PADS_CTL_IDDQ_1L (1 << 0) 128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6) 129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10) 130 131 #define PADS_PLL_CTL_TEGRA20 0x000000B8 132 #define PADS_PLL_CTL_TEGRA30 0x000000B4 133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) 134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8) 135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) 136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) 137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) 138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) 139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) 140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) 141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) 142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) 143 144 #define PADS_REFCLK_CFG0 0x000000C8 145 #define PADS_REFCLK_CFG1 0x000000CC 146 147 /* 148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit 149 * entries, one entry per PCIe port. These field definitions and desired 150 * values aren't in the TRM, but do come from NVIDIA. 151 */ 152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ 153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ 155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ 156 157 /* Default value provided by HW engineering is 0xfa5c */ 158 #define PADS_REFCLK_CFG_VALUE \ 159 ( \ 160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ 161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ 162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ 163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ 164 ) 165 166 #define RP_VEND_XP 0x00000F00 167 #define RP_VEND_XP_DL_UP (1 << 30) 168 169 #define RP_PRIV_MISC 0x00000FE0 170 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 171 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 172 173 #define RP_LINK_CONTROL_STATUS 0x00000090 174 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 175 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 176 177 struct tegra_pcie; 178 179 struct tegra_pcie_port { 180 struct tegra_pcie *pcie; 181 182 struct fdt_resource regs; 183 unsigned int num_lanes; 184 unsigned int index; 185 186 struct list_head list; 187 }; 188 189 struct tegra_pcie_soc { 190 unsigned int num_ports; 191 unsigned long pads_pll_ctl; 192 unsigned long tx_ref_sel; 193 bool has_pex_clkreq_en; 194 bool has_pex_bias_ctrl; 195 bool has_cml_clk; 196 bool has_gen2; 197 }; 198 199 struct tegra_pcie { 200 struct pci_controller hose; 201 202 struct fdt_resource pads; 203 struct fdt_resource afi; 204 struct fdt_resource cs; 205 206 struct fdt_resource prefetch; 207 struct fdt_resource mem; 208 struct fdt_resource io; 209 210 struct list_head ports; 211 unsigned long xbar; 212 213 const struct tegra_pcie_soc *soc; 214 struct tegra_xusb_phy *phy; 215 }; 216 217 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) 218 { 219 return container_of(hose, struct tegra_pcie, hose); 220 } 221 222 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, 223 unsigned long offset) 224 { 225 writel(value, pcie->afi.start + offset); 226 } 227 228 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) 229 { 230 return readl(pcie->afi.start + offset); 231 } 232 233 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, 234 unsigned long offset) 235 { 236 writel(value, pcie->pads.start + offset); 237 } 238 239 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) 240 { 241 return readl(pcie->pads.start + offset); 242 } 243 244 static unsigned long rp_readl(struct tegra_pcie_port *port, 245 unsigned long offset) 246 { 247 return readl(port->regs.start + offset); 248 } 249 250 static void rp_writel(struct tegra_pcie_port *port, unsigned long value, 251 unsigned long offset) 252 { 253 writel(value, port->regs.start + offset); 254 } 255 256 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) 257 { 258 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | 259 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | 260 (where & 0xfc); 261 } 262 263 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, 264 int where, unsigned long *address) 265 { 266 unsigned int bus = PCI_BUS(bdf); 267 268 if (bus == 0) { 269 unsigned int dev = PCI_DEV(bdf); 270 struct tegra_pcie_port *port; 271 272 list_for_each_entry(port, &pcie->ports, list) { 273 if (port->index + 1 == dev) { 274 *address = port->regs.start + (where & ~3); 275 return 0; 276 } 277 } 278 } else { 279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); 280 return 0; 281 } 282 283 return -1; 284 } 285 286 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, 287 int where, u32 *value) 288 { 289 struct tegra_pcie *pcie = to_tegra_pcie(hose); 290 unsigned long address; 291 int err; 292 293 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 294 if (err < 0) { 295 *value = 0xffffffff; 296 return 1; 297 } 298 299 *value = readl(address); 300 301 /* fixup root port class */ 302 if (PCI_BUS(bdf) == 0) { 303 if (where == PCI_CLASS_REVISION) { 304 *value &= ~0x00ff0000; 305 *value |= PCI_CLASS_BRIDGE_PCI << 16; 306 } 307 } 308 309 return 0; 310 } 311 312 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, 313 int where, u32 value) 314 { 315 struct tegra_pcie *pcie = to_tegra_pcie(hose); 316 unsigned long address; 317 int err; 318 319 err = tegra_pcie_conf_address(pcie, bdf, where, &address); 320 if (err < 0) 321 return 1; 322 323 writel(value, address); 324 325 return 0; 326 } 327 328 static int tegra_pcie_port_parse_dt(const void *fdt, int node, 329 struct tegra_pcie_port *port) 330 { 331 const u32 *addr; 332 int len; 333 334 addr = fdt_getprop(fdt, node, "assigned-addresses", &len); 335 if (!addr) { 336 error("property \"assigned-addresses\" not found"); 337 return -FDT_ERR_NOTFOUND; 338 } 339 340 port->regs.start = fdt32_to_cpu(addr[2]); 341 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); 342 343 return 0; 344 } 345 346 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, 347 unsigned long *xbar) 348 { 349 enum fdt_compat_id id = fdtdec_lookup(fdt, node); 350 351 switch (id) { 352 case COMPAT_NVIDIA_TEGRA20_PCIE: 353 switch (lanes) { 354 case 0x00000004: 355 debug("single-mode configuration\n"); 356 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; 357 return 0; 358 359 case 0x00000202: 360 debug("dual-mode configuration\n"); 361 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; 362 return 0; 363 } 364 break; 365 366 case COMPAT_NVIDIA_TEGRA30_PCIE: 367 switch (lanes) { 368 case 0x00000204: 369 debug("4x1, 2x1 configuration\n"); 370 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; 371 return 0; 372 373 case 0x00020202: 374 debug("2x3 configuration\n"); 375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; 376 return 0; 377 378 case 0x00010104: 379 debug("4x1, 1x2 configuration\n"); 380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; 381 return 0; 382 } 383 break; 384 385 case COMPAT_NVIDIA_TEGRA124_PCIE: 386 switch (lanes) { 387 case 0x0000104: 388 debug("4x1, 1x1 configuration\n"); 389 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; 390 return 0; 391 392 case 0x0000102: 393 debug("2x1, 1x1 configuration\n"); 394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; 395 return 0; 396 } 397 break; 398 399 default: 400 break; 401 } 402 403 return -FDT_ERR_NOTFOUND; 404 } 405 406 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, 407 struct tegra_pcie *pcie) 408 { 409 int parent, na_parent, na_pcie, ns_pcie; 410 const u32 *ptr, *end; 411 int len; 412 413 parent = fdt_parent_offset(fdt, node); 414 if (parent < 0) { 415 error("Can't find PCI parent node\n"); 416 return -FDT_ERR_NOTFOUND; 417 } 418 419 na_parent = fdt_address_cells(fdt, parent); 420 if (na_parent < 1) { 421 error("bad #address-cells for PCIE parent\n"); 422 return -FDT_ERR_NOTFOUND; 423 } 424 425 na_pcie = fdt_address_cells(fdt, node); 426 if (na_pcie < 1) { 427 error("bad #address-cells for PCIE\n"); 428 return -FDT_ERR_NOTFOUND; 429 } 430 431 ns_pcie = fdt_size_cells(fdt, node); 432 if (ns_pcie < 1) { 433 error("bad #size-cells for PCIE\n"); 434 return -FDT_ERR_NOTFOUND; 435 } 436 437 ptr = fdt_getprop(fdt, node, "ranges", &len); 438 if (!ptr) { 439 error("missing \"ranges\" property"); 440 return -FDT_ERR_NOTFOUND; 441 } 442 443 end = ptr + len / 4; 444 445 while (ptr < end) { 446 struct fdt_resource *res = NULL; 447 u32 space = fdt32_to_cpu(*ptr); 448 449 switch ((space >> 24) & 0x3) { 450 case 0x01: 451 res = &pcie->io; 452 break; 453 454 case 0x02: /* 32 bit */ 455 case 0x03: /* 64 bit */ 456 if (space & (1 << 30)) 457 res = &pcie->prefetch; 458 else 459 res = &pcie->mem; 460 461 break; 462 } 463 464 if (res) { 465 int start_low = na_pcie + (na_parent - 1); 466 int size_low = na_pcie + na_parent + (ns_pcie - 1); 467 res->start = fdt32_to_cpu(ptr[start_low]); 468 res->end = res->start + fdt32_to_cpu(ptr[size_low]); 469 } 470 471 ptr += na_pcie + na_parent + ns_pcie; 472 } 473 474 debug("PCI regions:\n"); 475 debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end); 476 debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start, 477 &pcie->mem.end); 478 debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start, 479 &pcie->prefetch.end); 480 481 return 0; 482 } 483 484 static int tegra_pcie_parse_port_info(const void *fdt, int node, 485 unsigned int *index, 486 unsigned int *lanes) 487 { 488 struct fdt_pci_addr addr; 489 int err; 490 491 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); 492 if (err < 0) { 493 error("failed to parse \"nvidia,num-lanes\" property"); 494 return err; 495 } 496 497 *lanes = err; 498 499 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); 500 if (err < 0) { 501 error("failed to parse \"reg\" property"); 502 return err; 503 } 504 505 *index = PCI_DEV(addr.phys_hi) - 1; 506 507 return 0; 508 } 509 510 static int tegra_pcie_parse_dt(const void *fdt, int node, 511 struct tegra_pcie *pcie) 512 { 513 int err, subnode; 514 u32 lanes = 0; 515 516 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", 517 &pcie->pads); 518 if (err < 0) { 519 error("resource \"pads\" not found"); 520 return err; 521 } 522 523 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", 524 &pcie->afi); 525 if (err < 0) { 526 error("resource \"afi\" not found"); 527 return err; 528 } 529 530 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", 531 &pcie->cs); 532 if (err < 0) { 533 error("resource \"cs\" not found"); 534 return err; 535 } 536 537 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); 538 if (pcie->phy) { 539 err = tegra_xusb_phy_prepare(pcie->phy); 540 if (err < 0) { 541 error("failed to prepare PHY: %d", err); 542 return err; 543 } 544 } 545 546 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); 547 if (err < 0) { 548 error("failed to parse \"ranges\" property"); 549 return err; 550 } 551 552 fdt_for_each_subnode(fdt, subnode, node) { 553 unsigned int index = 0, num_lanes = 0; 554 struct tegra_pcie_port *port; 555 556 err = tegra_pcie_parse_port_info(fdt, subnode, &index, 557 &num_lanes); 558 if (err < 0) { 559 error("failed to obtain root port info"); 560 continue; 561 } 562 563 lanes |= num_lanes << (index << 3); 564 565 if (!fdtdec_get_is_enabled(fdt, subnode)) 566 continue; 567 568 port = malloc(sizeof(*port)); 569 if (!port) 570 continue; 571 572 memset(port, 0, sizeof(*port)); 573 port->num_lanes = num_lanes; 574 port->index = index; 575 576 err = tegra_pcie_port_parse_dt(fdt, subnode, port); 577 if (err < 0) { 578 free(port); 579 continue; 580 } 581 582 list_add_tail(&port->list, &pcie->ports); 583 port->pcie = pcie; 584 } 585 586 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); 587 if (err < 0) { 588 error("invalid lane configuration"); 589 return err; 590 } 591 592 return 0; 593 } 594 595 int __weak tegra_pcie_board_init(void) 596 { 597 return 0; 598 } 599 600 static int tegra_pcie_power_on(struct tegra_pcie *pcie) 601 { 602 const struct tegra_pcie_soc *soc = pcie->soc; 603 unsigned long value; 604 int err; 605 606 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ 607 reset_set_enable(PERIPH_ID_PCIEXCLK, 1); 608 reset_set_enable(PERIPH_ID_AFI, 1); 609 reset_set_enable(PERIPH_ID_PCIE, 1); 610 611 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 612 if (err < 0) { 613 error("failed to power off PCIe partition: %d", err); 614 return err; 615 } 616 617 tegra_pcie_board_init(); 618 619 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 620 PERIPH_ID_PCIE); 621 if (err < 0) { 622 error("failed to power up PCIe partition: %d", err); 623 return err; 624 } 625 626 /* take AFI controller out of reset */ 627 reset_set_enable(PERIPH_ID_AFI, 0); 628 629 /* enable AFI clock */ 630 clock_enable(PERIPH_ID_AFI); 631 632 if (soc->has_cml_clk) { 633 /* enable CML clock */ 634 value = readl(NV_PA_CLK_RST_BASE + 0x48c); 635 value |= (1 << 0); 636 value &= ~(1 << 1); 637 writel(value, NV_PA_CLK_RST_BASE + 0x48c); 638 } 639 640 err = tegra_plle_enable(); 641 if (err < 0) { 642 error("failed to enable PLLE: %d\n", err); 643 return err; 644 } 645 646 return 0; 647 } 648 649 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) 650 { 651 const struct tegra_pcie_soc *soc = pcie->soc; 652 unsigned long start = get_timer(0); 653 u32 value; 654 655 while (get_timer(start) < timeout) { 656 value = pads_readl(pcie, soc->pads_pll_ctl); 657 if (value & PADS_PLL_CTL_LOCKDET) 658 return 0; 659 } 660 661 return -ETIMEDOUT; 662 } 663 664 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 665 { 666 const struct tegra_pcie_soc *soc = pcie->soc; 667 u32 value; 668 int err; 669 670 /* initialize internal PHY, enable up to 16 PCIe lanes */ 671 pads_writel(pcie, 0, PADS_CTL_SEL); 672 673 /* override IDDQ to 1 on all 4 lanes */ 674 value = pads_readl(pcie, PADS_CTL); 675 value |= PADS_CTL_IDDQ_1L; 676 pads_writel(pcie, value, PADS_CTL); 677 678 /* 679 * Set up PHY PLL inputs select PLLE output as refclock, set TX 680 * ref sel to div10 (not div5). 681 */ 682 value = pads_readl(pcie, soc->pads_pll_ctl); 683 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); 684 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; 685 pads_writel(pcie, value, soc->pads_pll_ctl); 686 687 /* reset PLL */ 688 value = pads_readl(pcie, soc->pads_pll_ctl); 689 value &= ~PADS_PLL_CTL_RST_B4SM; 690 pads_writel(pcie, value, soc->pads_pll_ctl); 691 692 udelay(20); 693 694 /* take PLL out of reset */ 695 value = pads_readl(pcie, soc->pads_pll_ctl); 696 value |= PADS_PLL_CTL_RST_B4SM; 697 pads_writel(pcie, value, soc->pads_pll_ctl); 698 699 /* configure the reference clock driver */ 700 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); 701 pads_writel(pcie, value, PADS_REFCLK_CFG0); 702 703 if (soc->num_ports > 2) 704 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); 705 706 /* wait for the PLL to lock */ 707 err = tegra_pcie_pll_wait(pcie, 500); 708 if (err < 0) { 709 error("PLL failed to lock: %d", err); 710 return err; 711 } 712 713 /* turn off IDDQ override */ 714 value = pads_readl(pcie, PADS_CTL); 715 value &= ~PADS_CTL_IDDQ_1L; 716 pads_writel(pcie, value, PADS_CTL); 717 718 /* enable TX/RX data */ 719 value = pads_readl(pcie, PADS_CTL); 720 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; 721 pads_writel(pcie, value, PADS_CTL); 722 723 return 0; 724 } 725 726 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) 727 { 728 const struct tegra_pcie_soc *soc = pcie->soc; 729 struct tegra_pcie_port *port; 730 u32 value; 731 int err; 732 733 if (pcie->phy) { 734 value = afi_readl(pcie, AFI_PLLE_CONTROL); 735 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 736 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 737 afi_writel(pcie, value, AFI_PLLE_CONTROL); 738 } 739 740 if (soc->has_pex_bias_ctrl) 741 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); 742 743 value = afi_readl(pcie, AFI_PCIE_CONFIG); 744 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 745 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; 746 747 list_for_each_entry(port, &pcie->ports, list) 748 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); 749 750 afi_writel(pcie, value, AFI_PCIE_CONFIG); 751 752 value = afi_readl(pcie, AFI_FUSE); 753 754 if (soc->has_gen2) 755 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 756 else 757 value |= AFI_FUSE_PCIE_T0_GEN2_DIS; 758 759 afi_writel(pcie, value, AFI_FUSE); 760 761 if (pcie->phy) 762 err = tegra_xusb_phy_enable(pcie->phy); 763 else 764 err = tegra_pcie_phy_enable(pcie); 765 766 if (err < 0) { 767 error("failed to power on PHY: %d\n", err); 768 return err; 769 } 770 771 /* take the PCIEXCLK logic out of reset */ 772 reset_set_enable(PERIPH_ID_PCIEXCLK, 0); 773 774 /* finally enable PCIe */ 775 value = afi_readl(pcie, AFI_CONFIGURATION); 776 value |= AFI_CONFIGURATION_EN_FPCI; 777 afi_writel(pcie, value, AFI_CONFIGURATION); 778 779 /* disable all interrupts */ 780 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); 781 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); 782 afi_writel(pcie, 0, AFI_INTR_MASK); 783 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); 784 785 return 0; 786 } 787 788 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) 789 { 790 unsigned long fpci, axi, size; 791 792 /* BAR 0: type 1 extended configuration space */ 793 fpci = 0xfe100000; 794 size = fdt_resource_size(&pcie->cs); 795 axi = pcie->cs.start; 796 797 afi_writel(pcie, axi, AFI_AXI_BAR0_START); 798 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); 799 afi_writel(pcie, fpci, AFI_FPCI_BAR0); 800 801 /* BAR 1: downstream I/O */ 802 fpci = 0xfdfc0000; 803 size = fdt_resource_size(&pcie->io); 804 axi = pcie->io.start; 805 806 afi_writel(pcie, axi, AFI_AXI_BAR1_START); 807 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); 808 afi_writel(pcie, fpci, AFI_FPCI_BAR1); 809 810 /* BAR 2: prefetchable memory */ 811 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; 812 size = fdt_resource_size(&pcie->prefetch); 813 axi = pcie->prefetch.start; 814 815 afi_writel(pcie, axi, AFI_AXI_BAR2_START); 816 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); 817 afi_writel(pcie, fpci, AFI_FPCI_BAR2); 818 819 /* BAR 3: non-prefetchable memory */ 820 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; 821 size = fdt_resource_size(&pcie->mem); 822 axi = pcie->mem.start; 823 824 afi_writel(pcie, axi, AFI_AXI_BAR3_START); 825 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); 826 afi_writel(pcie, fpci, AFI_FPCI_BAR3); 827 828 /* NULL out the remaining BARs as they are not used */ 829 afi_writel(pcie, 0, AFI_AXI_BAR4_START); 830 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); 831 afi_writel(pcie, 0, AFI_FPCI_BAR4); 832 833 afi_writel(pcie, 0, AFI_AXI_BAR5_START); 834 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); 835 afi_writel(pcie, 0, AFI_FPCI_BAR5); 836 837 /* map all upstream transactions as uncached */ 838 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); 839 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); 840 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); 841 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); 842 843 /* MSI translations are setup only when needed */ 844 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); 845 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 846 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); 847 afi_writel(pcie, 0, AFI_MSI_BAR_SZ); 848 } 849 850 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) 851 { 852 unsigned long ret = 0; 853 854 switch (port->index) { 855 case 0: 856 ret = AFI_PEX0_CTRL; 857 break; 858 859 case 1: 860 ret = AFI_PEX1_CTRL; 861 break; 862 863 case 2: 864 ret = AFI_PEX2_CTRL; 865 break; 866 } 867 868 return ret; 869 } 870 871 static void tegra_pcie_port_reset(struct tegra_pcie_port *port) 872 { 873 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 874 unsigned long value; 875 876 /* pulse reset signel */ 877 value = afi_readl(port->pcie, ctrl); 878 value &= ~AFI_PEX_CTRL_RST; 879 afi_writel(port->pcie, value, ctrl); 880 881 udelay(2000); 882 883 value = afi_readl(port->pcie, ctrl); 884 value |= AFI_PEX_CTRL_RST; 885 afi_writel(port->pcie, value, ctrl); 886 } 887 888 static void tegra_pcie_port_enable(struct tegra_pcie_port *port) 889 { 890 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 891 unsigned long value; 892 893 /* enable reference clock */ 894 value = afi_readl(port->pcie, ctrl); 895 value |= AFI_PEX_CTRL_REFCLK_EN; 896 897 if (port->pcie->soc->has_pex_clkreq_en) 898 value |= AFI_PEX_CTRL_CLKREQ_EN; 899 900 value |= AFI_PEX_CTRL_OVERRIDE_EN; 901 902 afi_writel(port->pcie, value, ctrl); 903 904 tegra_pcie_port_reset(port); 905 } 906 907 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) 908 { 909 unsigned int retries = 3; 910 unsigned long value; 911 912 value = rp_readl(port, RP_PRIV_MISC); 913 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 914 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 915 rp_writel(port, value, RP_PRIV_MISC); 916 917 do { 918 unsigned int timeout = 200; 919 920 do { 921 value = rp_readl(port, RP_VEND_XP); 922 if (value & RP_VEND_XP_DL_UP) 923 break; 924 925 udelay(2000); 926 } while (--timeout); 927 928 if (!timeout) { 929 debug("link %u down, retrying\n", port->index); 930 goto retry; 931 } 932 933 timeout = 200; 934 935 do { 936 value = rp_readl(port, RP_LINK_CONTROL_STATUS); 937 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 938 return true; 939 940 udelay(2000); 941 } while (--timeout); 942 943 retry: 944 tegra_pcie_port_reset(port); 945 } while (--retries); 946 947 return false; 948 } 949 950 static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 951 { 952 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); 953 unsigned long value; 954 955 /* assert port reset */ 956 value = afi_readl(port->pcie, ctrl); 957 value &= ~AFI_PEX_CTRL_RST; 958 afi_writel(port->pcie, value, ctrl); 959 960 /* disable reference clock */ 961 value = afi_readl(port->pcie, ctrl); 962 value &= ~AFI_PEX_CTRL_REFCLK_EN; 963 afi_writel(port->pcie, value, ctrl); 964 } 965 966 static void tegra_pcie_port_free(struct tegra_pcie_port *port) 967 { 968 list_del(&port->list); 969 free(port); 970 } 971 972 static int tegra_pcie_enable(struct tegra_pcie *pcie) 973 { 974 struct tegra_pcie_port *port, *tmp; 975 976 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 977 debug("probing port %u, using %u lanes\n", port->index, 978 port->num_lanes); 979 980 tegra_pcie_port_enable(port); 981 982 if (tegra_pcie_port_check_link(port)) 983 continue; 984 985 debug("link %u down, ignoring\n", port->index); 986 987 tegra_pcie_port_disable(port); 988 tegra_pcie_port_free(port); 989 } 990 991 return 0; 992 } 993 994 static const struct tegra_pcie_soc tegra20_pcie_soc = { 995 .num_ports = 2, 996 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, 997 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, 998 .has_pex_clkreq_en = false, 999 .has_pex_bias_ctrl = false, 1000 .has_cml_clk = false, 1001 .has_gen2 = false, 1002 }; 1003 1004 static const struct tegra_pcie_soc tegra30_pcie_soc = { 1005 .num_ports = 3, 1006 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1007 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1008 .has_pex_clkreq_en = true, 1009 .has_pex_bias_ctrl = true, 1010 .has_cml_clk = true, 1011 .has_gen2 = false, 1012 }; 1013 1014 static const struct tegra_pcie_soc tegra124_pcie_soc = { 1015 .num_ports = 2, 1016 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, 1017 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, 1018 .has_pex_clkreq_en = true, 1019 .has_pex_bias_ctrl = true, 1020 .has_cml_clk = true, 1021 .has_gen2 = true, 1022 }; 1023 1024 static int process_nodes(const void *fdt, int nodes[], unsigned int count) 1025 { 1026 unsigned int i; 1027 uint64_t dram_end; 1028 uint32_t pci_dram_size; 1029 1030 /* Clip PCI-accessible DRAM to 32-bits */ 1031 dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size; 1032 if (dram_end > 0x100000000) 1033 dram_end = 0x100000000; 1034 pci_dram_size = dram_end - NV_PA_SDRAM_BASE; 1035 1036 for (i = 0; i < count; i++) { 1037 const struct tegra_pcie_soc *soc; 1038 struct tegra_pcie *pcie; 1039 enum fdt_compat_id id; 1040 int err; 1041 1042 if (!fdtdec_get_is_enabled(fdt, nodes[i])) 1043 continue; 1044 1045 id = fdtdec_lookup(fdt, nodes[i]); 1046 switch (id) { 1047 case COMPAT_NVIDIA_TEGRA20_PCIE: 1048 soc = &tegra20_pcie_soc; 1049 break; 1050 1051 case COMPAT_NVIDIA_TEGRA30_PCIE: 1052 soc = &tegra30_pcie_soc; 1053 break; 1054 1055 case COMPAT_NVIDIA_TEGRA124_PCIE: 1056 soc = &tegra124_pcie_soc; 1057 break; 1058 1059 default: 1060 error("unsupported compatible: %s", 1061 fdtdec_get_compatible(id)); 1062 continue; 1063 } 1064 1065 pcie = malloc(sizeof(*pcie)); 1066 if (!pcie) { 1067 error("failed to allocate controller"); 1068 continue; 1069 } 1070 1071 memset(pcie, 0, sizeof(*pcie)); 1072 pcie->soc = soc; 1073 1074 INIT_LIST_HEAD(&pcie->ports); 1075 1076 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); 1077 if (err < 0) { 1078 free(pcie); 1079 continue; 1080 } 1081 1082 err = tegra_pcie_power_on(pcie); 1083 if (err < 0) { 1084 error("failed to power on"); 1085 continue; 1086 } 1087 1088 err = tegra_pcie_enable_controller(pcie); 1089 if (err < 0) { 1090 error("failed to enable controller"); 1091 continue; 1092 } 1093 1094 tegra_pcie_setup_translations(pcie); 1095 1096 err = tegra_pcie_enable(pcie); 1097 if (err < 0) { 1098 error("failed to enable PCIe"); 1099 continue; 1100 } 1101 1102 pcie->hose.first_busno = 0; 1103 pcie->hose.current_busno = 0; 1104 pcie->hose.last_busno = 0; 1105 1106 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, 1107 NV_PA_SDRAM_BASE, pci_dram_size, 1108 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 1109 1110 pci_set_region(&pcie->hose.regions[1], pcie->io.start, 1111 pcie->io.start, fdt_resource_size(&pcie->io), 1112 PCI_REGION_IO); 1113 1114 pci_set_region(&pcie->hose.regions[2], pcie->mem.start, 1115 pcie->mem.start, fdt_resource_size(&pcie->mem), 1116 PCI_REGION_MEM); 1117 1118 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, 1119 pcie->prefetch.start, 1120 fdt_resource_size(&pcie->prefetch), 1121 PCI_REGION_MEM | PCI_REGION_PREFETCH); 1122 1123 pcie->hose.region_count = 4; 1124 1125 pci_set_ops(&pcie->hose, 1126 pci_hose_read_config_byte_via_dword, 1127 pci_hose_read_config_word_via_dword, 1128 tegra_pcie_read_conf, 1129 pci_hose_write_config_byte_via_dword, 1130 pci_hose_write_config_word_via_dword, 1131 tegra_pcie_write_conf); 1132 1133 pci_register_hose(&pcie->hose); 1134 1135 #ifdef CONFIG_PCI_SCAN_SHOW 1136 printf("PCI: Enumerating devices...\n"); 1137 printf("---------------------------------------\n"); 1138 printf(" Device ID Description\n"); 1139 printf(" ------ -- -----------\n"); 1140 #endif 1141 1142 pcie->hose.last_busno = pci_hose_scan(&pcie->hose); 1143 } 1144 1145 return 0; 1146 } 1147 1148 void pci_init_board(void) 1149 { 1150 const void *fdt = gd->fdt_blob; 1151 int count, nodes[1]; 1152 1153 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1154 COMPAT_NVIDIA_TEGRA124_PCIE, 1155 nodes, ARRAY_SIZE(nodes)); 1156 if (process_nodes(fdt, nodes, count)) 1157 return; 1158 1159 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1160 COMPAT_NVIDIA_TEGRA30_PCIE, 1161 nodes, ARRAY_SIZE(nodes)); 1162 if (process_nodes(fdt, nodes, count)) 1163 return; 1164 1165 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", 1166 COMPAT_NVIDIA_TEGRA20_PCIE, 1167 nodes, ARRAY_SIZE(nodes)); 1168 if (process_nodes(fdt, nodes, count)) 1169 return; 1170 } 1171 1172 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) 1173 { 1174 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) 1175 return 1; 1176 1177 return 0; 1178 } 1179