xref: /rk3399_rockchip-uboot/drivers/pci/pci_indirect.c (revision 2eb48ff7a210ddd2a39bac23b3b9b39c60c32aef)
193a686eeSJean-Christophe PLAGNIOL-VILLARD /*
293a686eeSJean-Christophe PLAGNIOL-VILLARD  * Support for indirect PCI bridges.
393a686eeSJean-Christophe PLAGNIOL-VILLARD  *
493a686eeSJean-Christophe PLAGNIOL-VILLARD  * Copyright (C) 1998 Gabriel Paubert.
593a686eeSJean-Christophe PLAGNIOL-VILLARD  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
793a686eeSJean-Christophe PLAGNIOL-VILLARD  */
893a686eeSJean-Christophe PLAGNIOL-VILLARD 
993a686eeSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
1093a686eeSJean-Christophe PLAGNIOL-VILLARD 
1129161f47SMichael Schwingen #if !defined(__I386__)
1293a686eeSJean-Christophe PLAGNIOL-VILLARD 
1393a686eeSJean-Christophe PLAGNIOL-VILLARD #include <asm/processor.h>
1493a686eeSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
1593a686eeSJean-Christophe PLAGNIOL-VILLARD #include <pci.h>
1693a686eeSJean-Christophe PLAGNIOL-VILLARD 
1793a686eeSJean-Christophe PLAGNIOL-VILLARD #define cfg_read(val, addr, type, op)	*val = op((type)(addr))
1893a686eeSJean-Christophe PLAGNIOL-VILLARD #define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
1993a686eeSJean-Christophe PLAGNIOL-VILLARD 
20*2eb48ff7SHeiko Schocher #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
2193a686eeSJean-Christophe PLAGNIOL-VILLARD #define INDIRECT_PCI_OP(rw, size, type, op, mask)                        \
2293a686eeSJean-Christophe PLAGNIOL-VILLARD static int                                                               \
2393a686eeSJean-Christophe PLAGNIOL-VILLARD indirect_##rw##_config_##size(struct pci_controller *hose,               \
2493a686eeSJean-Christophe PLAGNIOL-VILLARD 			      pci_dev_t dev, int offset, type val)       \
2593a686eeSJean-Christophe PLAGNIOL-VILLARD {                                                                        \
2693a686eeSJean-Christophe PLAGNIOL-VILLARD 	u32 b, d,f;							 \
2793a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
2893a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = b - hose->first_busno;					 \
2993a686eeSJean-Christophe PLAGNIOL-VILLARD 	dev = PCI_BDF(b, d, f);						 \
3093a686eeSJean-Christophe PLAGNIOL-VILLARD 	*(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
3193a686eeSJean-Christophe PLAGNIOL-VILLARD 	sync();                                                          \
3293a686eeSJean-Christophe PLAGNIOL-VILLARD 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
3393a686eeSJean-Christophe PLAGNIOL-VILLARD 	return 0;                                                        \
3493a686eeSJean-Christophe PLAGNIOL-VILLARD }
3597c9f290SFelix Radensky #elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
3697c9f290SFelix Radensky       defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
3793a686eeSJean-Christophe PLAGNIOL-VILLARD #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
3893a686eeSJean-Christophe PLAGNIOL-VILLARD static int								 \
3993a686eeSJean-Christophe PLAGNIOL-VILLARD indirect_##rw##_config_##size(struct pci_controller *hose,		 \
4093a686eeSJean-Christophe PLAGNIOL-VILLARD 			      pci_dev_t dev, int offset, type val)	 \
4193a686eeSJean-Christophe PLAGNIOL-VILLARD {									 \
4293a686eeSJean-Christophe PLAGNIOL-VILLARD 	u32 b, d,f;							 \
4393a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
4493a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = b - hose->first_busno;					 \
4593a686eeSJean-Christophe PLAGNIOL-VILLARD 	dev = PCI_BDF(b, d, f);						 \
4693a686eeSJean-Christophe PLAGNIOL-VILLARD 	if (PCI_BUS(dev) > 0)                                            \
4793a686eeSJean-Christophe PLAGNIOL-VILLARD 		out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
4893a686eeSJean-Christophe PLAGNIOL-VILLARD 	else                                                             \
4993a686eeSJean-Christophe PLAGNIOL-VILLARD 		out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
5093a686eeSJean-Christophe PLAGNIOL-VILLARD 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
5193a686eeSJean-Christophe PLAGNIOL-VILLARD 	return 0;							 \
5293a686eeSJean-Christophe PLAGNIOL-VILLARD }
5393a686eeSJean-Christophe PLAGNIOL-VILLARD #else
5493a686eeSJean-Christophe PLAGNIOL-VILLARD #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
5593a686eeSJean-Christophe PLAGNIOL-VILLARD static int								 \
5693a686eeSJean-Christophe PLAGNIOL-VILLARD indirect_##rw##_config_##size(struct pci_controller *hose,		 \
5793a686eeSJean-Christophe PLAGNIOL-VILLARD 			      pci_dev_t dev, int offset, type val)	 \
5893a686eeSJean-Christophe PLAGNIOL-VILLARD {									 \
5993a686eeSJean-Christophe PLAGNIOL-VILLARD 	u32 b, d,f;							 \
6093a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
6193a686eeSJean-Christophe PLAGNIOL-VILLARD 	b = b - hose->first_busno;					 \
6293a686eeSJean-Christophe PLAGNIOL-VILLARD 	dev = PCI_BDF(b, d, f);						 \
6393a686eeSJean-Christophe PLAGNIOL-VILLARD 	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
6493a686eeSJean-Christophe PLAGNIOL-VILLARD 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
6593a686eeSJean-Christophe PLAGNIOL-VILLARD 	return 0;							 \
6693a686eeSJean-Christophe PLAGNIOL-VILLARD }
6793a686eeSJean-Christophe PLAGNIOL-VILLARD #endif
6893a686eeSJean-Christophe PLAGNIOL-VILLARD 
6993a686eeSJean-Christophe PLAGNIOL-VILLARD #define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask)		 \
7093a686eeSJean-Christophe PLAGNIOL-VILLARD static int								 \
7193a686eeSJean-Christophe PLAGNIOL-VILLARD indirect_##rw##_config_##size(struct pci_controller *hose,		 \
7293a686eeSJean-Christophe PLAGNIOL-VILLARD 			      pci_dev_t dev, int offset, type val)	 \
7393a686eeSJean-Christophe PLAGNIOL-VILLARD {									 \
7493a686eeSJean-Christophe PLAGNIOL-VILLARD 	unsigned int msr = mfmsr();					 \
7593a686eeSJean-Christophe PLAGNIOL-VILLARD 	mtmsr(msr & ~(MSR_EE | MSR_CE));				 \
7693a686eeSJean-Christophe PLAGNIOL-VILLARD 	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
7793a686eeSJean-Christophe PLAGNIOL-VILLARD 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
7893a686eeSJean-Christophe PLAGNIOL-VILLARD 	out_le32(hose->cfg_addr, 0x00000000);				 \
7993a686eeSJean-Christophe PLAGNIOL-VILLARD 	mtmsr(msr);							 \
8093a686eeSJean-Christophe PLAGNIOL-VILLARD 	return 0;							 \
8193a686eeSJean-Christophe PLAGNIOL-VILLARD }
8293a686eeSJean-Christophe PLAGNIOL-VILLARD 
8393a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
8493a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
8593a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
8693a686eeSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_405GP
8793a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
8893a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
8993a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
9093a686eeSJean-Christophe PLAGNIOL-VILLARD #else
9193a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
9293a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
9393a686eeSJean-Christophe PLAGNIOL-VILLARD INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
9493a686eeSJean-Christophe PLAGNIOL-VILLARD #endif
9593a686eeSJean-Christophe PLAGNIOL-VILLARD 
9693a686eeSJean-Christophe PLAGNIOL-VILLARD void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
9793a686eeSJean-Christophe PLAGNIOL-VILLARD {
9893a686eeSJean-Christophe PLAGNIOL-VILLARD 	pci_set_ops(hose,
9993a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_read_config_byte,
10093a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_read_config_word,
10193a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_read_config_dword,
10293a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_write_config_byte,
10393a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_write_config_word,
10493a686eeSJean-Christophe PLAGNIOL-VILLARD 		    indirect_write_config_dword);
10593a686eeSJean-Christophe PLAGNIOL-VILLARD 
10693a686eeSJean-Christophe PLAGNIOL-VILLARD 	hose->cfg_addr = (unsigned int *) cfg_addr;
10793a686eeSJean-Christophe PLAGNIOL-VILLARD 	hose->cfg_data = (unsigned char *) cfg_data;
10893a686eeSJean-Christophe PLAGNIOL-VILLARD }
10993a686eeSJean-Christophe PLAGNIOL-VILLARD 
11029161f47SMichael Schwingen #endif	/* !__I386__ */
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