1 /* 2 * PCI autoconfiguration library (legacy version, do not change) 3 * 4 * Author: Matt Porter <mporter@mvista.com> 5 * 6 * Copyright 2000 MontaVista Software Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <pci.h> 14 15 /* 16 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI 17 * and change pci_auto.c. 18 */ 19 20 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 21 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 22 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 23 #endif 24 25 /* 26 * 27 */ 28 29 void pciauto_setup_device(struct pci_controller *hose, 30 pci_dev_t dev, int bars_num, 31 struct pci_region *mem, 32 struct pci_region *prefetch, 33 struct pci_region *io) 34 { 35 u32 bar_response; 36 pci_size_t bar_size; 37 u16 cmdstat = 0; 38 int bar, bar_nr = 0; 39 #ifndef CONFIG_PCI_ENUM_ONLY 40 u8 header_type; 41 int rom_addr; 42 pci_addr_t bar_value; 43 struct pci_region *bar_res; 44 int found_mem64 = 0; 45 #endif 46 u16 class; 47 48 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 49 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 50 51 for (bar = PCI_BASE_ADDRESS_0; 52 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 53 /* Tickle the BAR and get the response */ 54 #ifndef CONFIG_PCI_ENUM_ONLY 55 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 56 #endif 57 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 58 59 /* If BAR is not implemented go to the next BAR */ 60 if (!bar_response) 61 continue; 62 63 #ifndef CONFIG_PCI_ENUM_ONLY 64 found_mem64 = 0; 65 #endif 66 67 /* Check the BAR type and set our address mask */ 68 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 69 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 70 & 0xffff) + 1; 71 #ifndef CONFIG_PCI_ENUM_ONLY 72 bar_res = io; 73 #endif 74 75 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", 76 bar_nr, (unsigned long long)bar_size); 77 } else { 78 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 79 PCI_BASE_ADDRESS_MEM_TYPE_64) { 80 u32 bar_response_upper; 81 u64 bar64; 82 83 #ifndef CONFIG_PCI_ENUM_ONLY 84 pci_hose_write_config_dword(hose, dev, bar + 4, 85 0xffffffff); 86 #endif 87 pci_hose_read_config_dword(hose, dev, bar + 4, 88 &bar_response_upper); 89 90 bar64 = ((u64)bar_response_upper << 32) | bar_response; 91 92 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 93 #ifndef CONFIG_PCI_ENUM_ONLY 94 found_mem64 = 1; 95 #endif 96 } else { 97 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 98 } 99 #ifndef CONFIG_PCI_ENUM_ONLY 100 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 101 bar_res = prefetch; 102 else 103 bar_res = mem; 104 #endif 105 106 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ", 107 bar_nr, bar_res == prefetch ? "Prf" : "Mem", 108 (unsigned long long)bar_size); 109 } 110 111 #ifndef CONFIG_PCI_ENUM_ONLY 112 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 113 /* Write it out and update our limit */ 114 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); 115 116 if (found_mem64) { 117 bar += 4; 118 #ifdef CONFIG_SYS_PCI_64BIT 119 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); 120 #else 121 /* 122 * If we are a 64-bit decoder then increment to the 123 * upper 32 bits of the bar and force it to locate 124 * in the lower 4GB of memory. 125 */ 126 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 127 #endif 128 } 129 130 } 131 #endif 132 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 133 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 134 135 debug("\n"); 136 137 bar_nr++; 138 } 139 140 #ifndef CONFIG_PCI_ENUM_ONLY 141 /* Configure the expansion ROM address */ 142 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 143 header_type &= 0x7f; 144 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 145 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 146 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 147 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe); 148 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response); 149 if (bar_response) { 150 bar_size = -(bar_response & ~1); 151 debug("PCI Autoconfig: ROM, size=%#x, ", 152 (unsigned int)bar_size); 153 if (pciauto_region_allocate(mem, bar_size, 154 &bar_value) == 0) { 155 pci_hose_write_config_dword(hose, dev, rom_addr, 156 bar_value); 157 } 158 cmdstat |= PCI_COMMAND_MEMORY; 159 debug("\n"); 160 } 161 } 162 #endif 163 164 /* PCI_COMMAND_IO must be set for VGA device */ 165 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 166 if (class == PCI_CLASS_DISPLAY_VGA) 167 cmdstat |= PCI_COMMAND_IO; 168 169 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 170 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 171 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 172 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 173 } 174 175 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 176 pci_dev_t dev, int sub_bus) 177 { 178 struct pci_region *pci_mem; 179 struct pci_region *pci_prefetch; 180 struct pci_region *pci_io; 181 u16 cmdstat, prefechable_64; 182 183 #ifdef CONFIG_DM_PCI 184 /* The root controller has the region information */ 185 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 186 187 pci_mem = ctlr_hose->pci_mem; 188 pci_prefetch = ctlr_hose->pci_prefetch; 189 pci_io = ctlr_hose->pci_io; 190 #else 191 pci_mem = hose->pci_mem; 192 pci_prefetch = hose->pci_prefetch; 193 pci_io = hose->pci_io; 194 #endif 195 196 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 197 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 198 &prefechable_64); 199 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 200 201 /* Configure bus number registers */ 202 #ifdef CONFIG_DM_PCI 203 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); 204 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); 205 #else 206 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 207 PCI_BUS(dev) - hose->first_busno); 208 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 209 sub_bus - hose->first_busno); 210 #endif 211 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 212 213 if (pci_mem) { 214 /* Round memory allocator to 1MB boundary */ 215 pciauto_region_align(pci_mem, 0x100000); 216 217 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 218 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 219 (pci_mem->bus_lower & 0xfff00000) >> 16); 220 221 cmdstat |= PCI_COMMAND_MEMORY; 222 } 223 224 if (pci_prefetch) { 225 /* Round memory allocator to 1MB boundary */ 226 pciauto_region_align(pci_prefetch, 0x100000); 227 228 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 229 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 230 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 231 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 232 #ifdef CONFIG_SYS_PCI_64BIT 233 pci_hose_write_config_dword(hose, dev, 234 PCI_PREF_BASE_UPPER32, 235 pci_prefetch->bus_lower >> 32); 236 #else 237 pci_hose_write_config_dword(hose, dev, 238 PCI_PREF_BASE_UPPER32, 239 0x0); 240 #endif 241 242 cmdstat |= PCI_COMMAND_MEMORY; 243 } else { 244 /* We don't support prefetchable memory for now, so disable */ 245 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 246 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 247 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 248 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); 249 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); 250 } 251 } 252 253 if (pci_io) { 254 /* Round I/O allocator to 4KB boundary */ 255 pciauto_region_align(pci_io, 0x1000); 256 257 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 258 (pci_io->bus_lower & 0x0000f000) >> 8); 259 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 260 (pci_io->bus_lower & 0xffff0000) >> 16); 261 262 cmdstat |= PCI_COMMAND_IO; 263 } 264 265 /* Enable memory and I/O accesses, enable bus master */ 266 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 267 cmdstat | PCI_COMMAND_MASTER); 268 } 269 270 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 271 pci_dev_t dev, int sub_bus) 272 { 273 struct pci_region *pci_mem; 274 struct pci_region *pci_prefetch; 275 struct pci_region *pci_io; 276 277 #ifdef CONFIG_DM_PCI 278 /* The root controller has the region information */ 279 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 280 281 pci_mem = ctlr_hose->pci_mem; 282 pci_prefetch = ctlr_hose->pci_prefetch; 283 pci_io = ctlr_hose->pci_io; 284 #else 285 pci_mem = hose->pci_mem; 286 pci_prefetch = hose->pci_prefetch; 287 pci_io = hose->pci_io; 288 #endif 289 290 /* Configure bus number registers */ 291 #ifdef CONFIG_DM_PCI 292 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); 293 #else 294 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 295 sub_bus - hose->first_busno); 296 #endif 297 298 if (pci_mem) { 299 /* Round memory allocator to 1MB boundary */ 300 pciauto_region_align(pci_mem, 0x100000); 301 302 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 303 (pci_mem->bus_lower - 1) >> 16); 304 } 305 306 if (pci_prefetch) { 307 u16 prefechable_64; 308 309 pci_hose_read_config_word(hose, dev, 310 PCI_PREF_MEMORY_LIMIT, 311 &prefechable_64); 312 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 313 314 /* Round memory allocator to 1MB boundary */ 315 pciauto_region_align(pci_prefetch, 0x100000); 316 317 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 318 (pci_prefetch->bus_lower - 1) >> 16); 319 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 320 #ifdef CONFIG_SYS_PCI_64BIT 321 pci_hose_write_config_dword(hose, dev, 322 PCI_PREF_LIMIT_UPPER32, 323 (pci_prefetch->bus_lower - 1) >> 32); 324 #else 325 pci_hose_write_config_dword(hose, dev, 326 PCI_PREF_LIMIT_UPPER32, 327 0x0); 328 #endif 329 } 330 331 if (pci_io) { 332 /* Round I/O allocator to 4KB boundary */ 333 pciauto_region_align(pci_io, 0x1000); 334 335 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 336 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 337 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 338 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 339 } 340 } 341 342 343 /* 344 * HJF: Changed this to return int. I think this is required 345 * to get the correct result when scanning bridges 346 */ 347 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 348 { 349 struct pci_region *pci_mem; 350 struct pci_region *pci_prefetch; 351 struct pci_region *pci_io; 352 unsigned int sub_bus = PCI_BUS(dev); 353 unsigned short class; 354 int n; 355 356 #ifdef CONFIG_DM_PCI 357 /* The root controller has the region information */ 358 struct pci_controller *ctlr_hose = pci_bus_to_hose(0); 359 360 pci_mem = ctlr_hose->pci_mem; 361 pci_prefetch = ctlr_hose->pci_prefetch; 362 pci_io = ctlr_hose->pci_io; 363 #else 364 pci_mem = hose->pci_mem; 365 pci_prefetch = hose->pci_prefetch; 366 pci_io = hose->pci_io; 367 #endif 368 369 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 370 371 switch (class) { 372 case PCI_CLASS_BRIDGE_PCI: 373 debug("PCI Autoconfig: Found P2P bridge, device %d\n", 374 PCI_DEV(dev)); 375 376 pciauto_setup_device(hose, dev, 2, pci_mem, 377 pci_prefetch, pci_io); 378 379 #ifdef CONFIG_DM_PCI 380 n = dm_pci_hose_probe_bus(hose, dev); 381 if (n < 0) 382 return n; 383 sub_bus = (unsigned int)n; 384 #else 385 /* Passing in current_busno allows for sibling P2P bridges */ 386 hose->current_busno++; 387 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 388 /* 389 * need to figure out if this is a subordinate bridge on the bus 390 * to be able to properly set the pri/sec/sub bridge registers. 391 */ 392 n = pci_hose_scan_bus(hose, hose->current_busno); 393 394 /* figure out the deepest we've gone for this leg */ 395 sub_bus = max((unsigned int)n, sub_bus); 396 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 397 398 sub_bus = hose->current_busno; 399 #endif 400 break; 401 402 case PCI_CLASS_BRIDGE_CARDBUS: 403 /* 404 * just do a minimal setup of the bridge, 405 * let the OS take care of the rest 406 */ 407 pciauto_setup_device(hose, dev, 0, pci_mem, 408 pci_prefetch, pci_io); 409 410 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 411 PCI_DEV(dev)); 412 413 #ifndef CONFIG_DM_PCI 414 hose->current_busno++; 415 #endif 416 break; 417 418 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 419 case PCI_CLASS_BRIDGE_OTHER: 420 debug("PCI Autoconfig: Skipping bridge device %d\n", 421 PCI_DEV(dev)); 422 break; 423 #endif 424 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 425 case PCI_CLASS_BRIDGE_OTHER: 426 /* 427 * The host/PCI bridge 1 seems broken in 8349 - it presents 428 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 429 * device claiming resources io/mem/irq.. we only allow for 430 * the PIMMR window to be allocated (BAR0 - 1MB size) 431 */ 432 debug("PCI Autoconfig: Broken bridge found, only minimal config\n"); 433 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 434 hose->pci_prefetch, hose->pci_io); 435 break; 436 #endif 437 438 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 439 debug("PCI AutoConfig: Found PowerPC device\n"); 440 441 default: 442 pciauto_setup_device(hose, dev, 6, pci_mem, 443 pci_prefetch, pci_io); 444 break; 445 } 446 447 return sub_bus; 448 } 449