1 /* 2 * arch/powerpc/kernel/pci_auto.c 3 * 4 * PCI autoconfiguration library 5 * 6 * Author: Matt Porter <mporter@mvista.com> 7 * 8 * Copyright 2000 MontaVista Software Inc. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <pci.h> 16 17 #ifdef DEBUG 18 #define DEBUGF(x...) printf(x) 19 #else 20 #define DEBUGF(x...) 21 #endif /* DEBUG */ 22 23 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ 24 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE 25 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 26 #endif 27 28 /* 29 * 30 */ 31 32 void pciauto_region_init(struct pci_region *res) 33 { 34 /* 35 * Avoid allocating PCI resources from address 0 -- this is illegal 36 * according to PCI 2.1 and moreover, this is known to cause Linux IDE 37 * drivers to fail. Use a reasonable starting value of 0x1000 instead. 38 */ 39 res->bus_lower = res->bus_start ? res->bus_start : 0x1000; 40 } 41 42 void pciauto_region_align(struct pci_region *res, pci_size_t size) 43 { 44 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; 45 } 46 47 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 48 pci_addr_t *bar) 49 { 50 pci_addr_t addr; 51 52 if (!res) { 53 DEBUGF("No resource"); 54 goto error; 55 } 56 57 addr = ((res->bus_lower - 1) | (size - 1)) + 1; 58 59 if (addr - res->bus_start + size > res->size) { 60 DEBUGF("No room in resource"); 61 goto error; 62 } 63 64 res->bus_lower = addr + size; 65 66 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower); 67 68 *bar = addr; 69 return 0; 70 71 error: 72 *bar = (pci_addr_t)-1; 73 return -1; 74 } 75 76 /* 77 * 78 */ 79 80 void pciauto_setup_device(struct pci_controller *hose, 81 pci_dev_t dev, int bars_num, 82 struct pci_region *mem, 83 struct pci_region *prefetch, 84 struct pci_region *io) 85 { 86 u32 bar_response; 87 pci_size_t bar_size; 88 u16 cmdstat = 0; 89 int bar, bar_nr = 0; 90 u8 header_type; 91 int rom_addr; 92 #ifndef CONFIG_PCI_ENUM_ONLY 93 pci_addr_t bar_value; 94 struct pci_region *bar_res; 95 int found_mem64 = 0; 96 #endif 97 98 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 99 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; 100 101 for (bar = PCI_BASE_ADDRESS_0; 102 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { 103 /* Tickle the BAR and get the response */ 104 #ifndef CONFIG_PCI_ENUM_ONLY 105 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); 106 #endif 107 pci_hose_read_config_dword(hose, dev, bar, &bar_response); 108 109 /* If BAR is not implemented go to the next BAR */ 110 if (!bar_response) 111 continue; 112 113 #ifndef CONFIG_PCI_ENUM_ONLY 114 found_mem64 = 0; 115 #endif 116 117 /* Check the BAR type and set our address mask */ 118 if (bar_response & PCI_BASE_ADDRESS_SPACE) { 119 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) 120 & 0xffff) + 1; 121 #ifndef CONFIG_PCI_ENUM_ONLY 122 bar_res = io; 123 #endif 124 125 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size); 126 } else { 127 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 128 PCI_BASE_ADDRESS_MEM_TYPE_64) { 129 u32 bar_response_upper; 130 u64 bar64; 131 132 #ifndef CONFIG_PCI_ENUM_ONLY 133 pci_hose_write_config_dword(hose, dev, bar + 4, 134 0xffffffff); 135 #endif 136 pci_hose_read_config_dword(hose, dev, bar + 4, 137 &bar_response_upper); 138 139 bar64 = ((u64)bar_response_upper << 32) | bar_response; 140 141 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; 142 #ifndef CONFIG_PCI_ENUM_ONLY 143 found_mem64 = 1; 144 #endif 145 } else { 146 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); 147 } 148 #ifndef CONFIG_PCI_ENUM_ONLY 149 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) 150 bar_res = prefetch; 151 else 152 bar_res = mem; 153 #endif 154 155 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size); 156 } 157 158 #ifndef CONFIG_PCI_ENUM_ONLY 159 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { 160 /* Write it out and update our limit */ 161 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); 162 163 if (found_mem64) { 164 bar += 4; 165 #ifdef CONFIG_SYS_PCI_64BIT 166 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); 167 #else 168 /* 169 * If we are a 64-bit decoder then increment to the 170 * upper 32 bits of the bar and force it to locate 171 * in the lower 4GB of memory. 172 */ 173 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); 174 #endif 175 } 176 177 } 178 #endif 179 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? 180 PCI_COMMAND_IO : PCI_COMMAND_MEMORY; 181 182 DEBUGF("\n"); 183 184 bar_nr++; 185 } 186 187 /* Configure the expansion ROM address */ 188 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); 189 if (header_type != PCI_HEADER_TYPE_CARDBUS) { 190 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? 191 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; 192 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe); 193 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response); 194 if (bar_response) { 195 bar_size = -(bar_response & ~1); 196 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size); 197 if (pciauto_region_allocate(mem, bar_size, 198 &bar_value) == 0) { 199 pci_hose_write_config_dword(hose, dev, rom_addr, 200 bar_value); 201 } 202 cmdstat |= PCI_COMMAND_MEMORY; 203 DEBUGF("\n"); 204 } 205 } 206 207 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat); 208 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 209 CONFIG_SYS_PCI_CACHE_LINE_SIZE); 210 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 211 } 212 213 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 214 pci_dev_t dev, int sub_bus) 215 { 216 struct pci_region *pci_mem = hose->pci_mem; 217 struct pci_region *pci_prefetch = hose->pci_prefetch; 218 struct pci_region *pci_io = hose->pci_io; 219 u16 cmdstat, prefechable_64; 220 221 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); 222 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 223 &prefechable_64); 224 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 225 226 /* Configure bus number registers */ 227 #ifdef CONFIG_DM_PCI 228 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); 229 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); 230 #else 231 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, 232 PCI_BUS(dev) - hose->first_busno); 233 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, 234 sub_bus - hose->first_busno); 235 #endif 236 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); 237 238 if (pci_mem) { 239 /* Round memory allocator to 1MB boundary */ 240 pciauto_region_align(pci_mem, 0x100000); 241 242 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 243 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, 244 (pci_mem->bus_lower & 0xfff00000) >> 16); 245 246 cmdstat |= PCI_COMMAND_MEMORY; 247 } 248 249 if (pci_prefetch) { 250 /* Round memory allocator to 1MB boundary */ 251 pciauto_region_align(pci_prefetch, 0x100000); 252 253 /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 254 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 255 (pci_prefetch->bus_lower & 0xfff00000) >> 16); 256 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 257 #ifdef CONFIG_SYS_PCI_64BIT 258 pci_hose_write_config_dword(hose, dev, 259 PCI_PREF_BASE_UPPER32, 260 pci_prefetch->bus_lower >> 32); 261 #else 262 pci_hose_write_config_dword(hose, dev, 263 PCI_PREF_BASE_UPPER32, 264 0x0); 265 #endif 266 267 cmdstat |= PCI_COMMAND_MEMORY; 268 } else { 269 /* We don't support prefetchable memory for now, so disable */ 270 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); 271 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); 272 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { 273 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); 274 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); 275 } 276 } 277 278 if (pci_io) { 279 /* Round I/O allocator to 4KB boundary */ 280 pciauto_region_align(pci_io, 0x1000); 281 282 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, 283 (pci_io->bus_lower & 0x0000f000) >> 8); 284 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, 285 (pci_io->bus_lower & 0xffff0000) >> 16); 286 287 cmdstat |= PCI_COMMAND_IO; 288 } 289 290 /* Enable memory and I/O accesses, enable bus master */ 291 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 292 cmdstat | PCI_COMMAND_MASTER); 293 } 294 295 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 296 pci_dev_t dev, int sub_bus) 297 { 298 struct pci_region *pci_mem = hose->pci_mem; 299 struct pci_region *pci_prefetch = hose->pci_prefetch; 300 struct pci_region *pci_io = hose->pci_io; 301 302 /* Configure bus number registers */ 303 #ifdef CONFIG_DM_PCI 304 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); 305 #else 306 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 307 sub_bus - hose->first_busno); 308 #endif 309 310 if (pci_mem) { 311 /* Round memory allocator to 1MB boundary */ 312 pciauto_region_align(pci_mem, 0x100000); 313 314 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, 315 (pci_mem->bus_lower - 1) >> 16); 316 } 317 318 if (pci_prefetch) { 319 u16 prefechable_64; 320 321 pci_hose_read_config_word(hose, dev, 322 PCI_PREF_MEMORY_LIMIT, 323 &prefechable_64); 324 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; 325 326 /* Round memory allocator to 1MB boundary */ 327 pciauto_region_align(pci_prefetch, 0x100000); 328 329 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 330 (pci_prefetch->bus_lower - 1) >> 16); 331 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) 332 #ifdef CONFIG_SYS_PCI_64BIT 333 pci_hose_write_config_dword(hose, dev, 334 PCI_PREF_LIMIT_UPPER32, 335 (pci_prefetch->bus_lower - 1) >> 32); 336 #else 337 pci_hose_write_config_dword(hose, dev, 338 PCI_PREF_LIMIT_UPPER32, 339 0x0); 340 #endif 341 } 342 343 if (pci_io) { 344 /* Round I/O allocator to 4KB boundary */ 345 pciauto_region_align(pci_io, 0x1000); 346 347 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, 348 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); 349 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, 350 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); 351 } 352 } 353 354 /* 355 * 356 */ 357 358 void pciauto_config_init(struct pci_controller *hose) 359 { 360 int i; 361 362 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; 363 364 for (i = 0; i < hose->region_count; i++) { 365 switch(hose->regions[i].flags) { 366 case PCI_REGION_IO: 367 if (!hose->pci_io || 368 hose->pci_io->size < hose->regions[i].size) 369 hose->pci_io = hose->regions + i; 370 break; 371 case PCI_REGION_MEM: 372 if (!hose->pci_mem || 373 hose->pci_mem->size < hose->regions[i].size) 374 hose->pci_mem = hose->regions + i; 375 break; 376 case (PCI_REGION_MEM | PCI_REGION_PREFETCH): 377 if (!hose->pci_prefetch || 378 hose->pci_prefetch->size < hose->regions[i].size) 379 hose->pci_prefetch = hose->regions + i; 380 break; 381 } 382 } 383 384 385 if (hose->pci_mem) { 386 pciauto_region_init(hose->pci_mem); 387 388 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n" 389 "\t\tPhysical Memory [%llx-%llxx]\n", 390 (u64)hose->pci_mem->bus_start, 391 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1), 392 (u64)hose->pci_mem->phys_start, 393 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1)); 394 } 395 396 if (hose->pci_prefetch) { 397 pciauto_region_init(hose->pci_prefetch); 398 399 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n" 400 "\t\tPhysical Memory [%llx-%llx]\n", 401 (u64)hose->pci_prefetch->bus_start, 402 (u64)(hose->pci_prefetch->bus_start + 403 hose->pci_prefetch->size - 1), 404 (u64)hose->pci_prefetch->phys_start, 405 (u64)(hose->pci_prefetch->phys_start + 406 hose->pci_prefetch->size - 1)); 407 } 408 409 if (hose->pci_io) { 410 pciauto_region_init(hose->pci_io); 411 412 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n" 413 "\t\tPhysical Memory: [%llx-%llx]\n", 414 (u64)hose->pci_io->bus_start, 415 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1), 416 (u64)hose->pci_io->phys_start, 417 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1)); 418 419 } 420 } 421 422 /* 423 * HJF: Changed this to return int. I think this is required 424 * to get the correct result when scanning bridges 425 */ 426 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) 427 { 428 unsigned int sub_bus = PCI_BUS(dev); 429 unsigned short class; 430 int n; 431 432 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); 433 434 switch (class) { 435 case PCI_CLASS_BRIDGE_PCI: 436 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", 437 PCI_DEV(dev)); 438 439 pciauto_setup_device(hose, dev, 2, hose->pci_mem, 440 hose->pci_prefetch, hose->pci_io); 441 442 #ifdef CONFIG_DM_PCI 443 n = dm_pci_hose_probe_bus(hose, dev); 444 if (n < 0) 445 return n; 446 sub_bus = (unsigned int)n; 447 #else 448 /* Passing in current_busno allows for sibling P2P bridges */ 449 hose->current_busno++; 450 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 451 /* 452 * need to figure out if this is a subordinate bridge on the bus 453 * to be able to properly set the pri/sec/sub bridge registers. 454 */ 455 n = pci_hose_scan_bus(hose, hose->current_busno); 456 457 /* figure out the deepest we've gone for this leg */ 458 sub_bus = max((unsigned int)n, sub_bus); 459 pciauto_postscan_setup_bridge(hose, dev, sub_bus); 460 461 sub_bus = hose->current_busno; 462 #endif 463 break; 464 465 case PCI_CLASS_BRIDGE_CARDBUS: 466 /* 467 * just do a minimal setup of the bridge, 468 * let the OS take care of the rest 469 */ 470 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 471 hose->pci_prefetch, hose->pci_io); 472 473 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", 474 PCI_DEV(dev)); 475 476 #ifndef CONFIG_DM_PCI 477 hose->current_busno++; 478 #endif 479 break; 480 481 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE) 482 case PCI_CLASS_BRIDGE_OTHER: 483 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", 484 PCI_DEV(dev)); 485 break; 486 #endif 487 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349) 488 case PCI_CLASS_BRIDGE_OTHER: 489 /* 490 * The host/PCI bridge 1 seems broken in 8349 - it presents 491 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ 492 * device claiming resources io/mem/irq.. we only allow for 493 * the PIMMR window to be allocated (BAR0 - 1MB size) 494 */ 495 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); 496 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 497 hose->pci_prefetch, hose->pci_io); 498 break; 499 #endif 500 501 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */ 502 DEBUGF("PCI AutoConfig: Found PowerPC device\n"); 503 504 default: 505 pciauto_setup_device(hose, dev, 6, hose->pci_mem, 506 hose->pci_prefetch, hose->pci_io); 507 break; 508 } 509 510 return sub_bus; 511 } 512