1 /* 2 * Copyright (c) 2014 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <inttypes.h> 13 #include <pci.h> 14 #include <dm/lists.h> 15 #include <dm/root.h> 16 #include <dm/device-internal.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 struct pci_controller *pci_bus_to_hose(int busnum) 21 { 22 struct udevice *bus; 23 int ret; 24 25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus); 26 if (ret) { 27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); 28 return NULL; 29 } 30 return dev_get_uclass_priv(bus); 31 } 32 33 pci_dev_t pci_get_bdf(struct udevice *dev) 34 { 35 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 36 struct udevice *bus = dev->parent; 37 38 return PCI_ADD_BUS(bus->seq, pplat->devfn); 39 } 40 41 /** 42 * pci_get_bus_max() - returns the bus number of the last active bus 43 * 44 * @return last bus number, or -1 if no active buses 45 */ 46 static int pci_get_bus_max(void) 47 { 48 struct udevice *bus; 49 struct uclass *uc; 50 int ret = -1; 51 52 ret = uclass_get(UCLASS_PCI, &uc); 53 uclass_foreach_dev(bus, uc) { 54 if (bus->seq > ret) 55 ret = bus->seq; 56 } 57 58 debug("%s: ret=%d\n", __func__, ret); 59 60 return ret; 61 } 62 63 int pci_last_busno(void) 64 { 65 struct pci_controller *hose; 66 struct udevice *bus; 67 struct uclass *uc; 68 int ret; 69 70 debug("pci_last_busno\n"); 71 ret = uclass_get(UCLASS_PCI, &uc); 72 if (ret || list_empty(&uc->dev_head)) 73 return -1; 74 75 /* Probe the last bus */ 76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 77 debug("bus = %p, %s\n", bus, bus->name); 78 assert(bus); 79 ret = device_probe(bus); 80 if (ret) 81 return ret; 82 83 /* If that bus has bridges, we may have new buses now. Get the last */ 84 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node); 85 hose = dev_get_uclass_priv(bus); 86 debug("bus = %s, hose = %p\n", bus->name, hose); 87 88 return hose->last_busno; 89 } 90 91 int pci_get_ff(enum pci_size_t size) 92 { 93 switch (size) { 94 case PCI_SIZE_8: 95 return 0xff; 96 case PCI_SIZE_16: 97 return 0xffff; 98 default: 99 return 0xffffffff; 100 } 101 } 102 103 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 104 struct udevice **devp) 105 { 106 struct udevice *dev; 107 108 for (device_find_first_child(bus, &dev); 109 dev; 110 device_find_next_child(&dev)) { 111 struct pci_child_platdata *pplat; 112 113 pplat = dev_get_parent_platdata(dev); 114 if (pplat && pplat->devfn == find_devfn) { 115 *devp = dev; 116 return 0; 117 } 118 } 119 120 return -ENODEV; 121 } 122 123 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) 124 { 125 struct udevice *bus; 126 int ret; 127 128 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 129 if (ret) 130 return ret; 131 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp); 132 } 133 134 static int pci_device_matches_ids(struct udevice *dev, 135 struct pci_device_id *ids) 136 { 137 struct pci_child_platdata *pplat; 138 int i; 139 140 pplat = dev_get_parent_platdata(dev); 141 if (!pplat) 142 return -EINVAL; 143 for (i = 0; ids[i].vendor != 0; i++) { 144 if (pplat->vendor == ids[i].vendor && 145 pplat->device == ids[i].device) 146 return i; 147 } 148 149 return -EINVAL; 150 } 151 152 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 153 int *indexp, struct udevice **devp) 154 { 155 struct udevice *dev; 156 157 /* Scan all devices on this bus */ 158 for (device_find_first_child(bus, &dev); 159 dev; 160 device_find_next_child(&dev)) { 161 if (pci_device_matches_ids(dev, ids) >= 0) { 162 if ((*indexp)-- <= 0) { 163 *devp = dev; 164 return 0; 165 } 166 } 167 } 168 169 return -ENODEV; 170 } 171 172 int pci_find_device_id(struct pci_device_id *ids, int index, 173 struct udevice **devp) 174 { 175 struct udevice *bus; 176 177 /* Scan all known buses */ 178 for (uclass_first_device(UCLASS_PCI, &bus); 179 bus; 180 uclass_next_device(&bus)) { 181 if (!pci_bus_find_devices(bus, ids, &index, devp)) 182 return 0; 183 } 184 *devp = NULL; 185 186 return -ENODEV; 187 } 188 189 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 190 unsigned long value, enum pci_size_t size) 191 { 192 struct dm_pci_ops *ops; 193 194 ops = pci_get_ops(bus); 195 if (!ops->write_config) 196 return -ENOSYS; 197 return ops->write_config(bus, bdf, offset, value, size); 198 } 199 200 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, 201 enum pci_size_t size) 202 { 203 struct udevice *bus; 204 int ret; 205 206 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 207 if (ret) 208 return ret; 209 210 return pci_bus_write_config(bus, bdf, offset, value, size); 211 } 212 213 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 214 enum pci_size_t size) 215 { 216 struct udevice *bus; 217 218 for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) 219 bus = bus->parent; 220 return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size); 221 } 222 223 224 int pci_write_config32(pci_dev_t bdf, int offset, u32 value) 225 { 226 return pci_write_config(bdf, offset, value, PCI_SIZE_32); 227 } 228 229 int pci_write_config16(pci_dev_t bdf, int offset, u16 value) 230 { 231 return pci_write_config(bdf, offset, value, PCI_SIZE_16); 232 } 233 234 int pci_write_config8(pci_dev_t bdf, int offset, u8 value) 235 { 236 return pci_write_config(bdf, offset, value, PCI_SIZE_8); 237 } 238 239 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value) 240 { 241 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8); 242 } 243 244 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value) 245 { 246 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16); 247 } 248 249 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value) 250 { 251 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32); 252 } 253 254 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 255 unsigned long *valuep, enum pci_size_t size) 256 { 257 struct dm_pci_ops *ops; 258 259 ops = pci_get_ops(bus); 260 if (!ops->read_config) 261 return -ENOSYS; 262 return ops->read_config(bus, bdf, offset, valuep, size); 263 } 264 265 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, 266 enum pci_size_t size) 267 { 268 struct udevice *bus; 269 int ret; 270 271 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus); 272 if (ret) 273 return ret; 274 275 return pci_bus_read_config(bus, bdf, offset, valuep, size); 276 } 277 278 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 279 enum pci_size_t size) 280 { 281 struct udevice *bus; 282 283 for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;) 284 bus = bus->parent; 285 return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep, 286 size); 287 } 288 289 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) 290 { 291 unsigned long value; 292 int ret; 293 294 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); 295 if (ret) 296 return ret; 297 *valuep = value; 298 299 return 0; 300 } 301 302 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) 303 { 304 unsigned long value; 305 int ret; 306 307 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); 308 if (ret) 309 return ret; 310 *valuep = value; 311 312 return 0; 313 } 314 315 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) 316 { 317 unsigned long value; 318 int ret; 319 320 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); 321 if (ret) 322 return ret; 323 *valuep = value; 324 325 return 0; 326 } 327 328 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep) 329 { 330 unsigned long value; 331 int ret; 332 333 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); 334 if (ret) 335 return ret; 336 *valuep = value; 337 338 return 0; 339 } 340 341 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep) 342 { 343 unsigned long value; 344 int ret; 345 346 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); 347 if (ret) 348 return ret; 349 *valuep = value; 350 351 return 0; 352 } 353 354 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep) 355 { 356 unsigned long value; 357 int ret; 358 359 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); 360 if (ret) 361 return ret; 362 *valuep = value; 363 364 return 0; 365 } 366 367 int pci_auto_config_devices(struct udevice *bus) 368 { 369 struct pci_controller *hose = bus->uclass_priv; 370 unsigned int sub_bus; 371 struct udevice *dev; 372 int ret; 373 374 sub_bus = bus->seq; 375 debug("%s: start\n", __func__); 376 pciauto_config_init(hose); 377 for (ret = device_find_first_child(bus, &dev); 378 !ret && dev; 379 ret = device_find_next_child(&dev)) { 380 unsigned int max_bus; 381 382 debug("%s: device %s\n", __func__, dev->name); 383 max_bus = pciauto_config_device(hose, pci_get_bdf(dev)); 384 sub_bus = max(sub_bus, max_bus); 385 } 386 debug("%s: done\n", __func__); 387 388 return sub_bus; 389 } 390 391 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf) 392 { 393 struct udevice *parent, *bus; 394 int sub_bus; 395 int ret; 396 397 debug("%s\n", __func__); 398 parent = hose->bus; 399 400 /* Find the bus within the parent */ 401 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus); 402 if (ret) { 403 debug("%s: Cannot find device %x on bus %s: %d\n", __func__, 404 bdf, parent->name, ret); 405 return ret; 406 } 407 408 sub_bus = pci_get_bus_max() + 1; 409 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); 410 pciauto_prescan_setup_bridge(hose, bdf, sub_bus); 411 412 ret = device_probe(bus); 413 if (ret) { 414 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name, 415 ret); 416 return ret; 417 } 418 if (sub_bus != bus->seq) { 419 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", 420 __func__, bus->name, bus->seq, sub_bus); 421 return -EPIPE; 422 } 423 sub_bus = pci_get_bus_max(); 424 pciauto_postscan_setup_bridge(hose, bdf, sub_bus); 425 426 return sub_bus; 427 } 428 429 /** 430 * pci_match_one_device - Tell if a PCI device structure has a matching 431 * PCI device id structure 432 * @id: single PCI device id structure to match 433 * @dev: the PCI device structure to match against 434 * 435 * Returns the matching pci_device_id structure or %NULL if there is no match. 436 */ 437 static bool pci_match_one_id(const struct pci_device_id *id, 438 const struct pci_device_id *find) 439 { 440 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) && 441 (id->device == PCI_ANY_ID || id->device == find->device) && 442 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) && 443 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) && 444 !((id->class ^ find->class) & id->class_mask)) 445 return true; 446 447 return false; 448 } 449 450 /** 451 * pci_find_and_bind_driver() - Find and bind the right PCI driver 452 * 453 * This only looks at certain fields in the descriptor. 454 */ 455 static int pci_find_and_bind_driver(struct udevice *parent, 456 struct pci_device_id *find_id, pci_dev_t bdf, 457 struct udevice **devp) 458 { 459 struct pci_driver_entry *start, *entry; 460 const char *drv; 461 int n_ents; 462 int ret; 463 char name[30], *str; 464 bool bridge; 465 466 *devp = NULL; 467 468 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__, 469 find_id->vendor, find_id->device); 470 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry); 471 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry); 472 for (entry = start; entry != start + n_ents; entry++) { 473 const struct pci_device_id *id; 474 struct udevice *dev; 475 const struct driver *drv; 476 477 for (id = entry->match; 478 id->vendor || id->subvendor || id->class_mask; 479 id++) { 480 if (!pci_match_one_id(id, find_id)) 481 continue; 482 483 drv = entry->driver; 484 485 /* 486 * In the pre-relocation phase, we only bind devices 487 * whose driver has the DM_FLAG_PRE_RELOC set, to save 488 * precious memory space as on some platforms as that 489 * space is pretty limited (ie: using Cache As RAM). 490 */ 491 if (!(gd->flags & GD_FLG_RELOC) && 492 !(drv->flags & DM_FLAG_PRE_RELOC)) 493 return 0; 494 495 /* 496 * We could pass the descriptor to the driver as 497 * platdata (instead of NULL) and allow its bind() 498 * method to return -ENOENT if it doesn't support this 499 * device. That way we could continue the search to 500 * find another driver. For now this doesn't seem 501 * necesssary, so just bind the first match. 502 */ 503 ret = device_bind(parent, drv, drv->name, NULL, -1, 504 &dev); 505 if (ret) 506 goto error; 507 debug("%s: Match found: %s\n", __func__, drv->name); 508 dev->driver_data = find_id->driver_data; 509 *devp = dev; 510 return 0; 511 } 512 } 513 514 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI; 515 /* 516 * In the pre-relocation phase, we only bind bridge devices to save 517 * precious memory space as on some platforms as that space is pretty 518 * limited (ie: using Cache As RAM). 519 */ 520 if (!(gd->flags & GD_FLG_RELOC) && !bridge) 521 return 0; 522 523 /* Bind a generic driver so that the device can be used */ 524 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf), 525 PCI_FUNC(bdf)); 526 str = strdup(name); 527 if (!str) 528 return -ENOMEM; 529 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv"; 530 531 ret = device_bind_driver(parent, drv, str, devp); 532 if (ret) { 533 debug("%s: Failed to bind generic driver: %d", __func__, ret); 534 return ret; 535 } 536 debug("%s: No match found: bound generic driver instead\n", __func__); 537 538 return 0; 539 540 error: 541 debug("%s: No match found: error %d\n", __func__, ret); 542 return ret; 543 } 544 545 int pci_bind_bus_devices(struct udevice *bus) 546 { 547 ulong vendor, device; 548 ulong header_type; 549 pci_dev_t bdf, end; 550 bool found_multi; 551 int ret; 552 553 found_multi = false; 554 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1, 555 PCI_MAX_PCI_FUNCTIONS - 1); 556 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end; 557 bdf += PCI_BDF(0, 0, 1)) { 558 struct pci_child_platdata *pplat; 559 struct udevice *dev; 560 ulong class; 561 562 if (PCI_FUNC(bdf) && !found_multi) 563 continue; 564 /* Check only the first access, we don't expect problems */ 565 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, 566 &header_type, PCI_SIZE_8); 567 if (ret) 568 goto error; 569 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, 570 PCI_SIZE_16); 571 if (vendor == 0xffff || vendor == 0x0000) 572 continue; 573 574 if (!PCI_FUNC(bdf)) 575 found_multi = header_type & 0x80; 576 577 debug("%s: bus %d/%s: found device %x, function %d\n", __func__, 578 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf)); 579 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device, 580 PCI_SIZE_16); 581 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class, 582 PCI_SIZE_32); 583 class >>= 8; 584 585 /* Find this device in the device tree */ 586 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); 587 588 /* Search for a driver */ 589 590 /* If nothing in the device tree, bind a generic device */ 591 if (ret == -ENODEV) { 592 struct pci_device_id find_id; 593 ulong val; 594 595 memset(&find_id, '\0', sizeof(find_id)); 596 find_id.vendor = vendor; 597 find_id.device = device; 598 find_id.class = class; 599 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { 600 pci_bus_read_config(bus, bdf, 601 PCI_SUBSYSTEM_VENDOR_ID, 602 &val, PCI_SIZE_32); 603 find_id.subvendor = val & 0xffff; 604 find_id.subdevice = val >> 16; 605 } 606 ret = pci_find_and_bind_driver(bus, &find_id, bdf, 607 &dev); 608 } 609 if (ret) 610 return ret; 611 612 /* Update the platform data */ 613 if (dev) { 614 pplat = dev_get_parent_platdata(dev); 615 pplat->devfn = PCI_MASK_BUS(bdf); 616 pplat->vendor = vendor; 617 pplat->device = device; 618 pplat->class = class; 619 } 620 } 621 622 return 0; 623 error: 624 printf("Cannot read bus configuration: %d\n", ret); 625 626 return ret; 627 } 628 629 static int pci_uclass_post_bind(struct udevice *bus) 630 { 631 /* 632 * Scan the device tree for devices. This does not probe the PCI bus, 633 * as this is not permitted while binding. It just finds devices 634 * mentioned in the device tree. 635 * 636 * Before relocation, only bind devices marked for pre-relocation 637 * use. 638 */ 639 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, 640 gd->flags & GD_FLG_RELOC ? false : true); 641 } 642 643 static int decode_regions(struct pci_controller *hose, const void *blob, 644 int parent_node, int node) 645 { 646 int pci_addr_cells, addr_cells, size_cells; 647 int cells_per_record; 648 phys_addr_t addr; 649 const u32 *prop; 650 int len; 651 int i; 652 653 prop = fdt_getprop(blob, node, "ranges", &len); 654 if (!prop) 655 return -EINVAL; 656 pci_addr_cells = fdt_address_cells(blob, node); 657 addr_cells = fdt_address_cells(blob, parent_node); 658 size_cells = fdt_size_cells(blob, node); 659 660 /* PCI addresses are always 3-cells */ 661 len /= sizeof(u32); 662 cells_per_record = pci_addr_cells + addr_cells + size_cells; 663 hose->region_count = 0; 664 debug("%s: len=%d, cells_per_record=%d\n", __func__, len, 665 cells_per_record); 666 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { 667 u64 pci_addr, addr, size; 668 int space_code; 669 u32 flags; 670 int type; 671 672 if (len < cells_per_record) 673 break; 674 flags = fdt32_to_cpu(prop[0]); 675 space_code = (flags >> 24) & 3; 676 pci_addr = fdtdec_get_number(prop + 1, 2); 677 prop += pci_addr_cells; 678 addr = fdtdec_get_number(prop, addr_cells); 679 prop += addr_cells; 680 size = fdtdec_get_number(prop, size_cells); 681 prop += size_cells; 682 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64 683 ", size=%" PRIx64 ", space_code=%d\n", __func__, 684 hose->region_count, pci_addr, addr, size, space_code); 685 if (space_code & 2) { 686 type = flags & (1U << 30) ? PCI_REGION_PREFETCH : 687 PCI_REGION_MEM; 688 } else if (space_code & 1) { 689 type = PCI_REGION_IO; 690 } else { 691 continue; 692 } 693 debug(" - type=%d\n", type); 694 pci_set_region(hose->regions + hose->region_count++, pci_addr, 695 addr, size, type); 696 } 697 698 /* Add a region for our local memory */ 699 addr = gd->ram_size; 700 if (gd->pci_ram_top && gd->pci_ram_top < addr) 701 addr = gd->pci_ram_top; 702 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr, 703 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 704 705 return 0; 706 } 707 708 static int pci_uclass_pre_probe(struct udevice *bus) 709 { 710 struct pci_controller *hose; 711 int ret; 712 713 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, 714 bus->parent->name); 715 hose = bus->uclass_priv; 716 717 /* For bridges, use the top-level PCI controller */ 718 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) { 719 hose->ctlr = bus; 720 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset, 721 bus->of_offset); 722 if (ret) { 723 debug("%s: Cannot decode regions\n", __func__); 724 return ret; 725 } 726 } else { 727 struct pci_controller *parent_hose; 728 729 parent_hose = dev_get_uclass_priv(bus->parent); 730 hose->ctlr = parent_hose->bus; 731 } 732 hose->bus = bus; 733 hose->first_busno = bus->seq; 734 hose->last_busno = bus->seq; 735 736 return 0; 737 } 738 739 static int pci_uclass_post_probe(struct udevice *bus) 740 { 741 int ret; 742 743 debug("%s: probing bus %d\n", __func__, bus->seq); 744 ret = pci_bind_bus_devices(bus); 745 if (ret) 746 return ret; 747 748 #ifdef CONFIG_PCI_PNP 749 ret = pci_auto_config_devices(bus); 750 #endif 751 752 return ret < 0 ? ret : 0; 753 } 754 755 static int pci_uclass_child_post_bind(struct udevice *dev) 756 { 757 struct pci_child_platdata *pplat; 758 struct fdt_pci_addr addr; 759 int ret; 760 761 if (dev->of_offset == -1) 762 return 0; 763 764 /* 765 * We could read vendor, device, class if available. But for now we 766 * just check the address. 767 */ 768 pplat = dev_get_parent_platdata(dev); 769 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, 770 FDT_PCI_SPACE_CONFIG, "reg", &addr); 771 772 if (ret) { 773 if (ret != -ENOENT) 774 return -EINVAL; 775 } else { 776 /* extract the bdf from fdt_pci_addr */ 777 pplat->devfn = addr.phys_hi & 0xffff00; 778 } 779 780 return 0; 781 } 782 783 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf, 784 uint offset, ulong *valuep, 785 enum pci_size_t size) 786 { 787 struct pci_controller *hose = bus->uclass_priv; 788 789 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); 790 } 791 792 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf, 793 uint offset, ulong value, 794 enum pci_size_t size) 795 { 796 struct pci_controller *hose = bus->uclass_priv; 797 798 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); 799 } 800 801 static int skip_to_next_device(struct udevice *bus, struct udevice **devp) 802 { 803 struct udevice *dev; 804 int ret = 0; 805 806 /* 807 * Scan through all the PCI controllers. On x86 there will only be one 808 * but that is not necessarily true on other hardware. 809 */ 810 do { 811 device_find_first_child(bus, &dev); 812 if (dev) { 813 *devp = dev; 814 return 0; 815 } 816 ret = uclass_next_device(&bus); 817 if (ret) 818 return ret; 819 } while (bus); 820 821 return 0; 822 } 823 824 int pci_find_next_device(struct udevice **devp) 825 { 826 struct udevice *child = *devp; 827 struct udevice *bus = child->parent; 828 int ret; 829 830 /* First try all the siblings */ 831 *devp = NULL; 832 while (child) { 833 device_find_next_child(&child); 834 if (child) { 835 *devp = child; 836 return 0; 837 } 838 } 839 840 /* We ran out of siblings. Try the next bus */ 841 ret = uclass_next_device(&bus); 842 if (ret) 843 return ret; 844 845 return bus ? skip_to_next_device(bus, devp) : 0; 846 } 847 848 int pci_find_first_device(struct udevice **devp) 849 { 850 struct udevice *bus; 851 int ret; 852 853 *devp = NULL; 854 ret = uclass_first_device(UCLASS_PCI, &bus); 855 if (ret) 856 return ret; 857 858 return skip_to_next_device(bus, devp); 859 } 860 861 UCLASS_DRIVER(pci) = { 862 .id = UCLASS_PCI, 863 .name = "pci", 864 .flags = DM_UC_FLAG_SEQ_ALIAS, 865 .post_bind = pci_uclass_post_bind, 866 .pre_probe = pci_uclass_pre_probe, 867 .post_probe = pci_uclass_post_probe, 868 .child_post_bind = pci_uclass_child_post_bind, 869 .per_device_auto_alloc_size = sizeof(struct pci_controller), 870 .per_child_platdata_auto_alloc_size = 871 sizeof(struct pci_child_platdata), 872 }; 873 874 static const struct dm_pci_ops pci_bridge_ops = { 875 .read_config = pci_bridge_read_config, 876 .write_config = pci_bridge_write_config, 877 }; 878 879 static const struct udevice_id pci_bridge_ids[] = { 880 { .compatible = "pci-bridge" }, 881 { } 882 }; 883 884 U_BOOT_DRIVER(pci_bridge_drv) = { 885 .name = "pci_bridge_drv", 886 .id = UCLASS_PCI, 887 .of_match = pci_bridge_ids, 888 .ops = &pci_bridge_ops, 889 }; 890 891 UCLASS_DRIVER(pci_generic) = { 892 .id = UCLASS_PCI_GENERIC, 893 .name = "pci_generic", 894 }; 895 896 static const struct udevice_id pci_generic_ids[] = { 897 { .compatible = "pci-generic" }, 898 { } 899 }; 900 901 U_BOOT_DRIVER(pci_generic_drv) = { 902 .name = "pci_generic_drv", 903 .id = UCLASS_PCI_GENERIC, 904 .of_match = pci_generic_ids, 905 }; 906