1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* 24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 25 * 26 * Initialize controller and call the common driver/pci pci_hose_scan to 27 * scan for bridges and devices. 28 * 29 * Hose fields which need to be pre-initialized by board specific code: 30 * regions[] 31 * first_busno 32 * 33 * Fields updated: 34 * last_busno 35 */ 36 37 #include <pci.h> 38 #include <asm/immap_fsl_pci.h> 39 40 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 41 pci_dev_t dev, int sub_bus); 42 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 43 pci_dev_t dev, int sub_bus); 44 void pciauto_config_init(struct pci_controller *hose); 45 46 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 47 #define CONFIG_SYS_PCI_MEMORY_BUS 0 48 #endif 49 50 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 51 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 52 #endif 53 54 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 55 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 56 #endif 57 58 int fsl_pci_setup_inbound_windows(struct pci_region *r) 59 { 60 struct pci_region *rgn_base = r; 61 u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); 62 63 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 64 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 65 pci_size_t pci_sz = 1ull << __ilog2_u64(sz); 66 67 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 68 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 69 pci_set_region(r++, bus_start, phys_start, pci_sz, 70 PCI_REGION_MEM | PCI_REGION_MEMORY | 71 PCI_REGION_PREFETCH); 72 73 sz -= pci_sz; 74 bus_start += pci_sz; 75 phys_start += pci_sz; 76 77 pci_sz = 1ull << __ilog2_u64(sz); 78 if (sz) { 79 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 80 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 81 pci_set_region(r++, bus_start, phys_start, pci_sz, 82 PCI_REGION_MEM | PCI_REGION_MEMORY | 83 PCI_REGION_PREFETCH); 84 sz -= pci_sz; 85 bus_start += pci_sz; 86 phys_start += pci_sz; 87 } 88 89 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 90 /* 91 * On 64-bit capable systems, set up a mapping for all of DRAM 92 * in high pci address space. 93 */ 94 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 95 /* round up to the next largest power of two */ 96 if (gd->ram_size > pci_sz) 97 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 98 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 99 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 100 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 101 (u64)pci_sz); 102 pci_set_region(r++, 103 CONFIG_SYS_PCI64_MEMORY_BUS, 104 CONFIG_SYS_PCI_MEMORY_PHYS, 105 pci_sz, 106 PCI_REGION_MEM | PCI_REGION_MEMORY | 107 PCI_REGION_PREFETCH); 108 #else 109 pci_sz = 1ull << __ilog2_u64(sz); 110 if (sz) { 111 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 112 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 113 pci_set_region(r++, bus_start, phys_start, pci_sz, 114 PCI_REGION_MEM | PCI_REGION_MEMORY | 115 PCI_REGION_PREFETCH); 116 sz -= pci_sz; 117 bus_start += pci_sz; 118 phys_start += pci_sz; 119 } 120 #endif 121 122 #ifdef CONFIG_PHYS_64BIT 123 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 124 printf("Was not able to map all of memory via " 125 "inbound windows -- %lld remaining\n", sz); 126 #endif 127 128 return r - rgn_base; 129 } 130 131 void fsl_pci_init(struct pci_controller *hose) 132 { 133 u16 temp16; 134 u32 temp32; 135 int busno = hose->first_busno; 136 int enabled; 137 u16 ltssm; 138 u8 temp8; 139 int r; 140 int bridge; 141 int inbound = 0; 142 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; 143 pci_dev_t dev = PCI_BDF(busno,0,0); 144 145 /* Initialize ATMU registers based on hose regions and flags */ 146 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 147 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */ 148 149 #ifdef DEBUG 150 int neg_link_w; 151 #endif 152 153 for (r=0; r<hose->region_count; r++) { 154 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 155 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ 156 u32 flag = PIWAR_EN | PIWAR_LOCAL | 157 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 158 pi->pitar = (hose->regions[r].phys_start >> 12); 159 pi->piwbar = (hose->regions[r].bus_start >> 12); 160 #ifdef CONFIG_SYS_PCI_64BIT 161 pi->piwbear = (hose->regions[r].bus_start >> 44); 162 #else 163 pi->piwbear = 0; 164 #endif 165 if (hose->regions[r].flags & PCI_REGION_PREFETCH) 166 flag |= PIWAR_PF; 167 pi->piwar = flag | sz; 168 pi++; 169 inbound = hose->regions[r].size > 0; 170 } else { /* Outbound */ 171 po->powbar = (hose->regions[r].phys_start >> 12); 172 po->potar = (hose->regions[r].bus_start >> 12); 173 #ifdef CONFIG_SYS_PCI_64BIT 174 po->potear = (hose->regions[r].bus_start >> 44); 175 #else 176 po->potear = 0; 177 #endif 178 if (hose->regions[r].flags & PCI_REGION_IO) 179 po->powar = POWAR_EN | sz | 180 POWAR_IO_READ | POWAR_IO_WRITE; 181 else 182 po->powar = POWAR_EN | sz | 183 POWAR_MEM_READ | POWAR_MEM_WRITE; 184 po++; 185 } 186 } 187 188 pci_register_hose(hose); 189 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 190 hose->current_busno = hose->first_busno; 191 192 pci->pedr = 0xffffffff; /* Clear any errors */ 193 pci->peer = ~0x20140; /* Enable All Error Interupts except 194 * - Master abort (pci) 195 * - Master PERR (pci) 196 * - ICCA (PCIe) 197 */ 198 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); 199 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 200 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 201 202 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); 203 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ 204 205 if ( bridge ) { 206 207 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 208 enabled = ltssm >= PCI_LTSSM_L0; 209 210 #ifdef CONFIG_FSL_PCIE_RESET 211 if (ltssm == 1) { 212 int i; 213 debug("....PCIe link error. " 214 "LTSSM=0x%02x.", ltssm); 215 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */ 216 temp32 = pci->pdb_stat; 217 udelay(100); 218 debug(" Asserting PCIe reset @%x = %x\n", 219 &pci->pdb_stat, pci->pdb_stat); 220 pci->pdb_stat &= ~0x08000000; /* clear reset */ 221 asm("sync;isync"); 222 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 223 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 224 <ssm); 225 udelay(1000); 226 debug("....PCIe link error. " 227 "LTSSM=0x%02x.\n", ltssm); 228 } 229 enabled = ltssm >= PCI_LTSSM_L0; 230 } 231 #endif 232 233 if (!enabled) { 234 debug("....PCIE link error. Skipping scan." 235 "LTSSM=0x%02x\n", ltssm); 236 hose->last_busno = hose->first_busno; 237 return; 238 } 239 240 pci->pme_msg_det = 0xffffffff; 241 pci->pme_msg_int_en = 0xffffffff; 242 #ifdef DEBUG 243 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 244 neg_link_w = (temp16 & 0x3f0 ) >> 4; 245 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 246 ltssm, neg_link_w); 247 #endif 248 hose->current_busno++; /* Start scan with secondary */ 249 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 250 251 } 252 253 /* Use generic setup_device to initialize standard pci regs, 254 * but do not allocate any windows since any BAR found (such 255 * as PCSRBAR) is not in this cpu's memory space. 256 */ 257 258 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 259 hose->pci_prefetch, hose->pci_io); 260 261 if (inbound) { 262 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 263 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 264 temp16 | PCI_COMMAND_MEMORY); 265 } 266 267 #ifndef CONFIG_PCI_NOSCAN 268 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 269 270 /* Programming Interface (PCI_CLASS_PROG) 271 * 0 == pci host or pcie root-complex, 272 * 1 == pci agent or pcie end-point 273 */ 274 if (!temp8) { 275 printf(" Scanning PCI bus %02x\n", 276 hose->current_busno); 277 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 278 } else { 279 debug(" Not scanning PCI bus %02x. PI=%x\n", 280 hose->current_busno, temp8); 281 hose->last_busno = hose->current_busno; 282 } 283 284 if ( bridge ) { /* update limit regs and subordinate busno */ 285 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 286 } 287 #else 288 hose->last_busno = hose->current_busno; 289 #endif 290 291 /* Clear all error indications */ 292 293 if (bridge) 294 pci->pme_msg_det = 0xffffffff; 295 pci->pedr = 0xffffffff; 296 297 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 298 if (temp16) { 299 pci_hose_write_config_word(hose, dev, 300 PCI_DSR, 0xffff); 301 } 302 303 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 304 if (temp16) { 305 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 306 } 307 } 308 309 #ifdef CONFIG_OF_BOARD_SETUP 310 #include <libfdt.h> 311 #include <fdt_support.h> 312 313 void ft_fsl_pci_setup(void *blob, const char *pci_alias, 314 struct pci_controller *hose) 315 { 316 int off = fdt_path_offset(blob, pci_alias); 317 318 if (off >= 0) { 319 u32 bus_range[2]; 320 321 bus_range[0] = 0; 322 bus_range[1] = hose->last_busno - hose->first_busno; 323 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 324 fdt_pci_dma_ranges(blob, off, hose); 325 } 326 } 327 #endif 328