1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* 24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 25 * 26 * Initialize controller and call the common driver/pci pci_hose_scan to 27 * scan for bridges and devices. 28 * 29 * Hose fields which need to be pre-initialized by board specific code: 30 * regions[] 31 * first_busno 32 * 33 * Fields updated: 34 * last_busno 35 */ 36 37 #include <pci.h> 38 #include <asm/fsl_pci.h> 39 40 /* Freescale-specific PCI config registers */ 41 #define FSL_PCI_PBFR 0x44 42 #define FSL_PCIE_CAP_ID 0x4c 43 #define FSL_PCIE_CFG_RDY 0x4b0 44 45 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 46 pci_dev_t dev, int sub_bus); 47 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 48 pci_dev_t dev, int sub_bus); 49 void pciauto_config_init(struct pci_controller *hose); 50 51 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 52 #define CONFIG_SYS_PCI_MEMORY_BUS 0 53 #endif 54 55 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 56 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 57 #endif 58 59 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 60 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 61 #endif 62 63 static int fsl_pci_setup_inbound_windows(struct pci_region *r) 64 { 65 struct pci_region *rgn_base = r; 66 u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); 67 68 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 69 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 70 pci_size_t pci_sz = 1ull << __ilog2_u64(sz); 71 72 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 73 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 74 pci_set_region(r++, bus_start, phys_start, pci_sz, 75 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 76 PCI_REGION_PREFETCH); 77 78 sz -= pci_sz; 79 bus_start += pci_sz; 80 phys_start += pci_sz; 81 82 pci_sz = 1ull << __ilog2_u64(sz); 83 if (sz) { 84 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 85 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 86 pci_set_region(r++, bus_start, phys_start, pci_sz, 87 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 88 PCI_REGION_PREFETCH); 89 sz -= pci_sz; 90 bus_start += pci_sz; 91 phys_start += pci_sz; 92 } 93 94 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 95 /* 96 * On 64-bit capable systems, set up a mapping for all of DRAM 97 * in high pci address space. 98 */ 99 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 100 /* round up to the next largest power of two */ 101 if (gd->ram_size > pci_sz) 102 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 103 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 104 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 105 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 106 (u64)pci_sz); 107 pci_set_region(r++, 108 CONFIG_SYS_PCI64_MEMORY_BUS, 109 CONFIG_SYS_PCI_MEMORY_PHYS, 110 pci_sz, 111 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 112 PCI_REGION_PREFETCH); 113 #else 114 pci_sz = 1ull << __ilog2_u64(sz); 115 if (sz) { 116 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 117 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 118 pci_set_region(r++, bus_start, phys_start, pci_sz, 119 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 120 PCI_REGION_PREFETCH); 121 sz -= pci_sz; 122 bus_start += pci_sz; 123 phys_start += pci_sz; 124 } 125 #endif 126 127 #ifdef CONFIG_PHYS_64BIT 128 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 129 printf("Was not able to map all of memory via " 130 "inbound windows -- %lld remaining\n", sz); 131 #endif 132 133 return r - rgn_base; 134 } 135 136 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) 137 { 138 u16 temp16; 139 u32 temp32; 140 int busno = hose->first_busno; 141 int enabled; 142 u16 ltssm; 143 u8 temp8; 144 int r; 145 int bridge; 146 int inbound = 0; 147 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 148 struct pci_region *reg = hose->regions + hose->region_count; 149 pci_dev_t dev = PCI_BDF(busno,0,0); 150 151 /* Initialize ATMU registers based on hose regions and flags */ 152 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 153 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */ 154 155 #ifdef DEBUG 156 int neg_link_w; 157 #endif 158 159 pci_setup_indirect(hose, cfg_addr, cfg_data); 160 161 /* inbound */ 162 reg += fsl_pci_setup_inbound_windows(reg); 163 164 hose->region_count = reg - hose->regions; 165 166 for (r=0; r<hose->region_count; r++) { 167 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 168 if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */ 169 u32 flag = PIWAR_EN | PIWAR_LOCAL | 170 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 171 pi->pitar = (hose->regions[r].phys_start >> 12); 172 pi->piwbar = (hose->regions[r].bus_start >> 12); 173 #ifdef CONFIG_SYS_PCI_64BIT 174 pi->piwbear = (hose->regions[r].bus_start >> 44); 175 #else 176 pi->piwbear = 0; 177 #endif 178 if (hose->regions[r].flags & PCI_REGION_PREFETCH) 179 flag |= PIWAR_PF; 180 pi->piwar = flag | sz; 181 pi++; 182 inbound = hose->regions[r].size > 0; 183 } else { /* Outbound */ 184 po->powbar = (hose->regions[r].phys_start >> 12); 185 po->potar = (hose->regions[r].bus_start >> 12); 186 #ifdef CONFIG_SYS_PCI_64BIT 187 po->potear = (hose->regions[r].bus_start >> 44); 188 #else 189 po->potear = 0; 190 #endif 191 if (hose->regions[r].flags & PCI_REGION_IO) 192 po->powar = POWAR_EN | sz | 193 POWAR_IO_READ | POWAR_IO_WRITE; 194 else 195 po->powar = POWAR_EN | sz | 196 POWAR_MEM_READ | POWAR_MEM_WRITE; 197 po++; 198 } 199 } 200 201 pci_register_hose(hose); 202 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 203 hose->current_busno = hose->first_busno; 204 205 pci->pedr = 0xffffffff; /* Clear any errors */ 206 pci->peer = ~0x20140; /* Enable All Error Interupts except 207 * - Master abort (pci) 208 * - Master PERR (pci) 209 * - ICCA (PCIe) 210 */ 211 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); 212 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 213 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 214 215 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); 216 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ 217 218 if ( bridge ) { 219 220 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 221 enabled = ltssm >= PCI_LTSSM_L0; 222 223 #ifdef CONFIG_FSL_PCIE_RESET 224 if (ltssm == 1) { 225 int i; 226 debug("....PCIe link error. " 227 "LTSSM=0x%02x.", ltssm); 228 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */ 229 temp32 = pci->pdb_stat; 230 udelay(100); 231 debug(" Asserting PCIe reset @%x = %x\n", 232 &pci->pdb_stat, pci->pdb_stat); 233 pci->pdb_stat &= ~0x08000000; /* clear reset */ 234 asm("sync;isync"); 235 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 236 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 237 <ssm); 238 udelay(1000); 239 debug("....PCIe link error. " 240 "LTSSM=0x%02x.\n", ltssm); 241 } 242 enabled = ltssm >= PCI_LTSSM_L0; 243 } 244 #endif 245 246 if (!enabled) { 247 debug("....PCIE link error. Skipping scan." 248 "LTSSM=0x%02x\n", ltssm); 249 hose->last_busno = hose->first_busno; 250 return; 251 } 252 253 pci->pme_msg_det = 0xffffffff; 254 pci->pme_msg_int_en = 0xffffffff; 255 #ifdef DEBUG 256 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 257 neg_link_w = (temp16 & 0x3f0 ) >> 4; 258 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 259 ltssm, neg_link_w); 260 #endif 261 hose->current_busno++; /* Start scan with secondary */ 262 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 263 264 } 265 266 /* Use generic setup_device to initialize standard pci regs, 267 * but do not allocate any windows since any BAR found (such 268 * as PCSRBAR) is not in this cpu's memory space. 269 */ 270 271 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 272 hose->pci_prefetch, hose->pci_io); 273 274 if (inbound) { 275 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 276 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 277 temp16 | PCI_COMMAND_MEMORY); 278 } 279 280 #ifndef CONFIG_PCI_NOSCAN 281 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 282 283 /* Programming Interface (PCI_CLASS_PROG) 284 * 0 == pci host or pcie root-complex, 285 * 1 == pci agent or pcie end-point 286 */ 287 if (!temp8) { 288 printf(" Scanning PCI bus %02x\n", 289 hose->current_busno); 290 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 291 } else { 292 debug(" Not scanning PCI bus %02x. PI=%x\n", 293 hose->current_busno, temp8); 294 hose->last_busno = hose->current_busno; 295 } 296 297 if ( bridge ) { /* update limit regs and subordinate busno */ 298 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 299 } 300 #else 301 hose->last_busno = hose->current_busno; 302 #endif 303 304 /* Clear all error indications */ 305 306 if (bridge) 307 pci->pme_msg_det = 0xffffffff; 308 pci->pedr = 0xffffffff; 309 310 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 311 if (temp16) { 312 pci_hose_write_config_word(hose, dev, 313 PCI_DSR, 0xffff); 314 } 315 316 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 317 if (temp16) { 318 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 319 } 320 } 321 322 /* Enable inbound PCI config cycles for agent/endpoint interface */ 323 void fsl_pci_config_unlock(struct pci_controller *hose) 324 { 325 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 326 u8 agent; 327 u8 pcie_cap; 328 u16 pbfr; 329 330 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 331 if (!agent) 332 return; 333 334 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 335 if (pcie_cap != 0x0) { 336 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 337 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 338 } else { 339 /* PCI - clear ACL bit of PBFR */ 340 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 341 pbfr &= ~0x20; 342 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 343 } 344 } 345 346 #ifdef CONFIG_OF_BOARD_SETUP 347 #include <libfdt.h> 348 #include <fdt_support.h> 349 350 void ft_fsl_pci_setup(void *blob, const char *pci_alias, 351 struct pci_controller *hose) 352 { 353 int off = fdt_path_offset(blob, pci_alias); 354 355 if (off >= 0) { 356 u32 bus_range[2]; 357 358 bus_range[0] = 0; 359 bus_range[1] = hose->last_busno - hose->first_busno; 360 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 361 fdt_pci_dma_ranges(blob, off, hose); 362 } 363 } 364 #endif 365