1 /* 2 * Copyright 2007-2010 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <asm/fsl_serdes.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's 28 * 29 * Initialize controller and call the common driver/pci pci_hose_scan to 30 * scan for bridges and devices. 31 * 32 * Hose fields which need to be pre-initialized by board specific code: 33 * regions[] 34 * first_busno 35 * 36 * Fields updated: 37 * last_busno 38 */ 39 40 #include <pci.h> 41 #include <asm/io.h> 42 #include <asm/fsl_pci.h> 43 44 /* Freescale-specific PCI config registers */ 45 #define FSL_PCI_PBFR 0x44 46 #define FSL_PCIE_CAP_ID 0x4c 47 #define FSL_PCIE_CFG_RDY 0x4b0 48 #define FSL_PROG_IF_AGENT 0x1 49 50 void pciauto_prescan_setup_bridge(struct pci_controller *hose, 51 pci_dev_t dev, int sub_bus); 52 void pciauto_postscan_setup_bridge(struct pci_controller *hose, 53 pci_dev_t dev, int sub_bus); 54 void pciauto_config_init(struct pci_controller *hose); 55 56 #ifndef CONFIG_SYS_PCI_MEMORY_BUS 57 #define CONFIG_SYS_PCI_MEMORY_BUS 0 58 #endif 59 60 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS 61 #define CONFIG_SYS_PCI_MEMORY_PHYS 0 62 #endif 63 64 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) 65 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) 66 #endif 67 68 /* Setup one inbound ATMU window. 69 * 70 * We let the caller decide what the window size should be 71 */ 72 static void set_inbound_window(volatile pit_t *pi, 73 struct pci_region *r, 74 u64 size) 75 { 76 u32 sz = (__ilog2_u64(size) - 1); 77 u32 flag = PIWAR_EN | PIWAR_LOCAL | 78 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 79 80 out_be32(&pi->pitar, r->phys_start >> 12); 81 out_be32(&pi->piwbar, r->bus_start >> 12); 82 #ifdef CONFIG_SYS_PCI_64BIT 83 out_be32(&pi->piwbear, r->bus_start >> 44); 84 #else 85 out_be32(&pi->piwbear, 0); 86 #endif 87 if (r->flags & PCI_REGION_PREFETCH) 88 flag |= PIWAR_PF; 89 out_be32(&pi->piwar, flag | sz); 90 } 91 92 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) 93 { 94 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; 95 96 /* Reset hose to make sure its in a clean state */ 97 memset(hose, 0, sizeof(struct pci_controller)); 98 99 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 100 101 return fsl_is_pci_agent(hose); 102 } 103 104 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, 105 u64 out_lo, u8 pcie_cap, 106 volatile pit_t *pi) 107 { 108 struct pci_region *r = hose->regions + hose->region_count; 109 u64 sz = min((u64)gd->ram_size, (1ull << 32)); 110 111 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; 112 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; 113 pci_size_t pci_sz; 114 115 /* we have no space available for inbound memory mapping */ 116 if (bus_start > out_lo) { 117 printf ("no space for inbound mapping of memory\n"); 118 return 0; 119 } 120 121 /* limit size */ 122 if ((bus_start + sz) > out_lo) { 123 sz = out_lo - bus_start; 124 debug ("limiting size to %llx\n", sz); 125 } 126 127 pci_sz = 1ull << __ilog2_u64(sz); 128 /* 129 * we can overlap inbound/outbound windows on PCI-E since RX & TX 130 * links a separate 131 */ 132 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { 133 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 134 (u64)bus_start, (u64)phys_start, (u64)sz); 135 pci_set_region(r, bus_start, phys_start, sz, 136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 137 PCI_REGION_PREFETCH); 138 139 /* if we aren't an exact power of two match, pci_sz is smaller 140 * round it up to the next power of two. We report the actual 141 * size to pci region tracking. 142 */ 143 if (pci_sz != sz) 144 sz = 2ull << __ilog2_u64(sz); 145 146 set_inbound_window(pi--, r++, sz); 147 sz = 0; /* make sure we dont set the R2 window */ 148 } else { 149 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", 150 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 151 pci_set_region(r, bus_start, phys_start, pci_sz, 152 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 153 PCI_REGION_PREFETCH); 154 set_inbound_window(pi--, r++, pci_sz); 155 156 sz -= pci_sz; 157 bus_start += pci_sz; 158 phys_start += pci_sz; 159 160 pci_sz = 1ull << __ilog2_u64(sz); 161 if (sz) { 162 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", 163 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 164 pci_set_region(r, bus_start, phys_start, pci_sz, 165 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 166 PCI_REGION_PREFETCH); 167 set_inbound_window(pi--, r++, pci_sz); 168 sz -= pci_sz; 169 bus_start += pci_sz; 170 phys_start += pci_sz; 171 } 172 } 173 174 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) 175 /* 176 * On 64-bit capable systems, set up a mapping for all of DRAM 177 * in high pci address space. 178 */ 179 pci_sz = 1ull << __ilog2_u64(gd->ram_size); 180 /* round up to the next largest power of two */ 181 if (gd->ram_size > pci_sz) 182 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); 183 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", 184 (u64)CONFIG_SYS_PCI64_MEMORY_BUS, 185 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, 186 (u64)pci_sz); 187 pci_set_region(r, 188 CONFIG_SYS_PCI64_MEMORY_BUS, 189 CONFIG_SYS_PCI_MEMORY_PHYS, 190 pci_sz, 191 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 192 PCI_REGION_PREFETCH); 193 set_inbound_window(pi--, r++, pci_sz); 194 #else 195 pci_sz = 1ull << __ilog2_u64(sz); 196 if (sz) { 197 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", 198 (u64)bus_start, (u64)phys_start, (u64)pci_sz); 199 pci_set_region(r, bus_start, phys_start, pci_sz, 200 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | 201 PCI_REGION_PREFETCH); 202 sz -= pci_sz; 203 bus_start += pci_sz; 204 phys_start += pci_sz; 205 set_inbound_window(pi--, r++, pci_sz); 206 } 207 #endif 208 209 #ifdef CONFIG_PHYS_64BIT 210 if (sz && (((u64)gd->ram_size) < (1ull << 32))) 211 printf("Was not able to map all of memory via " 212 "inbound windows -- %lld remaining\n", sz); 213 #endif 214 215 hose->region_count = r - hose->regions; 216 217 return 1; 218 } 219 220 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) 221 { 222 u16 temp16; 223 u32 temp32; 224 int enabled, r, inbound = 0; 225 u16 ltssm; 226 u8 temp8, pcie_cap; 227 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; 228 struct pci_region *reg = hose->regions + hose->region_count; 229 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 230 231 /* Initialize ATMU registers based on hose regions and flags */ 232 volatile pot_t *po = &pci->pot[1]; /* skip 0 */ 233 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ 234 235 u64 out_hi = 0, out_lo = -1ULL; 236 u32 pcicsrbar, pcicsrbar_sz; 237 238 #ifdef DEBUG 239 int neg_link_w; 240 #endif 241 242 pci_setup_indirect(hose, cfg_addr, cfg_data); 243 244 /* Handle setup of outbound windows first */ 245 for (r = 0; r < hose->region_count; r++) { 246 unsigned long flags = hose->regions[r].flags; 247 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1); 248 249 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE; 250 if (flags != PCI_REGION_SYS_MEMORY) { 251 u64 start = hose->regions[r].bus_start; 252 u64 end = start + hose->regions[r].size; 253 254 out_be32(&po->powbar, hose->regions[r].phys_start >> 12); 255 out_be32(&po->potar, start >> 12); 256 #ifdef CONFIG_SYS_PCI_64BIT 257 out_be32(&po->potear, start >> 44); 258 #else 259 out_be32(&po->potear, 0); 260 #endif 261 if (hose->regions[r].flags & PCI_REGION_IO) { 262 out_be32(&po->powar, POWAR_EN | sz | 263 POWAR_IO_READ | POWAR_IO_WRITE); 264 } else { 265 out_be32(&po->powar, POWAR_EN | sz | 266 POWAR_MEM_READ | POWAR_MEM_WRITE); 267 out_lo = min(start, out_lo); 268 out_hi = max(end, out_hi); 269 } 270 po++; 271 } 272 } 273 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi); 274 275 /* setup PCSRBAR/PEXCSRBAR */ 276 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); 277 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 278 pcicsrbar_sz = ~pcicsrbar_sz + 1; 279 280 if (out_hi < (0x100000000ull - pcicsrbar_sz) || 281 (out_lo > 0x100000000ull)) 282 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 283 else 284 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz; 285 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar); 286 287 out_lo = min(out_lo, (u64)pcicsrbar); 288 289 debug("PCICSRBAR @ 0x%x\n", pcicsrbar); 290 291 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS, 292 pcicsrbar_sz, PCI_REGION_SYS_MEMORY); 293 hose->region_count++; 294 295 /* see if we are a PCIe or PCI controller */ 296 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 297 298 /* inbound */ 299 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); 300 301 for (r = 0; r < hose->region_count; r++) 302 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r, 303 (u64)hose->regions[r].phys_start, 304 hose->regions[r].bus_start, 305 hose->regions[r].size, 306 hose->regions[r].flags); 307 308 pci_register_hose(hose); 309 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ 310 hose->current_busno = hose->first_busno; 311 312 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */ 313 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except 314 * - Master abort (pci) 315 * - Master PERR (pci) 316 * - ICCA (PCIe) 317 */ 318 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); 319 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ 320 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); 321 322 if (pcie_cap == PCI_CAP_ID_EXP) { 323 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); 324 enabled = ltssm >= PCI_LTSSM_L0; 325 326 #ifdef CONFIG_FSL_PCIE_RESET 327 if (ltssm == 1) { 328 int i; 329 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm); 330 /* assert PCIe reset */ 331 setbits_be32(&pci->pdb_stat, 0x08000000); 332 (void) in_be32(&pci->pdb_stat); 333 udelay(100); 334 debug(" Asserting PCIe reset @%x = %x\n", 335 &pci->pdb_stat, in_be32(&pci->pdb_stat)); 336 /* clear PCIe reset */ 337 clrbits_be32(&pci->pdb_stat, 0x08000000); 338 asm("sync;isync"); 339 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) { 340 pci_hose_read_config_word(hose, dev, PCI_LTSSM, 341 <ssm); 342 udelay(1000); 343 debug("....PCIe link error. " 344 "LTSSM=0x%02x.\n", ltssm); 345 } 346 enabled = ltssm >= PCI_LTSSM_L0; 347 348 /* we need to re-write the bar0 since a reset will 349 * clear it 350 */ 351 pci_hose_write_config_dword(hose, dev, 352 PCI_BASE_ADDRESS_0, pcicsrbar); 353 } 354 #endif 355 356 if (!enabled) { 357 debug("....PCIE link error. Skipping scan." 358 "LTSSM=0x%02x\n", ltssm); 359 hose->last_busno = hose->first_busno; 360 return; 361 } 362 363 out_be32(&pci->pme_msg_det, 0xffffffff); 364 out_be32(&pci->pme_msg_int_en, 0xffffffff); 365 #ifdef DEBUG 366 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); 367 neg_link_w = (temp16 & 0x3f0 ) >> 4; 368 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", 369 ltssm, neg_link_w); 370 #endif 371 hose->current_busno++; /* Start scan with secondary */ 372 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); 373 } 374 375 /* Use generic setup_device to initialize standard pci regs, 376 * but do not allocate any windows since any BAR found (such 377 * as PCSRBAR) is not in this cpu's memory space. 378 */ 379 pciauto_setup_device(hose, dev, 0, hose->pci_mem, 380 hose->pci_prefetch, hose->pci_io); 381 382 if (inbound) { 383 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); 384 pci_hose_write_config_word(hose, dev, PCI_COMMAND, 385 temp16 | PCI_COMMAND_MEMORY); 386 } 387 388 #ifndef CONFIG_PCI_NOSCAN 389 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); 390 391 /* Programming Interface (PCI_CLASS_PROG) 392 * 0 == pci host or pcie root-complex, 393 * 1 == pci agent or pcie end-point 394 */ 395 if (!temp8) { 396 debug(" Scanning PCI bus %02x\n", 397 hose->current_busno); 398 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); 399 } else { 400 debug(" Not scanning PCI bus %02x. PI=%x\n", 401 hose->current_busno, temp8); 402 hose->last_busno = hose->current_busno; 403 } 404 405 /* if we are PCIe - update limit regs and subordinate busno 406 * for the virtual P2P bridge 407 */ 408 if (pcie_cap == PCI_CAP_ID_EXP) { 409 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); 410 } 411 #else 412 hose->last_busno = hose->current_busno; 413 #endif 414 415 /* Clear all error indications */ 416 if (pcie_cap == PCI_CAP_ID_EXP) 417 out_be32(&pci->pme_msg_det, 0xffffffff); 418 out_be32(&pci->pedr, 0xffffffff); 419 420 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); 421 if (temp16) { 422 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); 423 } 424 425 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); 426 if (temp16) { 427 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); 428 } 429 } 430 431 int fsl_is_pci_agent(struct pci_controller *hose) 432 { 433 u8 prog_if; 434 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); 435 436 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); 437 438 return (prog_if == FSL_PROG_IF_AGENT); 439 } 440 441 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 442 struct pci_controller *hose, int busno) 443 { 444 volatile ccsr_fsl_pci_t *pci; 445 struct pci_region *r; 446 pci_dev_t dev = PCI_BDF(busno,0,0); 447 u8 pcie_cap; 448 449 pci = (ccsr_fsl_pci_t *) pci_info->regs; 450 451 /* on non-PCIe controllers we don't have pme_msg_det so this code 452 * should do nothing since the read will return 0 453 */ 454 if (in_be32(&pci->pme_msg_det)) { 455 out_be32(&pci->pme_msg_det, 0xffffffff); 456 debug (" with errors. Clearing. Now 0x%08x", 457 pci->pme_msg_det); 458 } 459 460 r = hose->regions + hose->region_count; 461 462 /* outbound memory */ 463 pci_set_region(r++, 464 pci_info->mem_bus, 465 pci_info->mem_phys, 466 pci_info->mem_size, 467 PCI_REGION_MEM); 468 469 /* outbound io */ 470 pci_set_region(r++, 471 pci_info->io_bus, 472 pci_info->io_phys, 473 pci_info->io_size, 474 PCI_REGION_IO); 475 476 hose->region_count = r - hose->regions; 477 hose->first_busno = busno; 478 479 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 480 481 if (fsl_is_pci_agent(hose)) { 482 fsl_pci_config_unlock(hose); 483 hose->last_busno = hose->first_busno; 484 } 485 486 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 487 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? 488 "E" : "", pci_info->pci_num, 489 hose->first_busno, hose->last_busno); 490 491 return(hose->last_busno + 1); 492 } 493 494 /* Enable inbound PCI config cycles for agent/endpoint interface */ 495 void fsl_pci_config_unlock(struct pci_controller *hose) 496 { 497 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); 498 u8 agent; 499 u8 pcie_cap; 500 u16 pbfr; 501 502 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); 503 if (!agent) 504 return; 505 506 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); 507 if (pcie_cap != 0x0) { 508 /* PCIe - set CFG_READY bit of Configuration Ready Register */ 509 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); 510 } else { 511 /* PCI - clear ACL bit of PBFR */ 512 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); 513 pbfr &= ~0x20; 514 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); 515 } 516 } 517 518 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ 519 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) 520 int fsl_configure_pcie(struct fsl_pci_info *info, 521 struct pci_controller *hose, 522 const char *connected, int busno) 523 { 524 int is_endpoint; 525 526 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); 527 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); 528 is_endpoint = fsl_setup_hose(hose, info->regs); 529 printf("PCIE%u: connected to %s as %s (base addr %lx)\n", 530 info->pci_num, connected, 531 is_endpoint ? "Endpoint" : "Root Complex", info->regs); 532 return fsl_pci_init_port(info, hose, busno); 533 } 534 535 #if defined(CONFIG_FSL_CORENET) 536 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 537 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 538 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 539 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 540 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 541 #elif defined(CONFIG_MPC85xx) 542 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE 543 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 544 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 545 #define _DEVDISR_PCIE4 0 546 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 547 #elif defined(CONFIG_MPC86xx) 548 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 549 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 550 #define _DEVDISR_PCIE3 0 551 #define _DEVDISR_PCIE4 0 552 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 553 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 554 #else 555 #error "No defines for DEVDISR_PCIE" 556 #endif 557 558 /* Implement a dummy function for those platforms w/o SERDES */ 559 static const char *__board_serdes_name(enum srds_prtcl device) 560 { 561 switch (device) { 562 #ifdef CONFIG_SYS_PCIE1_NAME 563 case PCIE1: 564 return CONFIG_SYS_PCIE1_NAME; 565 #endif 566 #ifdef CONFIG_SYS_PCIE2_NAME 567 case PCIE2: 568 return CONFIG_SYS_PCIE2_NAME; 569 #endif 570 #ifdef CONFIG_SYS_PCIE3_NAME 571 case PCIE3: 572 return CONFIG_SYS_PCIE3_NAME; 573 #endif 574 #ifdef CONFIG_SYS_PCIE4_NAME 575 case PCIE4: 576 return CONFIG_SYS_PCIE4_NAME; 577 #endif 578 default: 579 return NULL; 580 } 581 582 return NULL; 583 } 584 585 __attribute__((weak, alias("__board_serdes_name"))) const char * 586 board_serdes_name(enum srds_prtcl device); 587 588 static u32 devdisr_mask[] = { 589 _DEVDISR_PCIE1, 590 _DEVDISR_PCIE2, 591 _DEVDISR_PCIE3, 592 _DEVDISR_PCIE4, 593 }; 594 595 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 596 struct fsl_pci_info *pci_info) 597 { 598 struct pci_controller *hose; 599 int num = dev - PCIE1; 600 601 hose = calloc(1, sizeof(struct pci_controller)); 602 if (!hose) 603 return busno; 604 605 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { 606 busno = fsl_configure_pcie(pci_info, hose, 607 board_serdes_name(dev), busno); 608 } else { 609 printf("PCIE%d: disabled\n", num + 1); 610 } 611 612 return busno; 613 } 614 615 int fsl_pcie_init_board(int busno) 616 { 617 struct fsl_pci_info pci_info; 618 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 619 u32 devdisr = in_be32(&gur->devdisr); 620 621 #ifdef CONFIG_PCIE1 622 SET_STD_PCIE_INFO(pci_info, 1); 623 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); 624 #else 625 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ 626 #endif 627 628 #ifdef CONFIG_PCIE2 629 SET_STD_PCIE_INFO(pci_info, 2); 630 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); 631 #else 632 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ 633 #endif 634 635 #ifdef CONFIG_PCIE3 636 SET_STD_PCIE_INFO(pci_info, 3); 637 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); 638 #else 639 setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ 640 #endif 641 642 #ifdef CONFIG_PCIE4 643 SET_STD_PCIE_INFO(pci_info, 4); 644 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); 645 #else 646 setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ 647 #endif 648 649 return busno; 650 } 651 #else 652 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 653 struct fsl_pci_info *pci_info) 654 { 655 return busno; 656 } 657 658 int fsl_pcie_init_board(int busno) 659 { 660 return busno; 661 } 662 #endif 663 664 #ifdef CONFIG_OF_BOARD_SETUP 665 #include <libfdt.h> 666 #include <fdt_support.h> 667 668 void ft_fsl_pci_setup(void *blob, const char *pci_compat, 669 unsigned long ctrl_addr) 670 { 671 int off; 672 u32 bus_range[2]; 673 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; 674 struct pci_controller *hose; 675 676 hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); 677 678 /* convert ctrl_addr to true physical address */ 679 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; 680 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS; 681 682 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr); 683 684 if (off < 0) 685 return; 686 687 /* We assume a cfg_addr not being set means we didn't setup the controller */ 688 if ((hose == NULL) || (hose->cfg_addr == NULL)) { 689 fdt_del_node(blob, off); 690 } else { 691 bus_range[0] = 0; 692 bus_range[1] = hose->last_busno - hose->first_busno; 693 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4); 694 fdt_pci_dma_ranges(blob, off, hose); 695 } 696 } 697 #endif 698