1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <config.h> 16 #include <fdtdec.h> 17 #include <libfdt.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <watchdog.h> 23 #include <asm/system.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/sys_proto.h> 26 27 #if !defined(CONFIG_PHYLIB) 28 # error XILINX_GEM_ETHERNET requires PHYLIB 29 #endif 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 50 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 51 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 52 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 53 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 54 55 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 56 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 57 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 58 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 61 62 #ifdef CONFIG_ARM64 63 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 64 #else 65 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 66 #endif 67 68 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 69 ZYNQ_GEM_NWCFG_FDEN | \ 70 ZYNQ_GEM_NWCFG_FSREM | \ 71 ZYNQ_GEM_NWCFG_MDCCLKDIV) 72 73 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 74 75 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 76 /* Use full configured addressable space (8 Kb) */ 77 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 78 /* Use full configured addressable space (4 Kb) */ 79 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 80 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 81 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 82 83 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 84 ZYNQ_GEM_DMACR_RXSIZE | \ 85 ZYNQ_GEM_DMACR_TXSIZE | \ 86 ZYNQ_GEM_DMACR_RXBUF) 87 88 /* Use MII register 1 (MII status register) to detect PHY */ 89 #define PHY_DETECT_REG 1 90 91 /* Mask used to verify certain PHY features (or register contents) 92 * in the register above: 93 * 0x1000: 10Mbps full duplex support 94 * 0x0800: 10Mbps half duplex support 95 * 0x0008: Auto-negotiation support 96 */ 97 #define PHY_DETECT_MASK 0x1808 98 99 /* TX BD status masks */ 100 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 101 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 102 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 103 104 /* Clock frequencies for different speeds */ 105 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 106 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 107 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 108 109 /* Device registers */ 110 struct zynq_gem_regs { 111 u32 nwctrl; /* 0x0 - Network Control reg */ 112 u32 nwcfg; /* 0x4 - Network Config reg */ 113 u32 nwsr; /* 0x8 - Network Status reg */ 114 u32 reserved1; 115 u32 dmacr; /* 0x10 - DMA Control reg */ 116 u32 txsr; /* 0x14 - TX Status reg */ 117 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 118 u32 txqbase; /* 0x1c - TX Q Base address reg */ 119 u32 rxsr; /* 0x20 - RX Status reg */ 120 u32 reserved2[2]; 121 u32 idr; /* 0x2c - Interrupt Disable reg */ 122 u32 reserved3; 123 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 124 u32 reserved4[18]; 125 u32 hashl; /* 0x80 - Hash Low address reg */ 126 u32 hashh; /* 0x84 - Hash High address reg */ 127 #define LADDR_LOW 0 128 #define LADDR_HIGH 1 129 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 130 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 131 u32 reserved6[18]; 132 #define STAT_SIZE 44 133 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 134 }; 135 136 /* BD descriptors */ 137 struct emac_bd { 138 u32 addr; /* Next descriptor pointer */ 139 u32 status; 140 }; 141 142 #define RX_BUF 32 143 /* Page table entries are set to 1MB, or multiples of 1MB 144 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 145 */ 146 #define BD_SPACE 0x100000 147 /* BD separation space */ 148 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 149 150 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 151 struct zynq_gem_priv { 152 struct emac_bd *tx_bd; 153 struct emac_bd *rx_bd; 154 char *rxbuffers; 155 u32 rxbd_current; 156 u32 rx_first_buf; 157 int phyaddr; 158 u32 emio; 159 int init; 160 phy_interface_t interface; 161 struct phy_device *phydev; 162 struct mii_dev *bus; 163 }; 164 165 static inline int mdio_wait(struct eth_device *dev) 166 { 167 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 168 u32 timeout = 20000; 169 170 /* Wait till MDIO interface is ready to accept a new transaction. */ 171 while (--timeout) { 172 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 173 break; 174 WATCHDOG_RESET(); 175 } 176 177 if (!timeout) { 178 printf("%s: Timeout\n", __func__); 179 return 1; 180 } 181 182 return 0; 183 } 184 185 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 186 u32 op, u16 *data) 187 { 188 u32 mgtcr; 189 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 190 191 if (mdio_wait(dev)) 192 return 1; 193 194 /* Construct mgtcr mask for the operation */ 195 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 196 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 197 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 198 199 /* Write mgtcr and wait for completion */ 200 writel(mgtcr, ®s->phymntnc); 201 202 if (mdio_wait(dev)) 203 return 1; 204 205 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 206 *data = readl(®s->phymntnc); 207 208 return 0; 209 } 210 211 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 212 { 213 u32 ret; 214 215 ret = phy_setup_op(dev, phy_addr, regnum, 216 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 217 218 if (!ret) 219 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 220 phy_addr, regnum, *val); 221 222 return ret; 223 } 224 225 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 226 { 227 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 228 regnum, data); 229 230 return phy_setup_op(dev, phy_addr, regnum, 231 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 232 } 233 234 static void phy_detection(struct eth_device *dev) 235 { 236 int i; 237 u16 phyreg; 238 struct zynq_gem_priv *priv = dev->priv; 239 240 if (priv->phyaddr != -1) { 241 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 242 if ((phyreg != 0xFFFF) && 243 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 244 /* Found a valid PHY address */ 245 debug("Default phy address %d is valid\n", 246 priv->phyaddr); 247 return; 248 } else { 249 debug("PHY address is not setup correctly %d\n", 250 priv->phyaddr); 251 priv->phyaddr = -1; 252 } 253 } 254 255 debug("detecting phy address\n"); 256 if (priv->phyaddr == -1) { 257 /* detect the PHY address */ 258 for (i = 31; i >= 0; i--) { 259 phyread(dev, i, PHY_DETECT_REG, &phyreg); 260 if ((phyreg != 0xFFFF) && 261 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 262 /* Found a valid PHY address */ 263 priv->phyaddr = i; 264 debug("Found valid phy address, %d\n", i); 265 return; 266 } 267 } 268 } 269 printf("PHY is not detected\n"); 270 } 271 272 static int zynq_gem_setup_mac(struct eth_device *dev) 273 { 274 u32 i, macaddrlow, macaddrhigh; 275 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 276 277 /* Set the MAC bits [31:0] in BOT */ 278 macaddrlow = dev->enetaddr[0]; 279 macaddrlow |= dev->enetaddr[1] << 8; 280 macaddrlow |= dev->enetaddr[2] << 16; 281 macaddrlow |= dev->enetaddr[3] << 24; 282 283 /* Set MAC bits [47:32] in TOP */ 284 macaddrhigh = dev->enetaddr[4]; 285 macaddrhigh |= dev->enetaddr[5] << 8; 286 287 for (i = 0; i < 4; i++) { 288 writel(0, ®s->laddr[i][LADDR_LOW]); 289 writel(0, ®s->laddr[i][LADDR_HIGH]); 290 /* Do not use MATCHx register */ 291 writel(0, ®s->match[i]); 292 } 293 294 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 295 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 296 297 return 0; 298 } 299 300 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 301 { 302 u32 i; 303 unsigned long clk_rate = 0; 304 struct phy_device *phydev; 305 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 306 struct zynq_gem_priv *priv = dev->priv; 307 const u32 supported = SUPPORTED_10baseT_Half | 308 SUPPORTED_10baseT_Full | 309 SUPPORTED_100baseT_Half | 310 SUPPORTED_100baseT_Full | 311 SUPPORTED_1000baseT_Half | 312 SUPPORTED_1000baseT_Full; 313 314 if (!priv->init) { 315 /* Disable all interrupts */ 316 writel(0xFFFFFFFF, ®s->idr); 317 318 /* Disable the receiver & transmitter */ 319 writel(0, ®s->nwctrl); 320 writel(0, ®s->txsr); 321 writel(0, ®s->rxsr); 322 writel(0, ®s->phymntnc); 323 324 /* Clear the Hash registers for the mac address 325 * pointed by AddressPtr 326 */ 327 writel(0x0, ®s->hashl); 328 /* Write bits [63:32] in TOP */ 329 writel(0x0, ®s->hashh); 330 331 /* Clear all counters */ 332 for (i = 0; i < STAT_SIZE; i++) 333 readl(®s->stat[i]); 334 335 /* Setup RxBD space */ 336 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 337 338 for (i = 0; i < RX_BUF; i++) { 339 priv->rx_bd[i].status = 0xF0000000; 340 priv->rx_bd[i].addr = 341 ((ulong)(priv->rxbuffers) + 342 (i * PKTSIZE_ALIGN)); 343 } 344 /* WRAP bit to last BD */ 345 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 346 /* Write RxBDs to IP */ 347 writel((ulong)priv->rx_bd, ®s->rxqbase); 348 349 /* Setup for DMA Configuration register */ 350 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 351 352 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 353 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 354 355 priv->init++; 356 } 357 358 phy_detection(dev); 359 360 /* interface - look at tsec */ 361 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 362 priv->interface); 363 364 phydev->supported = supported | ADVERTISED_Pause | 365 ADVERTISED_Asym_Pause; 366 phydev->advertising = phydev->supported; 367 priv->phydev = phydev; 368 phy_config(phydev); 369 phy_startup(phydev); 370 371 if (!phydev->link) { 372 printf("%s: No link.\n", phydev->dev->name); 373 return -1; 374 } 375 376 switch (phydev->speed) { 377 case SPEED_1000: 378 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 379 ®s->nwcfg); 380 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 381 break; 382 case SPEED_100: 383 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 384 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 385 clk_rate = ZYNQ_GEM_FREQUENCY_100; 386 break; 387 case SPEED_10: 388 clk_rate = ZYNQ_GEM_FREQUENCY_10; 389 break; 390 } 391 392 /* Change the rclk and clk only not using EMIO interface */ 393 if (!priv->emio) 394 zynq_slcr_gem_clk_setup(dev->iobase != 395 ZYNQ_GEM_BASEADDR0, clk_rate); 396 397 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 398 ZYNQ_GEM_NWCTRL_TXEN_MASK); 399 400 return 0; 401 } 402 403 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 404 { 405 u32 addr, size; 406 struct zynq_gem_priv *priv = dev->priv; 407 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 408 409 /* setup BD */ 410 writel((ulong)priv->tx_bd, ®s->txqbase); 411 412 /* Setup Tx BD */ 413 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 414 415 priv->tx_bd->addr = (ulong)ptr; 416 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 417 ZYNQ_GEM_TXBUF_LAST_MASK | 418 ZYNQ_GEM_TXBUF_WRAP_MASK; 419 420 addr = (ulong) ptr; 421 addr &= ~(ARCH_DMA_MINALIGN - 1); 422 size = roundup(len, ARCH_DMA_MINALIGN); 423 flush_dcache_range(addr, addr + size); 424 425 addr = (ulong)priv->rxbuffers; 426 addr &= ~(ARCH_DMA_MINALIGN - 1); 427 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 428 flush_dcache_range(addr, addr + size); 429 barrier(); 430 431 /* Start transmit */ 432 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 433 434 /* Read TX BD status */ 435 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) 436 printf("TX underrun\n"); 437 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 438 printf("TX buffers exhausted in mid frame\n"); 439 440 return 0; 441 } 442 443 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 444 static int zynq_gem_recv(struct eth_device *dev) 445 { 446 int frame_len; 447 struct zynq_gem_priv *priv = dev->priv; 448 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 449 struct emac_bd *first_bd; 450 451 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 452 return 0; 453 454 if (!(current_bd->status & 455 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 456 printf("GEM: SOF or EOF not set for last buffer received!\n"); 457 return 0; 458 } 459 460 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 461 if (frame_len) { 462 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 463 addr &= ~(ARCH_DMA_MINALIGN - 1); 464 465 net_process_received_packet((u8 *)(ulong)addr, frame_len); 466 467 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 468 priv->rx_first_buf = priv->rxbd_current; 469 else { 470 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 471 current_bd->status = 0xF0000000; /* FIXME */ 472 } 473 474 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 475 first_bd = &priv->rx_bd[priv->rx_first_buf]; 476 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 477 first_bd->status = 0xF0000000; 478 } 479 480 if ((++priv->rxbd_current) >= RX_BUF) 481 priv->rxbd_current = 0; 482 } 483 484 return frame_len; 485 } 486 487 static void zynq_gem_halt(struct eth_device *dev) 488 { 489 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 490 491 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 492 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 493 } 494 495 static int zynq_gem_miiphyread(const char *devname, uchar addr, 496 uchar reg, ushort *val) 497 { 498 struct eth_device *dev = eth_get_dev(); 499 int ret; 500 501 ret = phyread(dev, addr, reg, val); 502 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 503 return ret; 504 } 505 506 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 507 uchar reg, ushort val) 508 { 509 struct eth_device *dev = eth_get_dev(); 510 511 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 512 return phywrite(dev, addr, reg, val); 513 } 514 515 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 516 int phy_addr, u32 emio) 517 { 518 struct eth_device *dev; 519 struct zynq_gem_priv *priv; 520 void *bd_space; 521 522 dev = calloc(1, sizeof(*dev)); 523 if (dev == NULL) 524 return -1; 525 526 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 527 if (dev->priv == NULL) { 528 free(dev); 529 return -1; 530 } 531 priv = dev->priv; 532 533 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 534 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 535 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 536 537 /* Align bd_space to MMU_SECTION_SHIFT */ 538 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 539 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 540 BD_SPACE, DCACHE_OFF); 541 542 /* Initialize the bd spaces for tx and rx bd's */ 543 priv->tx_bd = (struct emac_bd *)bd_space; 544 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 545 546 priv->phyaddr = phy_addr; 547 priv->emio = emio; 548 549 #ifndef CONFIG_ZYNQ_GEM_INTERFACE 550 priv->interface = PHY_INTERFACE_MODE_MII; 551 #else 552 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 553 #endif 554 555 sprintf(dev->name, "Gem.%lx", base_addr); 556 557 dev->iobase = base_addr; 558 559 dev->init = zynq_gem_init; 560 dev->halt = zynq_gem_halt; 561 dev->send = zynq_gem_send; 562 dev->recv = zynq_gem_recv; 563 dev->write_hwaddr = zynq_gem_setup_mac; 564 565 eth_register(dev); 566 567 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 568 priv->bus = miiphy_get_dev_by_name(dev->name); 569 570 return 1; 571 } 572 573 #if CONFIG_IS_ENABLED(OF_CONTROL) 574 int zynq_gem_of_init(const void *blob) 575 { 576 int offset = 0; 577 u32 ret = 0; 578 u32 reg, phy_reg; 579 580 debug("ZYNQ GEM: Initialization\n"); 581 582 do { 583 offset = fdt_node_offset_by_compatible(blob, offset, 584 "xlnx,ps7-ethernet-1.00.a"); 585 if (offset != -1) { 586 reg = fdtdec_get_addr(blob, offset, "reg"); 587 if (reg != FDT_ADDR_T_NONE) { 588 offset = fdtdec_lookup_phandle(blob, offset, 589 "phy-handle"); 590 if (offset != -1) 591 phy_reg = fdtdec_get_addr(blob, offset, 592 "reg"); 593 else 594 phy_reg = 0; 595 596 debug("ZYNQ GEM: addr %x, phyaddr %x\n", 597 reg, phy_reg); 598 599 ret |= zynq_gem_initialize(NULL, reg, 600 phy_reg, 0); 601 602 } else { 603 debug("ZYNQ GEM: Can't get base address\n"); 604 return -1; 605 } 606 } 607 } while (offset != -1); 608 609 return ret; 610 } 611 #endif 612