1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <clk.h> 13 #include <common.h> 14 #include <dm.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <config.h> 18 #include <console.h> 19 #include <malloc.h> 20 #include <asm/io.h> 21 #include <phy.h> 22 #include <miiphy.h> 23 #include <wait_bit.h> 24 #include <watchdog.h> 25 #include <asm/system.h> 26 #include <asm/arch/hardware.h> 27 #include <asm/arch/sys_proto.h> 28 #include <linux/errno.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* Bit/mask specification */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38 39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42 43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46 47 /* Wrap bit, last descriptor */ 48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51 52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56 57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 63 #ifdef CONFIG_ARM64 64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 65 #else 66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 67 #endif 68 69 #ifdef CONFIG_ARM64 70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 71 #else 72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 73 #endif 74 75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 76 ZYNQ_GEM_NWCFG_FDEN | \ 77 ZYNQ_GEM_NWCFG_FSREM | \ 78 ZYNQ_GEM_NWCFG_MDCCLKDIV) 79 80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 81 82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 83 /* Use full configured addressable space (8 Kb) */ 84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 85 /* Use full configured addressable space (4 Kb) */ 86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 89 90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 91 ZYNQ_GEM_DMACR_RXSIZE | \ 92 ZYNQ_GEM_DMACR_TXSIZE | \ 93 ZYNQ_GEM_DMACR_RXBUF) 94 95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 96 97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 98 99 /* Use MII register 1 (MII status register) to detect PHY */ 100 #define PHY_DETECT_REG 1 101 102 /* Mask used to verify certain PHY features (or register contents) 103 * in the register above: 104 * 0x1000: 10Mbps full duplex support 105 * 0x0800: 10Mbps half duplex support 106 * 0x0008: Auto-negotiation support 107 */ 108 #define PHY_DETECT_MASK 0x1808 109 110 /* TX BD status masks */ 111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 114 115 /* Clock frequencies for different speeds */ 116 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 117 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 119 120 /* Device registers */ 121 struct zynq_gem_regs { 122 u32 nwctrl; /* 0x0 - Network Control reg */ 123 u32 nwcfg; /* 0x4 - Network Config reg */ 124 u32 nwsr; /* 0x8 - Network Status reg */ 125 u32 reserved1; 126 u32 dmacr; /* 0x10 - DMA Control reg */ 127 u32 txsr; /* 0x14 - TX Status reg */ 128 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 129 u32 txqbase; /* 0x1c - TX Q Base address reg */ 130 u32 rxsr; /* 0x20 - RX Status reg */ 131 u32 reserved2[2]; 132 u32 idr; /* 0x2c - Interrupt Disable reg */ 133 u32 reserved3; 134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 135 u32 reserved4[18]; 136 u32 hashl; /* 0x80 - Hash Low address reg */ 137 u32 hashh; /* 0x84 - Hash High address reg */ 138 #define LADDR_LOW 0 139 #define LADDR_HIGH 1 140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 142 u32 reserved6[18]; 143 #define STAT_SIZE 44 144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 145 u32 reserved9[20]; 146 u32 pcscntrl; 147 u32 reserved7[143]; 148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 149 u32 reserved8[15]; 150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 151 }; 152 153 /* BD descriptors */ 154 struct emac_bd { 155 u32 addr; /* Next descriptor pointer */ 156 u32 status; 157 }; 158 159 #define RX_BUF 32 160 /* Page table entries are set to 1MB, or multiples of 1MB 161 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 162 */ 163 #define BD_SPACE 0x100000 164 /* BD separation space */ 165 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 166 167 /* Setup the first free TX descriptor */ 168 #define TX_FREE_DESC 2 169 170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 171 struct zynq_gem_priv { 172 struct emac_bd *tx_bd; 173 struct emac_bd *rx_bd; 174 char *rxbuffers; 175 u32 rxbd_current; 176 u32 rx_first_buf; 177 int phyaddr; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) 185 struct clk clk; 186 #endif 187 }; 188 189 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 190 u32 op, u16 *data) 191 { 192 u32 mgtcr; 193 struct zynq_gem_regs *regs = priv->iobase; 194 int err; 195 196 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 197 true, 20000, true); 198 if (err) 199 return err; 200 201 /* Construct mgtcr mask for the operation */ 202 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 203 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 204 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 205 206 /* Write mgtcr and wait for completion */ 207 writel(mgtcr, ®s->phymntnc); 208 209 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 210 true, 20000, true); 211 if (err) 212 return err; 213 214 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 215 *data = readl(®s->phymntnc); 216 217 return 0; 218 } 219 220 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 221 u32 regnum, u16 *val) 222 { 223 u32 ret; 224 225 ret = phy_setup_op(priv, phy_addr, regnum, 226 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 227 228 if (!ret) 229 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 230 phy_addr, regnum, *val); 231 232 return ret; 233 } 234 235 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 236 u32 regnum, u16 data) 237 { 238 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 239 regnum, data); 240 241 return phy_setup_op(priv, phy_addr, regnum, 242 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 243 } 244 245 static int phy_detection(struct udevice *dev) 246 { 247 int i; 248 u16 phyreg; 249 struct zynq_gem_priv *priv = dev->priv; 250 251 if (priv->phyaddr != -1) { 252 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 253 if ((phyreg != 0xFFFF) && 254 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 255 /* Found a valid PHY address */ 256 debug("Default phy address %d is valid\n", 257 priv->phyaddr); 258 return 0; 259 } else { 260 debug("PHY address is not setup correctly %d\n", 261 priv->phyaddr); 262 priv->phyaddr = -1; 263 } 264 } 265 266 debug("detecting phy address\n"); 267 if (priv->phyaddr == -1) { 268 /* detect the PHY address */ 269 for (i = 31; i >= 0; i--) { 270 phyread(priv, i, PHY_DETECT_REG, &phyreg); 271 if ((phyreg != 0xFFFF) && 272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 273 /* Found a valid PHY address */ 274 priv->phyaddr = i; 275 debug("Found valid phy address, %d\n", i); 276 return 0; 277 } 278 } 279 } 280 printf("PHY is not detected\n"); 281 return -1; 282 } 283 284 static int zynq_gem_setup_mac(struct udevice *dev) 285 { 286 u32 i, macaddrlow, macaddrhigh; 287 struct eth_pdata *pdata = dev_get_platdata(dev); 288 struct zynq_gem_priv *priv = dev_get_priv(dev); 289 struct zynq_gem_regs *regs = priv->iobase; 290 291 /* Set the MAC bits [31:0] in BOT */ 292 macaddrlow = pdata->enetaddr[0]; 293 macaddrlow |= pdata->enetaddr[1] << 8; 294 macaddrlow |= pdata->enetaddr[2] << 16; 295 macaddrlow |= pdata->enetaddr[3] << 24; 296 297 /* Set MAC bits [47:32] in TOP */ 298 macaddrhigh = pdata->enetaddr[4]; 299 macaddrhigh |= pdata->enetaddr[5] << 8; 300 301 for (i = 0; i < 4; i++) { 302 writel(0, ®s->laddr[i][LADDR_LOW]); 303 writel(0, ®s->laddr[i][LADDR_HIGH]); 304 /* Do not use MATCHx register */ 305 writel(0, ®s->match[i]); 306 } 307 308 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 309 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 310 311 return 0; 312 } 313 314 static int zynq_phy_init(struct udevice *dev) 315 { 316 int ret; 317 struct zynq_gem_priv *priv = dev_get_priv(dev); 318 struct zynq_gem_regs *regs = priv->iobase; 319 const u32 supported = SUPPORTED_10baseT_Half | 320 SUPPORTED_10baseT_Full | 321 SUPPORTED_100baseT_Half | 322 SUPPORTED_100baseT_Full | 323 SUPPORTED_1000baseT_Half | 324 SUPPORTED_1000baseT_Full; 325 326 /* Enable only MDIO bus */ 327 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 328 329 if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 330 ret = phy_detection(dev); 331 if (ret) { 332 printf("GEM PHY init failed\n"); 333 return ret; 334 } 335 } 336 337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 338 priv->interface); 339 if (!priv->phydev) 340 return -ENODEV; 341 342 priv->phydev->supported = supported | ADVERTISED_Pause | 343 ADVERTISED_Asym_Pause; 344 priv->phydev->advertising = priv->phydev->supported; 345 346 if (priv->phy_of_handle > 0) 347 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); 348 349 return phy_config(priv->phydev); 350 } 351 352 static int zynq_gem_init(struct udevice *dev) 353 { 354 u32 i, nwconfig; 355 int ret; 356 unsigned long clk_rate = 0; 357 struct zynq_gem_priv *priv = dev_get_priv(dev); 358 struct zynq_gem_regs *regs = priv->iobase; 359 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 360 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 361 362 if (!priv->init) { 363 /* Disable all interrupts */ 364 writel(0xFFFFFFFF, ®s->idr); 365 366 /* Disable the receiver & transmitter */ 367 writel(0, ®s->nwctrl); 368 writel(0, ®s->txsr); 369 writel(0, ®s->rxsr); 370 writel(0, ®s->phymntnc); 371 372 /* Clear the Hash registers for the mac address 373 * pointed by AddressPtr 374 */ 375 writel(0x0, ®s->hashl); 376 /* Write bits [63:32] in TOP */ 377 writel(0x0, ®s->hashh); 378 379 /* Clear all counters */ 380 for (i = 0; i < STAT_SIZE; i++) 381 readl(®s->stat[i]); 382 383 /* Setup RxBD space */ 384 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 385 386 for (i = 0; i < RX_BUF; i++) { 387 priv->rx_bd[i].status = 0xF0000000; 388 priv->rx_bd[i].addr = 389 ((ulong)(priv->rxbuffers) + 390 (i * PKTSIZE_ALIGN)); 391 } 392 /* WRAP bit to last BD */ 393 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 394 /* Write RxBDs to IP */ 395 writel((ulong)priv->rx_bd, ®s->rxqbase); 396 397 /* Setup for DMA Configuration register */ 398 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 399 400 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 401 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 402 403 /* Disable the second priority queue */ 404 dummy_tx_bd->addr = 0; 405 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 406 ZYNQ_GEM_TXBUF_LAST_MASK| 407 ZYNQ_GEM_TXBUF_USED_MASK; 408 409 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 410 ZYNQ_GEM_RXBUF_NEW_MASK; 411 dummy_rx_bd->status = 0; 412 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 413 sizeof(dummy_tx_bd)); 414 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 415 sizeof(dummy_rx_bd)); 416 417 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 418 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 419 420 priv->init++; 421 } 422 423 ret = phy_startup(priv->phydev); 424 if (ret) 425 return ret; 426 427 if (!priv->phydev->link) { 428 printf("%s: No link.\n", priv->phydev->dev->name); 429 return -1; 430 } 431 432 nwconfig = ZYNQ_GEM_NWCFG_INIT; 433 434 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 435 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 436 ZYNQ_GEM_NWCFG_PCS_SEL; 437 #ifdef CONFIG_ARM64 438 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 439 ®s->pcscntrl); 440 #endif 441 } 442 443 switch (priv->phydev->speed) { 444 case SPEED_1000: 445 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 446 ®s->nwcfg); 447 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 448 break; 449 case SPEED_100: 450 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 451 ®s->nwcfg); 452 clk_rate = ZYNQ_GEM_FREQUENCY_100; 453 break; 454 case SPEED_10: 455 clk_rate = ZYNQ_GEM_FREQUENCY_10; 456 break; 457 } 458 459 #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) 460 ret = clk_set_rate(&priv->clk, clk_rate); 461 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { 462 dev_err(dev, "failed to set tx clock rate\n"); 463 return ret; 464 } 465 466 ret = clk_enable(&priv->clk); 467 if (ret && ret != -ENOSYS) { 468 dev_err(dev, "failed to enable tx clock\n"); 469 return ret; 470 } 471 #else 472 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 473 ZYNQ_GEM_BASEADDR0, clk_rate); 474 #endif 475 476 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 477 ZYNQ_GEM_NWCTRL_TXEN_MASK); 478 479 return 0; 480 } 481 482 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 483 { 484 u32 addr, size; 485 struct zynq_gem_priv *priv = dev_get_priv(dev); 486 struct zynq_gem_regs *regs = priv->iobase; 487 struct emac_bd *current_bd = &priv->tx_bd[1]; 488 489 /* Setup Tx BD */ 490 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 491 492 priv->tx_bd->addr = (ulong)ptr; 493 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 494 ZYNQ_GEM_TXBUF_LAST_MASK; 495 /* Dummy descriptor to mark it as the last in descriptor chain */ 496 current_bd->addr = 0x0; 497 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 498 ZYNQ_GEM_TXBUF_LAST_MASK| 499 ZYNQ_GEM_TXBUF_USED_MASK; 500 501 /* setup BD */ 502 writel((ulong)priv->tx_bd, ®s->txqbase); 503 504 addr = (ulong) ptr; 505 addr &= ~(ARCH_DMA_MINALIGN - 1); 506 size = roundup(len, ARCH_DMA_MINALIGN); 507 flush_dcache_range(addr, addr + size); 508 509 addr = (ulong)priv->rxbuffers; 510 addr &= ~(ARCH_DMA_MINALIGN - 1); 511 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 512 flush_dcache_range(addr, addr + size); 513 barrier(); 514 515 /* Start transmit */ 516 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 517 518 /* Read TX BD status */ 519 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 520 printf("TX buffers exhausted in mid frame\n"); 521 522 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 523 true, 20000, true); 524 } 525 526 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 527 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 528 { 529 int frame_len; 530 u32 addr; 531 struct zynq_gem_priv *priv = dev_get_priv(dev); 532 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 533 534 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 535 return -1; 536 537 if (!(current_bd->status & 538 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 539 printf("GEM: SOF or EOF not set for last buffer received!\n"); 540 return -1; 541 } 542 543 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 544 if (!frame_len) { 545 printf("%s: Zero size packet?\n", __func__); 546 return -1; 547 } 548 549 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 550 addr &= ~(ARCH_DMA_MINALIGN - 1); 551 *packetp = (uchar *)(uintptr_t)addr; 552 553 return frame_len; 554 } 555 556 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 557 { 558 struct zynq_gem_priv *priv = dev_get_priv(dev); 559 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 560 struct emac_bd *first_bd; 561 562 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 563 priv->rx_first_buf = priv->rxbd_current; 564 } else { 565 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 566 current_bd->status = 0xF0000000; /* FIXME */ 567 } 568 569 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 570 first_bd = &priv->rx_bd[priv->rx_first_buf]; 571 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 572 first_bd->status = 0xF0000000; 573 } 574 575 if ((++priv->rxbd_current) >= RX_BUF) 576 priv->rxbd_current = 0; 577 578 return 0; 579 } 580 581 static void zynq_gem_halt(struct udevice *dev) 582 { 583 struct zynq_gem_priv *priv = dev_get_priv(dev); 584 struct zynq_gem_regs *regs = priv->iobase; 585 586 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 587 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 588 } 589 590 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 591 { 592 return -ENOSYS; 593 } 594 595 static int zynq_gem_read_rom_mac(struct udevice *dev) 596 { 597 int retval; 598 struct eth_pdata *pdata = dev_get_platdata(dev); 599 600 retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); 601 if (retval == -ENOSYS) 602 retval = 0; 603 604 return retval; 605 } 606 607 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 608 int devad, int reg) 609 { 610 struct zynq_gem_priv *priv = bus->priv; 611 int ret; 612 u16 val; 613 614 ret = phyread(priv, addr, reg, &val); 615 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 616 return val; 617 } 618 619 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 620 int reg, u16 value) 621 { 622 struct zynq_gem_priv *priv = bus->priv; 623 624 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 625 return phywrite(priv, addr, reg, value); 626 } 627 628 static int zynq_gem_probe(struct udevice *dev) 629 { 630 void *bd_space; 631 struct zynq_gem_priv *priv = dev_get_priv(dev); 632 int ret; 633 634 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 635 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 636 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 637 638 /* Align bd_space to MMU_SECTION_SHIFT */ 639 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 640 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 641 BD_SPACE, DCACHE_OFF); 642 643 /* Initialize the bd spaces for tx and rx bd's */ 644 priv->tx_bd = (struct emac_bd *)bd_space; 645 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 646 647 #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) 648 ret = clk_get_by_name(dev, "tx_clk", &priv->clk); 649 if (ret < 0) { 650 dev_err(dev, "failed to get clock\n"); 651 return -EINVAL; 652 } 653 #endif 654 655 priv->bus = mdio_alloc(); 656 priv->bus->read = zynq_gem_miiphy_read; 657 priv->bus->write = zynq_gem_miiphy_write; 658 priv->bus->priv = priv; 659 660 ret = mdio_register_seq(priv->bus, dev->seq); 661 if (ret) 662 return ret; 663 664 return zynq_phy_init(dev); 665 } 666 667 static int zynq_gem_remove(struct udevice *dev) 668 { 669 struct zynq_gem_priv *priv = dev_get_priv(dev); 670 671 free(priv->phydev); 672 mdio_unregister(priv->bus); 673 mdio_free(priv->bus); 674 675 return 0; 676 } 677 678 static const struct eth_ops zynq_gem_ops = { 679 .start = zynq_gem_init, 680 .send = zynq_gem_send, 681 .recv = zynq_gem_recv, 682 .free_pkt = zynq_gem_free_pkt, 683 .stop = zynq_gem_halt, 684 .write_hwaddr = zynq_gem_setup_mac, 685 .read_rom_hwaddr = zynq_gem_read_rom_mac, 686 }; 687 688 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 689 { 690 struct eth_pdata *pdata = dev_get_platdata(dev); 691 struct zynq_gem_priv *priv = dev_get_priv(dev); 692 int node = dev_of_offset(dev); 693 const char *phy_mode; 694 695 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 696 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 697 /* Hardcode for now */ 698 priv->phyaddr = -1; 699 700 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, 701 "phy-handle"); 702 if (priv->phy_of_handle > 0) 703 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 704 priv->phy_of_handle, "reg", -1); 705 706 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 707 if (phy_mode) 708 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 709 if (pdata->phy_interface == -1) { 710 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 711 return -EINVAL; 712 } 713 priv->interface = pdata->phy_interface; 714 715 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 716 priv->phyaddr, phy_string_for_interface(priv->interface)); 717 718 return 0; 719 } 720 721 static const struct udevice_id zynq_gem_ids[] = { 722 { .compatible = "cdns,zynqmp-gem" }, 723 { .compatible = "cdns,zynq-gem" }, 724 { .compatible = "cdns,gem" }, 725 { } 726 }; 727 728 U_BOOT_DRIVER(zynq_gem) = { 729 .name = "zynq_gem", 730 .id = UCLASS_ETH, 731 .of_match = zynq_gem_ids, 732 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 733 .probe = zynq_gem_probe, 734 .remove = zynq_gem_remove, 735 .ops = &zynq_gem_ops, 736 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 737 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 738 }; 739