1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <malloc.h> 18 #include <asm/io.h> 19 #include <phy.h> 20 #include <miiphy.h> 21 #include <watchdog.h> 22 #include <asm/system.h> 23 #include <asm/arch/hardware.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm-generic/errno.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #if !defined(CONFIG_PHYLIB) 30 # error XILINX_GEM_ETHERNET requires PHYLIB 31 #endif 32 33 /* Bit/mask specification */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 36 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 37 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 38 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 39 40 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 41 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 42 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 43 44 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 45 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 46 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 47 48 /* Wrap bit, last descriptor */ 49 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 50 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 51 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 52 53 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 54 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 55 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 56 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 57 58 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 59 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 60 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 61 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 62 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 63 64 #ifdef CONFIG_ARM64 65 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 66 #else 67 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 68 #endif 69 70 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 71 ZYNQ_GEM_NWCFG_FDEN | \ 72 ZYNQ_GEM_NWCFG_FSREM | \ 73 ZYNQ_GEM_NWCFG_MDCCLKDIV) 74 75 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 76 77 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 78 /* Use full configured addressable space (8 Kb) */ 79 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 80 /* Use full configured addressable space (4 Kb) */ 81 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 82 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 83 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 84 85 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 86 ZYNQ_GEM_DMACR_RXSIZE | \ 87 ZYNQ_GEM_DMACR_TXSIZE | \ 88 ZYNQ_GEM_DMACR_RXBUF) 89 90 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 91 92 /* Use MII register 1 (MII status register) to detect PHY */ 93 #define PHY_DETECT_REG 1 94 95 /* Mask used to verify certain PHY features (or register contents) 96 * in the register above: 97 * 0x1000: 10Mbps full duplex support 98 * 0x0800: 10Mbps half duplex support 99 * 0x0008: Auto-negotiation support 100 */ 101 #define PHY_DETECT_MASK 0x1808 102 103 /* TX BD status masks */ 104 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 105 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 106 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 107 108 /* Clock frequencies for different speeds */ 109 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 110 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 111 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 112 113 /* Device registers */ 114 struct zynq_gem_regs { 115 u32 nwctrl; /* 0x0 - Network Control reg */ 116 u32 nwcfg; /* 0x4 - Network Config reg */ 117 u32 nwsr; /* 0x8 - Network Status reg */ 118 u32 reserved1; 119 u32 dmacr; /* 0x10 - DMA Control reg */ 120 u32 txsr; /* 0x14 - TX Status reg */ 121 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 122 u32 txqbase; /* 0x1c - TX Q Base address reg */ 123 u32 rxsr; /* 0x20 - RX Status reg */ 124 u32 reserved2[2]; 125 u32 idr; /* 0x2c - Interrupt Disable reg */ 126 u32 reserved3; 127 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 128 u32 reserved4[18]; 129 u32 hashl; /* 0x80 - Hash Low address reg */ 130 u32 hashh; /* 0x84 - Hash High address reg */ 131 #define LADDR_LOW 0 132 #define LADDR_HIGH 1 133 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 134 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 135 u32 reserved6[18]; 136 #define STAT_SIZE 44 137 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 138 u32 reserved7[164]; 139 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 140 u32 reserved8[15]; 141 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 142 }; 143 144 /* BD descriptors */ 145 struct emac_bd { 146 u32 addr; /* Next descriptor pointer */ 147 u32 status; 148 }; 149 150 #define RX_BUF 32 151 /* Page table entries are set to 1MB, or multiples of 1MB 152 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 153 */ 154 #define BD_SPACE 0x100000 155 /* BD separation space */ 156 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 157 158 /* Setup the first free TX descriptor */ 159 #define TX_FREE_DESC 2 160 161 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 162 struct zynq_gem_priv { 163 struct emac_bd *tx_bd; 164 struct emac_bd *rx_bd; 165 char *rxbuffers; 166 u32 rxbd_current; 167 u32 rx_first_buf; 168 int phyaddr; 169 u32 emio; 170 int init; 171 struct zynq_gem_regs *iobase; 172 phy_interface_t interface; 173 struct phy_device *phydev; 174 struct mii_dev *bus; 175 }; 176 177 static inline int mdio_wait(struct zynq_gem_regs *regs) 178 { 179 u32 timeout = 20000; 180 181 /* Wait till MDIO interface is ready to accept a new transaction. */ 182 while (--timeout) { 183 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 184 break; 185 WATCHDOG_RESET(); 186 } 187 188 if (!timeout) { 189 printf("%s: Timeout\n", __func__); 190 return 1; 191 } 192 193 return 0; 194 } 195 196 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 197 u32 op, u16 *data) 198 { 199 u32 mgtcr; 200 struct zynq_gem_regs *regs = priv->iobase; 201 202 if (mdio_wait(regs)) 203 return 1; 204 205 /* Construct mgtcr mask for the operation */ 206 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 207 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 208 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 209 210 /* Write mgtcr and wait for completion */ 211 writel(mgtcr, ®s->phymntnc); 212 213 if (mdio_wait(regs)) 214 return 1; 215 216 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 217 *data = readl(®s->phymntnc); 218 219 return 0; 220 } 221 222 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 223 u32 regnum, u16 *val) 224 { 225 u32 ret; 226 227 ret = phy_setup_op(priv, phy_addr, regnum, 228 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 229 230 if (!ret) 231 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 232 phy_addr, regnum, *val); 233 234 return ret; 235 } 236 237 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 238 u32 regnum, u16 data) 239 { 240 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 241 regnum, data); 242 243 return phy_setup_op(priv, phy_addr, regnum, 244 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 245 } 246 247 static int phy_detection(struct udevice *dev) 248 { 249 int i; 250 u16 phyreg; 251 struct zynq_gem_priv *priv = dev->priv; 252 253 if (priv->phyaddr != -1) { 254 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 255 if ((phyreg != 0xFFFF) && 256 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 257 /* Found a valid PHY address */ 258 debug("Default phy address %d is valid\n", 259 priv->phyaddr); 260 return 0; 261 } else { 262 debug("PHY address is not setup correctly %d\n", 263 priv->phyaddr); 264 priv->phyaddr = -1; 265 } 266 } 267 268 debug("detecting phy address\n"); 269 if (priv->phyaddr == -1) { 270 /* detect the PHY address */ 271 for (i = 31; i >= 0; i--) { 272 phyread(priv, i, PHY_DETECT_REG, &phyreg); 273 if ((phyreg != 0xFFFF) && 274 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 275 /* Found a valid PHY address */ 276 priv->phyaddr = i; 277 debug("Found valid phy address, %d\n", i); 278 return 0; 279 } 280 } 281 } 282 printf("PHY is not detected\n"); 283 return -1; 284 } 285 286 static int zynq_gem_setup_mac(struct udevice *dev) 287 { 288 u32 i, macaddrlow, macaddrhigh; 289 struct eth_pdata *pdata = dev_get_platdata(dev); 290 struct zynq_gem_priv *priv = dev_get_priv(dev); 291 struct zynq_gem_regs *regs = priv->iobase; 292 293 /* Set the MAC bits [31:0] in BOT */ 294 macaddrlow = pdata->enetaddr[0]; 295 macaddrlow |= pdata->enetaddr[1] << 8; 296 macaddrlow |= pdata->enetaddr[2] << 16; 297 macaddrlow |= pdata->enetaddr[3] << 24; 298 299 /* Set MAC bits [47:32] in TOP */ 300 macaddrhigh = pdata->enetaddr[4]; 301 macaddrhigh |= pdata->enetaddr[5] << 8; 302 303 for (i = 0; i < 4; i++) { 304 writel(0, ®s->laddr[i][LADDR_LOW]); 305 writel(0, ®s->laddr[i][LADDR_HIGH]); 306 /* Do not use MATCHx register */ 307 writel(0, ®s->match[i]); 308 } 309 310 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 311 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 312 313 return 0; 314 } 315 316 static int zynq_phy_init(struct udevice *dev) 317 { 318 int ret; 319 struct zynq_gem_priv *priv = dev_get_priv(dev); 320 struct zynq_gem_regs *regs = priv->iobase; 321 const u32 supported = SUPPORTED_10baseT_Half | 322 SUPPORTED_10baseT_Full | 323 SUPPORTED_100baseT_Half | 324 SUPPORTED_100baseT_Full | 325 SUPPORTED_1000baseT_Half | 326 SUPPORTED_1000baseT_Full; 327 328 /* Enable only MDIO bus */ 329 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 330 331 ret = phy_detection(dev); 332 if (ret) { 333 printf("GEM PHY init failed\n"); 334 return ret; 335 } 336 337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 338 priv->interface); 339 if (!priv->phydev) 340 return -ENODEV; 341 342 priv->phydev->supported = supported | ADVERTISED_Pause | 343 ADVERTISED_Asym_Pause; 344 priv->phydev->advertising = priv->phydev->supported; 345 phy_config(priv->phydev); 346 347 return 0; 348 } 349 350 static int zynq_gem_init(struct udevice *dev) 351 { 352 u32 i; 353 unsigned long clk_rate = 0; 354 struct zynq_gem_priv *priv = dev_get_priv(dev); 355 struct zynq_gem_regs *regs = priv->iobase; 356 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 357 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 358 359 if (!priv->init) { 360 /* Disable all interrupts */ 361 writel(0xFFFFFFFF, ®s->idr); 362 363 /* Disable the receiver & transmitter */ 364 writel(0, ®s->nwctrl); 365 writel(0, ®s->txsr); 366 writel(0, ®s->rxsr); 367 writel(0, ®s->phymntnc); 368 369 /* Clear the Hash registers for the mac address 370 * pointed by AddressPtr 371 */ 372 writel(0x0, ®s->hashl); 373 /* Write bits [63:32] in TOP */ 374 writel(0x0, ®s->hashh); 375 376 /* Clear all counters */ 377 for (i = 0; i < STAT_SIZE; i++) 378 readl(®s->stat[i]); 379 380 /* Setup RxBD space */ 381 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 382 383 for (i = 0; i < RX_BUF; i++) { 384 priv->rx_bd[i].status = 0xF0000000; 385 priv->rx_bd[i].addr = 386 ((ulong)(priv->rxbuffers) + 387 (i * PKTSIZE_ALIGN)); 388 } 389 /* WRAP bit to last BD */ 390 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 391 /* Write RxBDs to IP */ 392 writel((ulong)priv->rx_bd, ®s->rxqbase); 393 394 /* Setup for DMA Configuration register */ 395 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 396 397 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 398 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 399 400 /* Disable the second priority queue */ 401 dummy_tx_bd->addr = 0; 402 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 403 ZYNQ_GEM_TXBUF_LAST_MASK| 404 ZYNQ_GEM_TXBUF_USED_MASK; 405 406 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 407 ZYNQ_GEM_RXBUF_NEW_MASK; 408 dummy_rx_bd->status = 0; 409 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 410 sizeof(dummy_tx_bd)); 411 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 412 sizeof(dummy_rx_bd)); 413 414 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 415 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 416 417 priv->init++; 418 } 419 420 phy_startup(priv->phydev); 421 422 if (!priv->phydev->link) { 423 printf("%s: No link.\n", priv->phydev->dev->name); 424 return -1; 425 } 426 427 switch (priv->phydev->speed) { 428 case SPEED_1000: 429 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 430 ®s->nwcfg); 431 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 432 break; 433 case SPEED_100: 434 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, 435 ®s->nwcfg); 436 clk_rate = ZYNQ_GEM_FREQUENCY_100; 437 break; 438 case SPEED_10: 439 clk_rate = ZYNQ_GEM_FREQUENCY_10; 440 break; 441 } 442 443 /* Change the rclk and clk only not using EMIO interface */ 444 if (!priv->emio) 445 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 446 ZYNQ_GEM_BASEADDR0, clk_rate); 447 448 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 449 ZYNQ_GEM_NWCTRL_TXEN_MASK); 450 451 return 0; 452 } 453 454 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 455 bool set, unsigned int timeout) 456 { 457 u32 val; 458 unsigned long start = get_timer(0); 459 460 while (1) { 461 val = readl(reg); 462 463 if (!set) 464 val = ~val; 465 466 if ((val & mask) == mask) 467 return 0; 468 469 if (get_timer(start) > timeout) 470 break; 471 472 udelay(1); 473 } 474 475 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 476 func, reg, mask, set); 477 478 return -ETIMEDOUT; 479 } 480 481 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 482 { 483 u32 addr, size; 484 struct zynq_gem_priv *priv = dev_get_priv(dev); 485 struct zynq_gem_regs *regs = priv->iobase; 486 struct emac_bd *current_bd = &priv->tx_bd[1]; 487 488 /* Setup Tx BD */ 489 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 490 491 priv->tx_bd->addr = (ulong)ptr; 492 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 493 ZYNQ_GEM_TXBUF_LAST_MASK; 494 /* Dummy descriptor to mark it as the last in descriptor chain */ 495 current_bd->addr = 0x0; 496 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 497 ZYNQ_GEM_TXBUF_LAST_MASK| 498 ZYNQ_GEM_TXBUF_USED_MASK; 499 500 /* setup BD */ 501 writel((ulong)priv->tx_bd, ®s->txqbase); 502 503 addr = (ulong) ptr; 504 addr &= ~(ARCH_DMA_MINALIGN - 1); 505 size = roundup(len, ARCH_DMA_MINALIGN); 506 flush_dcache_range(addr, addr + size); 507 508 addr = (ulong)priv->rxbuffers; 509 addr &= ~(ARCH_DMA_MINALIGN - 1); 510 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 511 flush_dcache_range(addr, addr + size); 512 barrier(); 513 514 /* Start transmit */ 515 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 516 517 /* Read TX BD status */ 518 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 519 printf("TX buffers exhausted in mid frame\n"); 520 521 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 522 true, 20000); 523 } 524 525 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 526 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 527 { 528 int frame_len; 529 struct zynq_gem_priv *priv = dev_get_priv(dev); 530 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 531 struct emac_bd *first_bd; 532 533 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 534 return 0; 535 536 if (!(current_bd->status & 537 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 538 printf("GEM: SOF or EOF not set for last buffer received!\n"); 539 return 0; 540 } 541 542 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 543 if (frame_len) { 544 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 545 addr &= ~(ARCH_DMA_MINALIGN - 1); 546 547 net_process_received_packet((u8 *)(ulong)addr, frame_len); 548 549 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 550 priv->rx_first_buf = priv->rxbd_current; 551 else { 552 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 553 current_bd->status = 0xF0000000; /* FIXME */ 554 } 555 556 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 557 first_bd = &priv->rx_bd[priv->rx_first_buf]; 558 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 559 first_bd->status = 0xF0000000; 560 } 561 562 if ((++priv->rxbd_current) >= RX_BUF) 563 priv->rxbd_current = 0; 564 } 565 566 return frame_len; 567 } 568 569 static void zynq_gem_halt(struct udevice *dev) 570 { 571 struct zynq_gem_priv *priv = dev_get_priv(dev); 572 struct zynq_gem_regs *regs = priv->iobase; 573 574 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 575 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 576 } 577 578 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 579 int devad, int reg) 580 { 581 struct zynq_gem_priv *priv = bus->priv; 582 int ret; 583 u16 val; 584 585 ret = phyread(priv, addr, reg, &val); 586 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 587 return val; 588 } 589 590 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 591 int reg, u16 value) 592 { 593 struct zynq_gem_priv *priv = bus->priv; 594 595 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 596 return phywrite(priv, addr, reg, value); 597 } 598 599 static int zynq_gem_probe(struct udevice *dev) 600 { 601 void *bd_space; 602 struct zynq_gem_priv *priv = dev_get_priv(dev); 603 int ret; 604 605 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 606 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 607 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 608 609 /* Align bd_space to MMU_SECTION_SHIFT */ 610 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 611 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 612 BD_SPACE, DCACHE_OFF); 613 614 /* Initialize the bd spaces for tx and rx bd's */ 615 priv->tx_bd = (struct emac_bd *)bd_space; 616 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 617 618 priv->bus = mdio_alloc(); 619 priv->bus->read = zynq_gem_miiphy_read; 620 priv->bus->write = zynq_gem_miiphy_write; 621 priv->bus->priv = priv; 622 strcpy(priv->bus->name, "gem"); 623 624 #ifndef CONFIG_ZYNQ_GEM_INTERFACE 625 priv->interface = PHY_INTERFACE_MODE_MII; 626 #else 627 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 628 #endif 629 630 ret = mdio_register(priv->bus); 631 if (ret) 632 return ret; 633 634 zynq_phy_init(dev); 635 636 return 0; 637 } 638 639 static int zynq_gem_remove(struct udevice *dev) 640 { 641 struct zynq_gem_priv *priv = dev_get_priv(dev); 642 643 free(priv->phydev); 644 mdio_unregister(priv->bus); 645 mdio_free(priv->bus); 646 647 return 0; 648 } 649 650 static const struct eth_ops zynq_gem_ops = { 651 .start = zynq_gem_init, 652 .send = zynq_gem_send, 653 .recv = zynq_gem_recv, 654 .stop = zynq_gem_halt, 655 .write_hwaddr = zynq_gem_setup_mac, 656 }; 657 658 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 659 { 660 struct eth_pdata *pdata = dev_get_platdata(dev); 661 struct zynq_gem_priv *priv = dev_get_priv(dev); 662 int offset = 0; 663 664 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 665 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 666 /* Hardcode for now */ 667 priv->emio = 0; 668 669 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 670 "phy-handle"); 671 if (offset > 0) 672 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); 673 674 printf("ZYNQ GEM: %lx, phyaddr %d\n", (ulong)priv->iobase, 675 priv->phyaddr); 676 677 return 0; 678 } 679 680 static const struct udevice_id zynq_gem_ids[] = { 681 { .compatible = "cdns,zynqmp-gem" }, 682 { .compatible = "cdns,zynq-gem" }, 683 { .compatible = "cdns,gem" }, 684 { } 685 }; 686 687 U_BOOT_DRIVER(zynq_gem) = { 688 .name = "zynq_gem", 689 .id = UCLASS_ETH, 690 .of_match = zynq_gem_ids, 691 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 692 .probe = zynq_gem_probe, 693 .remove = zynq_gem_remove, 694 .ops = &zynq_gem_ops, 695 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 696 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 697 }; 698