1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <config.h> 16 #include <fdtdec.h> 17 #include <libfdt.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <watchdog.h> 23 #include <asm/system.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/sys_proto.h> 26 27 #if !defined(CONFIG_PHYLIB) 28 # error XILINX_GEM_ETHERNET requires PHYLIB 29 #endif 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 62 63 #ifdef CONFIG_ARM64 64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 65 #else 66 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 67 #endif 68 69 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 70 ZYNQ_GEM_NWCFG_FDEN | \ 71 ZYNQ_GEM_NWCFG_FSREM | \ 72 ZYNQ_GEM_NWCFG_MDCCLKDIV) 73 74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 75 76 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 77 /* Use full configured addressable space (8 Kb) */ 78 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 79 /* Use full configured addressable space (4 Kb) */ 80 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 82 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 83 84 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 85 ZYNQ_GEM_DMACR_RXSIZE | \ 86 ZYNQ_GEM_DMACR_TXSIZE | \ 87 ZYNQ_GEM_DMACR_RXBUF) 88 89 /* Use MII register 1 (MII status register) to detect PHY */ 90 #define PHY_DETECT_REG 1 91 92 /* Mask used to verify certain PHY features (or register contents) 93 * in the register above: 94 * 0x1000: 10Mbps full duplex support 95 * 0x0800: 10Mbps half duplex support 96 * 0x0008: Auto-negotiation support 97 */ 98 #define PHY_DETECT_MASK 0x1808 99 100 /* TX BD status masks */ 101 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 102 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 103 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 104 105 /* Clock frequencies for different speeds */ 106 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 107 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 108 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 109 110 /* Device registers */ 111 struct zynq_gem_regs { 112 u32 nwctrl; /* 0x0 - Network Control reg */ 113 u32 nwcfg; /* 0x4 - Network Config reg */ 114 u32 nwsr; /* 0x8 - Network Status reg */ 115 u32 reserved1; 116 u32 dmacr; /* 0x10 - DMA Control reg */ 117 u32 txsr; /* 0x14 - TX Status reg */ 118 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 119 u32 txqbase; /* 0x1c - TX Q Base address reg */ 120 u32 rxsr; /* 0x20 - RX Status reg */ 121 u32 reserved2[2]; 122 u32 idr; /* 0x2c - Interrupt Disable reg */ 123 u32 reserved3; 124 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 125 u32 reserved4[18]; 126 u32 hashl; /* 0x80 - Hash Low address reg */ 127 u32 hashh; /* 0x84 - Hash High address reg */ 128 #define LADDR_LOW 0 129 #define LADDR_HIGH 1 130 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 131 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 132 u32 reserved6[18]; 133 #define STAT_SIZE 44 134 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 135 u32 reserved7[164]; 136 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 137 u32 reserved8[15]; 138 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 139 }; 140 141 /* BD descriptors */ 142 struct emac_bd { 143 u32 addr; /* Next descriptor pointer */ 144 u32 status; 145 }; 146 147 #define RX_BUF 32 148 /* Page table entries are set to 1MB, or multiples of 1MB 149 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 150 */ 151 #define BD_SPACE 0x100000 152 /* BD separation space */ 153 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 154 155 /* Setup the first free TX descriptor */ 156 #define TX_FREE_DESC 2 157 158 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 159 struct zynq_gem_priv { 160 struct emac_bd *tx_bd; 161 struct emac_bd *rx_bd; 162 char *rxbuffers; 163 u32 rxbd_current; 164 u32 rx_first_buf; 165 int phyaddr; 166 u32 emio; 167 int init; 168 phy_interface_t interface; 169 struct phy_device *phydev; 170 struct mii_dev *bus; 171 }; 172 173 static inline int mdio_wait(struct eth_device *dev) 174 { 175 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 176 u32 timeout = 20000; 177 178 /* Wait till MDIO interface is ready to accept a new transaction. */ 179 while (--timeout) { 180 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 181 break; 182 WATCHDOG_RESET(); 183 } 184 185 if (!timeout) { 186 printf("%s: Timeout\n", __func__); 187 return 1; 188 } 189 190 return 0; 191 } 192 193 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 194 u32 op, u16 *data) 195 { 196 u32 mgtcr; 197 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 198 199 if (mdio_wait(dev)) 200 return 1; 201 202 /* Construct mgtcr mask for the operation */ 203 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 204 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 205 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 206 207 /* Write mgtcr and wait for completion */ 208 writel(mgtcr, ®s->phymntnc); 209 210 if (mdio_wait(dev)) 211 return 1; 212 213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 214 *data = readl(®s->phymntnc); 215 216 return 0; 217 } 218 219 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 220 { 221 u32 ret; 222 223 ret = phy_setup_op(dev, phy_addr, regnum, 224 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 225 226 if (!ret) 227 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 228 phy_addr, regnum, *val); 229 230 return ret; 231 } 232 233 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 234 { 235 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 236 regnum, data); 237 238 return phy_setup_op(dev, phy_addr, regnum, 239 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 240 } 241 242 static void phy_detection(struct eth_device *dev) 243 { 244 int i; 245 u16 phyreg; 246 struct zynq_gem_priv *priv = dev->priv; 247 248 if (priv->phyaddr != -1) { 249 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 250 if ((phyreg != 0xFFFF) && 251 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 252 /* Found a valid PHY address */ 253 debug("Default phy address %d is valid\n", 254 priv->phyaddr); 255 return; 256 } else { 257 debug("PHY address is not setup correctly %d\n", 258 priv->phyaddr); 259 priv->phyaddr = -1; 260 } 261 } 262 263 debug("detecting phy address\n"); 264 if (priv->phyaddr == -1) { 265 /* detect the PHY address */ 266 for (i = 31; i >= 0; i--) { 267 phyread(dev, i, PHY_DETECT_REG, &phyreg); 268 if ((phyreg != 0xFFFF) && 269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 270 /* Found a valid PHY address */ 271 priv->phyaddr = i; 272 debug("Found valid phy address, %d\n", i); 273 return; 274 } 275 } 276 } 277 printf("PHY is not detected\n"); 278 } 279 280 static int zynq_gem_setup_mac(struct eth_device *dev) 281 { 282 u32 i, macaddrlow, macaddrhigh; 283 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 284 285 /* Set the MAC bits [31:0] in BOT */ 286 macaddrlow = dev->enetaddr[0]; 287 macaddrlow |= dev->enetaddr[1] << 8; 288 macaddrlow |= dev->enetaddr[2] << 16; 289 macaddrlow |= dev->enetaddr[3] << 24; 290 291 /* Set MAC bits [47:32] in TOP */ 292 macaddrhigh = dev->enetaddr[4]; 293 macaddrhigh |= dev->enetaddr[5] << 8; 294 295 for (i = 0; i < 4; i++) { 296 writel(0, ®s->laddr[i][LADDR_LOW]); 297 writel(0, ®s->laddr[i][LADDR_HIGH]); 298 /* Do not use MATCHx register */ 299 writel(0, ®s->match[i]); 300 } 301 302 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 303 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 304 305 return 0; 306 } 307 308 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 309 { 310 u32 i; 311 unsigned long clk_rate = 0; 312 struct phy_device *phydev; 313 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 314 struct zynq_gem_priv *priv = dev->priv; 315 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 316 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 317 const u32 supported = SUPPORTED_10baseT_Half | 318 SUPPORTED_10baseT_Full | 319 SUPPORTED_100baseT_Half | 320 SUPPORTED_100baseT_Full | 321 SUPPORTED_1000baseT_Half | 322 SUPPORTED_1000baseT_Full; 323 324 if (!priv->init) { 325 /* Disable all interrupts */ 326 writel(0xFFFFFFFF, ®s->idr); 327 328 /* Disable the receiver & transmitter */ 329 writel(0, ®s->nwctrl); 330 writel(0, ®s->txsr); 331 writel(0, ®s->rxsr); 332 writel(0, ®s->phymntnc); 333 334 /* Clear the Hash registers for the mac address 335 * pointed by AddressPtr 336 */ 337 writel(0x0, ®s->hashl); 338 /* Write bits [63:32] in TOP */ 339 writel(0x0, ®s->hashh); 340 341 /* Clear all counters */ 342 for (i = 0; i < STAT_SIZE; i++) 343 readl(®s->stat[i]); 344 345 /* Setup RxBD space */ 346 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 347 348 for (i = 0; i < RX_BUF; i++) { 349 priv->rx_bd[i].status = 0xF0000000; 350 priv->rx_bd[i].addr = 351 ((ulong)(priv->rxbuffers) + 352 (i * PKTSIZE_ALIGN)); 353 } 354 /* WRAP bit to last BD */ 355 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 356 /* Write RxBDs to IP */ 357 writel((ulong)priv->rx_bd, ®s->rxqbase); 358 359 /* Setup for DMA Configuration register */ 360 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 361 362 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 363 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 364 365 /* Disable the second priority queue */ 366 dummy_tx_bd->addr = 0; 367 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 368 ZYNQ_GEM_TXBUF_LAST_MASK| 369 ZYNQ_GEM_TXBUF_USED_MASK; 370 371 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 372 ZYNQ_GEM_RXBUF_NEW_MASK; 373 dummy_rx_bd->status = 0; 374 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 375 sizeof(dummy_tx_bd)); 376 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 377 sizeof(dummy_rx_bd)); 378 379 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 380 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 381 382 priv->init++; 383 } 384 385 phy_detection(dev); 386 387 /* interface - look at tsec */ 388 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 389 priv->interface); 390 391 phydev->supported = supported | ADVERTISED_Pause | 392 ADVERTISED_Asym_Pause; 393 phydev->advertising = phydev->supported; 394 priv->phydev = phydev; 395 phy_config(phydev); 396 phy_startup(phydev); 397 398 if (!phydev->link) { 399 printf("%s: No link.\n", phydev->dev->name); 400 return -1; 401 } 402 403 switch (phydev->speed) { 404 case SPEED_1000: 405 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 406 ®s->nwcfg); 407 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 408 break; 409 case SPEED_100: 410 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 411 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 412 clk_rate = ZYNQ_GEM_FREQUENCY_100; 413 break; 414 case SPEED_10: 415 clk_rate = ZYNQ_GEM_FREQUENCY_10; 416 break; 417 } 418 419 /* Change the rclk and clk only not using EMIO interface */ 420 if (!priv->emio) 421 zynq_slcr_gem_clk_setup(dev->iobase != 422 ZYNQ_GEM_BASEADDR0, clk_rate); 423 424 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 425 ZYNQ_GEM_NWCTRL_TXEN_MASK); 426 427 return 0; 428 } 429 430 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 431 { 432 u32 addr, size; 433 struct zynq_gem_priv *priv = dev->priv; 434 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 435 struct emac_bd *current_bd = &priv->tx_bd[1]; 436 437 /* Setup Tx BD */ 438 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 439 440 priv->tx_bd->addr = (ulong)ptr; 441 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 442 ZYNQ_GEM_TXBUF_LAST_MASK; 443 /* Dummy descriptor to mark it as the last in descriptor chain */ 444 current_bd->addr = 0x0; 445 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 446 ZYNQ_GEM_TXBUF_LAST_MASK| 447 ZYNQ_GEM_TXBUF_USED_MASK; 448 449 /* setup BD */ 450 writel((ulong)priv->tx_bd, ®s->txqbase); 451 452 addr = (ulong) ptr; 453 addr &= ~(ARCH_DMA_MINALIGN - 1); 454 size = roundup(len, ARCH_DMA_MINALIGN); 455 flush_dcache_range(addr, addr + size); 456 457 addr = (ulong)priv->rxbuffers; 458 addr &= ~(ARCH_DMA_MINALIGN - 1); 459 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 460 flush_dcache_range(addr, addr + size); 461 barrier(); 462 463 /* Start transmit */ 464 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 465 466 /* Read TX BD status */ 467 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 468 printf("TX buffers exhausted in mid frame\n"); 469 470 return 0; 471 } 472 473 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 474 static int zynq_gem_recv(struct eth_device *dev) 475 { 476 int frame_len; 477 struct zynq_gem_priv *priv = dev->priv; 478 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 479 struct emac_bd *first_bd; 480 481 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 482 return 0; 483 484 if (!(current_bd->status & 485 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 486 printf("GEM: SOF or EOF not set for last buffer received!\n"); 487 return 0; 488 } 489 490 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 491 if (frame_len) { 492 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 493 addr &= ~(ARCH_DMA_MINALIGN - 1); 494 495 net_process_received_packet((u8 *)(ulong)addr, frame_len); 496 497 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 498 priv->rx_first_buf = priv->rxbd_current; 499 else { 500 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 501 current_bd->status = 0xF0000000; /* FIXME */ 502 } 503 504 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 505 first_bd = &priv->rx_bd[priv->rx_first_buf]; 506 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 507 first_bd->status = 0xF0000000; 508 } 509 510 if ((++priv->rxbd_current) >= RX_BUF) 511 priv->rxbd_current = 0; 512 } 513 514 return frame_len; 515 } 516 517 static void zynq_gem_halt(struct eth_device *dev) 518 { 519 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 520 521 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 522 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 523 } 524 525 static int zynq_gem_miiphyread(const char *devname, uchar addr, 526 uchar reg, ushort *val) 527 { 528 struct eth_device *dev = eth_get_dev(); 529 int ret; 530 531 ret = phyread(dev, addr, reg, val); 532 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 533 return ret; 534 } 535 536 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 537 uchar reg, ushort val) 538 { 539 struct eth_device *dev = eth_get_dev(); 540 541 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 542 return phywrite(dev, addr, reg, val); 543 } 544 545 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 546 int phy_addr, u32 emio) 547 { 548 struct eth_device *dev; 549 struct zynq_gem_priv *priv; 550 void *bd_space; 551 552 dev = calloc(1, sizeof(*dev)); 553 if (dev == NULL) 554 return -1; 555 556 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 557 if (dev->priv == NULL) { 558 free(dev); 559 return -1; 560 } 561 priv = dev->priv; 562 563 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 564 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 565 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 566 567 /* Align bd_space to MMU_SECTION_SHIFT */ 568 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 569 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 570 BD_SPACE, DCACHE_OFF); 571 572 /* Initialize the bd spaces for tx and rx bd's */ 573 priv->tx_bd = (struct emac_bd *)bd_space; 574 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 575 576 priv->phyaddr = phy_addr; 577 priv->emio = emio; 578 579 #ifndef CONFIG_ZYNQ_GEM_INTERFACE 580 priv->interface = PHY_INTERFACE_MODE_MII; 581 #else 582 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 583 #endif 584 585 sprintf(dev->name, "Gem.%lx", base_addr); 586 587 dev->iobase = base_addr; 588 589 dev->init = zynq_gem_init; 590 dev->halt = zynq_gem_halt; 591 dev->send = zynq_gem_send; 592 dev->recv = zynq_gem_recv; 593 dev->write_hwaddr = zynq_gem_setup_mac; 594 595 eth_register(dev); 596 597 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 598 priv->bus = miiphy_get_dev_by_name(dev->name); 599 600 return 1; 601 } 602 603 #if CONFIG_IS_ENABLED(OF_CONTROL) 604 int zynq_gem_of_init(const void *blob) 605 { 606 int offset = 0; 607 u32 ret = 0; 608 u32 reg, phy_reg; 609 610 debug("ZYNQ GEM: Initialization\n"); 611 612 do { 613 offset = fdt_node_offset_by_compatible(blob, offset, 614 "xlnx,ps7-ethernet-1.00.a"); 615 if (offset != -1) { 616 reg = fdtdec_get_addr(blob, offset, "reg"); 617 if (reg != FDT_ADDR_T_NONE) { 618 offset = fdtdec_lookup_phandle(blob, offset, 619 "phy-handle"); 620 if (offset != -1) 621 phy_reg = fdtdec_get_addr(blob, offset, 622 "reg"); 623 else 624 phy_reg = 0; 625 626 debug("ZYNQ GEM: addr %x, phyaddr %x\n", 627 reg, phy_reg); 628 629 ret |= zynq_gem_initialize(NULL, reg, 630 phy_reg, 0); 631 632 } else { 633 debug("ZYNQ GEM: Can't get base address\n"); 634 return -1; 635 } 636 } 637 } while (offset != -1); 638 639 return ret; 640 } 641 #endif 642