1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <wait_bit.h> 23 #include <watchdog.h> 24 #include <asm/system.h> 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm-generic/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ 61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ 62 #ifdef CONFIG_ARM64 63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ 64 #else 65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ 66 #endif 67 68 #ifdef CONFIG_ARM64 69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 70 #else 71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 72 #endif 73 74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 75 ZYNQ_GEM_NWCFG_FDEN | \ 76 ZYNQ_GEM_NWCFG_FSREM | \ 77 ZYNQ_GEM_NWCFG_MDCCLKDIV) 78 79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 80 81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 82 /* Use full configured addressable space (8 Kb) */ 83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 84 /* Use full configured addressable space (4 Kb) */ 85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 88 89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 90 ZYNQ_GEM_DMACR_RXSIZE | \ 91 ZYNQ_GEM_DMACR_TXSIZE | \ 92 ZYNQ_GEM_DMACR_RXBUF) 93 94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 95 96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 97 98 /* Use MII register 1 (MII status register) to detect PHY */ 99 #define PHY_DETECT_REG 1 100 101 /* Mask used to verify certain PHY features (or register contents) 102 * in the register above: 103 * 0x1000: 10Mbps full duplex support 104 * 0x0800: 10Mbps half duplex support 105 * 0x0008: Auto-negotiation support 106 */ 107 #define PHY_DETECT_MASK 0x1808 108 109 /* TX BD status masks */ 110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 113 114 /* Clock frequencies for different speeds */ 115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 118 119 /* Device registers */ 120 struct zynq_gem_regs { 121 u32 nwctrl; /* 0x0 - Network Control reg */ 122 u32 nwcfg; /* 0x4 - Network Config reg */ 123 u32 nwsr; /* 0x8 - Network Status reg */ 124 u32 reserved1; 125 u32 dmacr; /* 0x10 - DMA Control reg */ 126 u32 txsr; /* 0x14 - TX Status reg */ 127 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 128 u32 txqbase; /* 0x1c - TX Q Base address reg */ 129 u32 rxsr; /* 0x20 - RX Status reg */ 130 u32 reserved2[2]; 131 u32 idr; /* 0x2c - Interrupt Disable reg */ 132 u32 reserved3; 133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 134 u32 reserved4[18]; 135 u32 hashl; /* 0x80 - Hash Low address reg */ 136 u32 hashh; /* 0x84 - Hash High address reg */ 137 #define LADDR_LOW 0 138 #define LADDR_HIGH 1 139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 141 u32 reserved6[18]; 142 #define STAT_SIZE 44 143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 144 u32 reserved9[20]; 145 u32 pcscntrl; 146 u32 reserved7[143]; 147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 148 u32 reserved8[15]; 149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 150 }; 151 152 /* BD descriptors */ 153 struct emac_bd { 154 u32 addr; /* Next descriptor pointer */ 155 u32 status; 156 }; 157 158 #define RX_BUF 32 159 /* Page table entries are set to 1MB, or multiples of 1MB 160 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 161 */ 162 #define BD_SPACE 0x100000 163 /* BD separation space */ 164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 165 166 /* Setup the first free TX descriptor */ 167 #define TX_FREE_DESC 2 168 169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 170 struct zynq_gem_priv { 171 struct emac_bd *tx_bd; 172 struct emac_bd *rx_bd; 173 char *rxbuffers; 174 u32 rxbd_current; 175 u32 rx_first_buf; 176 int phyaddr; 177 u32 emio; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 struct mii_dev *bus; 183 }; 184 185 static inline int mdio_wait(struct zynq_gem_regs *regs) 186 { 187 u32 timeout = 20000; 188 189 /* Wait till MDIO interface is ready to accept a new transaction. */ 190 while (--timeout) { 191 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 192 break; 193 WATCHDOG_RESET(); 194 } 195 196 if (!timeout) { 197 printf("%s: Timeout\n", __func__); 198 return 1; 199 } 200 201 return 0; 202 } 203 204 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 205 u32 op, u16 *data) 206 { 207 u32 mgtcr; 208 struct zynq_gem_regs *regs = priv->iobase; 209 210 if (mdio_wait(regs)) 211 return 1; 212 213 /* Construct mgtcr mask for the operation */ 214 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 215 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 216 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 217 218 /* Write mgtcr and wait for completion */ 219 writel(mgtcr, ®s->phymntnc); 220 221 if (mdio_wait(regs)) 222 return 1; 223 224 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 225 *data = readl(®s->phymntnc); 226 227 return 0; 228 } 229 230 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 231 u32 regnum, u16 *val) 232 { 233 u32 ret; 234 235 ret = phy_setup_op(priv, phy_addr, regnum, 236 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 237 238 if (!ret) 239 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 240 phy_addr, regnum, *val); 241 242 return ret; 243 } 244 245 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 246 u32 regnum, u16 data) 247 { 248 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 249 regnum, data); 250 251 return phy_setup_op(priv, phy_addr, regnum, 252 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 253 } 254 255 static int phy_detection(struct udevice *dev) 256 { 257 int i; 258 u16 phyreg; 259 struct zynq_gem_priv *priv = dev->priv; 260 261 if (priv->phyaddr != -1) { 262 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 263 if ((phyreg != 0xFFFF) && 264 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 265 /* Found a valid PHY address */ 266 debug("Default phy address %d is valid\n", 267 priv->phyaddr); 268 return 0; 269 } else { 270 debug("PHY address is not setup correctly %d\n", 271 priv->phyaddr); 272 priv->phyaddr = -1; 273 } 274 } 275 276 debug("detecting phy address\n"); 277 if (priv->phyaddr == -1) { 278 /* detect the PHY address */ 279 for (i = 31; i >= 0; i--) { 280 phyread(priv, i, PHY_DETECT_REG, &phyreg); 281 if ((phyreg != 0xFFFF) && 282 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 283 /* Found a valid PHY address */ 284 priv->phyaddr = i; 285 debug("Found valid phy address, %d\n", i); 286 return 0; 287 } 288 } 289 } 290 printf("PHY is not detected\n"); 291 return -1; 292 } 293 294 static int zynq_gem_setup_mac(struct udevice *dev) 295 { 296 u32 i, macaddrlow, macaddrhigh; 297 struct eth_pdata *pdata = dev_get_platdata(dev); 298 struct zynq_gem_priv *priv = dev_get_priv(dev); 299 struct zynq_gem_regs *regs = priv->iobase; 300 301 /* Set the MAC bits [31:0] in BOT */ 302 macaddrlow = pdata->enetaddr[0]; 303 macaddrlow |= pdata->enetaddr[1] << 8; 304 macaddrlow |= pdata->enetaddr[2] << 16; 305 macaddrlow |= pdata->enetaddr[3] << 24; 306 307 /* Set MAC bits [47:32] in TOP */ 308 macaddrhigh = pdata->enetaddr[4]; 309 macaddrhigh |= pdata->enetaddr[5] << 8; 310 311 for (i = 0; i < 4; i++) { 312 writel(0, ®s->laddr[i][LADDR_LOW]); 313 writel(0, ®s->laddr[i][LADDR_HIGH]); 314 /* Do not use MATCHx register */ 315 writel(0, ®s->match[i]); 316 } 317 318 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 319 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 320 321 return 0; 322 } 323 324 static int zynq_phy_init(struct udevice *dev) 325 { 326 int ret; 327 struct zynq_gem_priv *priv = dev_get_priv(dev); 328 struct zynq_gem_regs *regs = priv->iobase; 329 const u32 supported = SUPPORTED_10baseT_Half | 330 SUPPORTED_10baseT_Full | 331 SUPPORTED_100baseT_Half | 332 SUPPORTED_100baseT_Full | 333 SUPPORTED_1000baseT_Half | 334 SUPPORTED_1000baseT_Full; 335 336 /* Enable only MDIO bus */ 337 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 338 339 if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 340 ret = phy_detection(dev); 341 if (ret) { 342 printf("GEM PHY init failed\n"); 343 return ret; 344 } 345 } 346 347 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 348 priv->interface); 349 if (!priv->phydev) 350 return -ENODEV; 351 352 priv->phydev->supported = supported | ADVERTISED_Pause | 353 ADVERTISED_Asym_Pause; 354 priv->phydev->advertising = priv->phydev->supported; 355 phy_config(priv->phydev); 356 357 return 0; 358 } 359 360 static int zynq_gem_init(struct udevice *dev) 361 { 362 u32 i, nwconfig; 363 int ret; 364 unsigned long clk_rate = 0; 365 struct zynq_gem_priv *priv = dev_get_priv(dev); 366 struct zynq_gem_regs *regs = priv->iobase; 367 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 368 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 369 370 if (!priv->init) { 371 /* Disable all interrupts */ 372 writel(0xFFFFFFFF, ®s->idr); 373 374 /* Disable the receiver & transmitter */ 375 writel(0, ®s->nwctrl); 376 writel(0, ®s->txsr); 377 writel(0, ®s->rxsr); 378 writel(0, ®s->phymntnc); 379 380 /* Clear the Hash registers for the mac address 381 * pointed by AddressPtr 382 */ 383 writel(0x0, ®s->hashl); 384 /* Write bits [63:32] in TOP */ 385 writel(0x0, ®s->hashh); 386 387 /* Clear all counters */ 388 for (i = 0; i < STAT_SIZE; i++) 389 readl(®s->stat[i]); 390 391 /* Setup RxBD space */ 392 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 393 394 for (i = 0; i < RX_BUF; i++) { 395 priv->rx_bd[i].status = 0xF0000000; 396 priv->rx_bd[i].addr = 397 ((ulong)(priv->rxbuffers) + 398 (i * PKTSIZE_ALIGN)); 399 } 400 /* WRAP bit to last BD */ 401 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 402 /* Write RxBDs to IP */ 403 writel((ulong)priv->rx_bd, ®s->rxqbase); 404 405 /* Setup for DMA Configuration register */ 406 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 407 408 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 409 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 410 411 /* Disable the second priority queue */ 412 dummy_tx_bd->addr = 0; 413 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 414 ZYNQ_GEM_TXBUF_LAST_MASK| 415 ZYNQ_GEM_TXBUF_USED_MASK; 416 417 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 418 ZYNQ_GEM_RXBUF_NEW_MASK; 419 dummy_rx_bd->status = 0; 420 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 421 sizeof(dummy_tx_bd)); 422 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 423 sizeof(dummy_rx_bd)); 424 425 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 426 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 427 428 priv->init++; 429 } 430 431 ret = phy_startup(priv->phydev); 432 if (ret) 433 return ret; 434 435 if (!priv->phydev->link) { 436 printf("%s: No link.\n", priv->phydev->dev->name); 437 return -1; 438 } 439 440 nwconfig = ZYNQ_GEM_NWCFG_INIT; 441 442 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 443 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 444 ZYNQ_GEM_NWCFG_PCS_SEL; 445 #ifdef CONFIG_ARM64 446 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 447 ®s->pcscntrl); 448 #endif 449 } 450 451 switch (priv->phydev->speed) { 452 case SPEED_1000: 453 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 454 ®s->nwcfg); 455 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 456 break; 457 case SPEED_100: 458 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 459 ®s->nwcfg); 460 clk_rate = ZYNQ_GEM_FREQUENCY_100; 461 break; 462 case SPEED_10: 463 clk_rate = ZYNQ_GEM_FREQUENCY_10; 464 break; 465 } 466 467 /* Change the rclk and clk only not using EMIO interface */ 468 if (!priv->emio) 469 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 470 ZYNQ_GEM_BASEADDR0, clk_rate); 471 472 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 473 ZYNQ_GEM_NWCTRL_TXEN_MASK); 474 475 return 0; 476 } 477 478 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 479 { 480 u32 addr, size; 481 struct zynq_gem_priv *priv = dev_get_priv(dev); 482 struct zynq_gem_regs *regs = priv->iobase; 483 struct emac_bd *current_bd = &priv->tx_bd[1]; 484 485 /* Setup Tx BD */ 486 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 487 488 priv->tx_bd->addr = (ulong)ptr; 489 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 490 ZYNQ_GEM_TXBUF_LAST_MASK; 491 /* Dummy descriptor to mark it as the last in descriptor chain */ 492 current_bd->addr = 0x0; 493 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 494 ZYNQ_GEM_TXBUF_LAST_MASK| 495 ZYNQ_GEM_TXBUF_USED_MASK; 496 497 /* setup BD */ 498 writel((ulong)priv->tx_bd, ®s->txqbase); 499 500 addr = (ulong) ptr; 501 addr &= ~(ARCH_DMA_MINALIGN - 1); 502 size = roundup(len, ARCH_DMA_MINALIGN); 503 flush_dcache_range(addr, addr + size); 504 505 addr = (ulong)priv->rxbuffers; 506 addr &= ~(ARCH_DMA_MINALIGN - 1); 507 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 508 flush_dcache_range(addr, addr + size); 509 barrier(); 510 511 /* Start transmit */ 512 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 513 514 /* Read TX BD status */ 515 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 516 printf("TX buffers exhausted in mid frame\n"); 517 518 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 519 true, 20000, true); 520 } 521 522 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 523 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 524 { 525 int frame_len; 526 u32 addr; 527 struct zynq_gem_priv *priv = dev_get_priv(dev); 528 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 529 530 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 531 return -1; 532 533 if (!(current_bd->status & 534 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 535 printf("GEM: SOF or EOF not set for last buffer received!\n"); 536 return -1; 537 } 538 539 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 540 if (!frame_len) { 541 printf("%s: Zero size packet?\n", __func__); 542 return -1; 543 } 544 545 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 546 addr &= ~(ARCH_DMA_MINALIGN - 1); 547 *packetp = (uchar *)(uintptr_t)addr; 548 549 return frame_len; 550 } 551 552 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 553 { 554 struct zynq_gem_priv *priv = dev_get_priv(dev); 555 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 556 struct emac_bd *first_bd; 557 558 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 559 priv->rx_first_buf = priv->rxbd_current; 560 } else { 561 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 562 current_bd->status = 0xF0000000; /* FIXME */ 563 } 564 565 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 566 first_bd = &priv->rx_bd[priv->rx_first_buf]; 567 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 568 first_bd->status = 0xF0000000; 569 } 570 571 if ((++priv->rxbd_current) >= RX_BUF) 572 priv->rxbd_current = 0; 573 574 return 0; 575 } 576 577 static void zynq_gem_halt(struct udevice *dev) 578 { 579 struct zynq_gem_priv *priv = dev_get_priv(dev); 580 struct zynq_gem_regs *regs = priv->iobase; 581 582 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 583 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 584 } 585 586 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 587 { 588 return -ENOSYS; 589 } 590 591 static int zynq_gem_read_rom_mac(struct udevice *dev) 592 { 593 int retval; 594 struct eth_pdata *pdata = dev_get_platdata(dev); 595 596 retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); 597 if (retval == -ENOSYS) 598 retval = 0; 599 600 return retval; 601 } 602 603 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 604 int devad, int reg) 605 { 606 struct zynq_gem_priv *priv = bus->priv; 607 int ret; 608 u16 val; 609 610 ret = phyread(priv, addr, reg, &val); 611 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 612 return val; 613 } 614 615 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 616 int reg, u16 value) 617 { 618 struct zynq_gem_priv *priv = bus->priv; 619 620 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 621 return phywrite(priv, addr, reg, value); 622 } 623 624 static int zynq_gem_probe(struct udevice *dev) 625 { 626 void *bd_space; 627 struct zynq_gem_priv *priv = dev_get_priv(dev); 628 int ret; 629 630 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 631 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 632 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 633 634 /* Align bd_space to MMU_SECTION_SHIFT */ 635 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 636 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 637 BD_SPACE, DCACHE_OFF); 638 639 /* Initialize the bd spaces for tx and rx bd's */ 640 priv->tx_bd = (struct emac_bd *)bd_space; 641 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 642 643 priv->bus = mdio_alloc(); 644 priv->bus->read = zynq_gem_miiphy_read; 645 priv->bus->write = zynq_gem_miiphy_write; 646 priv->bus->priv = priv; 647 strcpy(priv->bus->name, "gem"); 648 649 ret = mdio_register(priv->bus); 650 if (ret) 651 return ret; 652 653 return zynq_phy_init(dev); 654 } 655 656 static int zynq_gem_remove(struct udevice *dev) 657 { 658 struct zynq_gem_priv *priv = dev_get_priv(dev); 659 660 free(priv->phydev); 661 mdio_unregister(priv->bus); 662 mdio_free(priv->bus); 663 664 return 0; 665 } 666 667 static const struct eth_ops zynq_gem_ops = { 668 .start = zynq_gem_init, 669 .send = zynq_gem_send, 670 .recv = zynq_gem_recv, 671 .free_pkt = zynq_gem_free_pkt, 672 .stop = zynq_gem_halt, 673 .write_hwaddr = zynq_gem_setup_mac, 674 .read_rom_hwaddr = zynq_gem_read_rom_mac, 675 }; 676 677 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 678 { 679 struct eth_pdata *pdata = dev_get_platdata(dev); 680 struct zynq_gem_priv *priv = dev_get_priv(dev); 681 int offset = 0; 682 const char *phy_mode; 683 684 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 685 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 686 /* Hardcode for now */ 687 priv->emio = 0; 688 priv->phyaddr = -1; 689 690 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 691 "phy-handle"); 692 if (offset > 0) 693 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 694 695 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 696 if (phy_mode) 697 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 698 if (pdata->phy_interface == -1) { 699 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 700 return -EINVAL; 701 } 702 priv->interface = pdata->phy_interface; 703 704 priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); 705 706 printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 707 priv->phyaddr, phy_string_for_interface(priv->interface)); 708 709 return 0; 710 } 711 712 static const struct udevice_id zynq_gem_ids[] = { 713 { .compatible = "cdns,zynqmp-gem" }, 714 { .compatible = "cdns,zynq-gem" }, 715 { .compatible = "cdns,gem" }, 716 { } 717 }; 718 719 U_BOOT_DRIVER(zynq_gem) = { 720 .name = "zynq_gem", 721 .id = UCLASS_ETH, 722 .of_match = zynq_gem_ids, 723 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 724 .probe = zynq_gem_probe, 725 .remove = zynq_gem_remove, 726 .ops = &zynq_gem_ops, 727 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 728 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 729 }; 730