1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <config.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <wait_bit.h> 23 #include <watchdog.h> 24 #include <asm/system.h> 25 #include <asm/arch/hardware.h> 26 #include <asm/arch/sys_proto.h> 27 #include <linux/errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ 61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ 62 #ifdef CONFIG_ARM64 63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ 64 #else 65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ 66 #endif 67 68 #ifdef CONFIG_ARM64 69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 70 #else 71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 72 #endif 73 74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 75 ZYNQ_GEM_NWCFG_FDEN | \ 76 ZYNQ_GEM_NWCFG_FSREM | \ 77 ZYNQ_GEM_NWCFG_MDCCLKDIV) 78 79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 80 81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 82 /* Use full configured addressable space (8 Kb) */ 83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 84 /* Use full configured addressable space (4 Kb) */ 85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 88 89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 90 ZYNQ_GEM_DMACR_RXSIZE | \ 91 ZYNQ_GEM_DMACR_TXSIZE | \ 92 ZYNQ_GEM_DMACR_RXBUF) 93 94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 95 96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 97 98 /* Use MII register 1 (MII status register) to detect PHY */ 99 #define PHY_DETECT_REG 1 100 101 /* Mask used to verify certain PHY features (or register contents) 102 * in the register above: 103 * 0x1000: 10Mbps full duplex support 104 * 0x0800: 10Mbps half duplex support 105 * 0x0008: Auto-negotiation support 106 */ 107 #define PHY_DETECT_MASK 0x1808 108 109 /* TX BD status masks */ 110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 113 114 /* Clock frequencies for different speeds */ 115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 118 119 /* Device registers */ 120 struct zynq_gem_regs { 121 u32 nwctrl; /* 0x0 - Network Control reg */ 122 u32 nwcfg; /* 0x4 - Network Config reg */ 123 u32 nwsr; /* 0x8 - Network Status reg */ 124 u32 reserved1; 125 u32 dmacr; /* 0x10 - DMA Control reg */ 126 u32 txsr; /* 0x14 - TX Status reg */ 127 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 128 u32 txqbase; /* 0x1c - TX Q Base address reg */ 129 u32 rxsr; /* 0x20 - RX Status reg */ 130 u32 reserved2[2]; 131 u32 idr; /* 0x2c - Interrupt Disable reg */ 132 u32 reserved3; 133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 134 u32 reserved4[18]; 135 u32 hashl; /* 0x80 - Hash Low address reg */ 136 u32 hashh; /* 0x84 - Hash High address reg */ 137 #define LADDR_LOW 0 138 #define LADDR_HIGH 1 139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 141 u32 reserved6[18]; 142 #define STAT_SIZE 44 143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 144 u32 reserved9[20]; 145 u32 pcscntrl; 146 u32 reserved7[143]; 147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 148 u32 reserved8[15]; 149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 150 }; 151 152 /* BD descriptors */ 153 struct emac_bd { 154 u32 addr; /* Next descriptor pointer */ 155 u32 status; 156 }; 157 158 #define RX_BUF 32 159 /* Page table entries are set to 1MB, or multiples of 1MB 160 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 161 */ 162 #define BD_SPACE 0x100000 163 /* BD separation space */ 164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 165 166 /* Setup the first free TX descriptor */ 167 #define TX_FREE_DESC 2 168 169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 170 struct zynq_gem_priv { 171 struct emac_bd *tx_bd; 172 struct emac_bd *rx_bd; 173 char *rxbuffers; 174 u32 rxbd_current; 175 u32 rx_first_buf; 176 int phyaddr; 177 u32 emio; 178 int init; 179 struct zynq_gem_regs *iobase; 180 phy_interface_t interface; 181 struct phy_device *phydev; 182 int phy_of_handle; 183 struct mii_dev *bus; 184 }; 185 186 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, 187 u32 op, u16 *data) 188 { 189 u32 mgtcr; 190 struct zynq_gem_regs *regs = priv->iobase; 191 int err; 192 193 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 194 true, 20000, true); 195 if (err) 196 return err; 197 198 /* Construct mgtcr mask for the operation */ 199 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 200 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 201 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 202 203 /* Write mgtcr and wait for completion */ 204 writel(mgtcr, ®s->phymntnc); 205 206 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, 207 true, 20000, true); 208 if (err) 209 return err; 210 211 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 212 *data = readl(®s->phymntnc); 213 214 return 0; 215 } 216 217 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, 218 u32 regnum, u16 *val) 219 { 220 u32 ret; 221 222 ret = phy_setup_op(priv, phy_addr, regnum, 223 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 224 225 if (!ret) 226 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 227 phy_addr, regnum, *val); 228 229 return ret; 230 } 231 232 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, 233 u32 regnum, u16 data) 234 { 235 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 236 regnum, data); 237 238 return phy_setup_op(priv, phy_addr, regnum, 239 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 240 } 241 242 static int phy_detection(struct udevice *dev) 243 { 244 int i; 245 u16 phyreg; 246 struct zynq_gem_priv *priv = dev->priv; 247 248 if (priv->phyaddr != -1) { 249 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); 250 if ((phyreg != 0xFFFF) && 251 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 252 /* Found a valid PHY address */ 253 debug("Default phy address %d is valid\n", 254 priv->phyaddr); 255 return 0; 256 } else { 257 debug("PHY address is not setup correctly %d\n", 258 priv->phyaddr); 259 priv->phyaddr = -1; 260 } 261 } 262 263 debug("detecting phy address\n"); 264 if (priv->phyaddr == -1) { 265 /* detect the PHY address */ 266 for (i = 31; i >= 0; i--) { 267 phyread(priv, i, PHY_DETECT_REG, &phyreg); 268 if ((phyreg != 0xFFFF) && 269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 270 /* Found a valid PHY address */ 271 priv->phyaddr = i; 272 debug("Found valid phy address, %d\n", i); 273 return 0; 274 } 275 } 276 } 277 printf("PHY is not detected\n"); 278 return -1; 279 } 280 281 static int zynq_gem_setup_mac(struct udevice *dev) 282 { 283 u32 i, macaddrlow, macaddrhigh; 284 struct eth_pdata *pdata = dev_get_platdata(dev); 285 struct zynq_gem_priv *priv = dev_get_priv(dev); 286 struct zynq_gem_regs *regs = priv->iobase; 287 288 /* Set the MAC bits [31:0] in BOT */ 289 macaddrlow = pdata->enetaddr[0]; 290 macaddrlow |= pdata->enetaddr[1] << 8; 291 macaddrlow |= pdata->enetaddr[2] << 16; 292 macaddrlow |= pdata->enetaddr[3] << 24; 293 294 /* Set MAC bits [47:32] in TOP */ 295 macaddrhigh = pdata->enetaddr[4]; 296 macaddrhigh |= pdata->enetaddr[5] << 8; 297 298 for (i = 0; i < 4; i++) { 299 writel(0, ®s->laddr[i][LADDR_LOW]); 300 writel(0, ®s->laddr[i][LADDR_HIGH]); 301 /* Do not use MATCHx register */ 302 writel(0, ®s->match[i]); 303 } 304 305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 307 308 return 0; 309 } 310 311 static int zynq_phy_init(struct udevice *dev) 312 { 313 int ret; 314 struct zynq_gem_priv *priv = dev_get_priv(dev); 315 struct zynq_gem_regs *regs = priv->iobase; 316 const u32 supported = SUPPORTED_10baseT_Half | 317 SUPPORTED_10baseT_Full | 318 SUPPORTED_100baseT_Half | 319 SUPPORTED_100baseT_Full | 320 SUPPORTED_1000baseT_Half | 321 SUPPORTED_1000baseT_Full; 322 323 /* Enable only MDIO bus */ 324 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); 325 326 if (priv->interface != PHY_INTERFACE_MODE_SGMII) { 327 ret = phy_detection(dev); 328 if (ret) { 329 printf("GEM PHY init failed\n"); 330 return ret; 331 } 332 } 333 334 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, 335 priv->interface); 336 if (!priv->phydev) 337 return -ENODEV; 338 339 priv->phydev->supported = supported | ADVERTISED_Pause | 340 ADVERTISED_Asym_Pause; 341 priv->phydev->advertising = priv->phydev->supported; 342 343 if (priv->phy_of_handle > 0) 344 priv->phydev->dev->of_offset = priv->phy_of_handle; 345 346 return phy_config(priv->phydev); 347 } 348 349 static int zynq_gem_init(struct udevice *dev) 350 { 351 u32 i, nwconfig; 352 int ret; 353 unsigned long clk_rate = 0; 354 struct zynq_gem_priv *priv = dev_get_priv(dev); 355 struct zynq_gem_regs *regs = priv->iobase; 356 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 357 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 358 359 if (!priv->init) { 360 /* Disable all interrupts */ 361 writel(0xFFFFFFFF, ®s->idr); 362 363 /* Disable the receiver & transmitter */ 364 writel(0, ®s->nwctrl); 365 writel(0, ®s->txsr); 366 writel(0, ®s->rxsr); 367 writel(0, ®s->phymntnc); 368 369 /* Clear the Hash registers for the mac address 370 * pointed by AddressPtr 371 */ 372 writel(0x0, ®s->hashl); 373 /* Write bits [63:32] in TOP */ 374 writel(0x0, ®s->hashh); 375 376 /* Clear all counters */ 377 for (i = 0; i < STAT_SIZE; i++) 378 readl(®s->stat[i]); 379 380 /* Setup RxBD space */ 381 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 382 383 for (i = 0; i < RX_BUF; i++) { 384 priv->rx_bd[i].status = 0xF0000000; 385 priv->rx_bd[i].addr = 386 ((ulong)(priv->rxbuffers) + 387 (i * PKTSIZE_ALIGN)); 388 } 389 /* WRAP bit to last BD */ 390 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 391 /* Write RxBDs to IP */ 392 writel((ulong)priv->rx_bd, ®s->rxqbase); 393 394 /* Setup for DMA Configuration register */ 395 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 396 397 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 398 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 399 400 /* Disable the second priority queue */ 401 dummy_tx_bd->addr = 0; 402 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 403 ZYNQ_GEM_TXBUF_LAST_MASK| 404 ZYNQ_GEM_TXBUF_USED_MASK; 405 406 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 407 ZYNQ_GEM_RXBUF_NEW_MASK; 408 dummy_rx_bd->status = 0; 409 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 410 sizeof(dummy_tx_bd)); 411 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 412 sizeof(dummy_rx_bd)); 413 414 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 415 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 416 417 priv->init++; 418 } 419 420 ret = phy_startup(priv->phydev); 421 if (ret) 422 return ret; 423 424 if (!priv->phydev->link) { 425 printf("%s: No link.\n", priv->phydev->dev->name); 426 return -1; 427 } 428 429 nwconfig = ZYNQ_GEM_NWCFG_INIT; 430 431 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 432 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | 433 ZYNQ_GEM_NWCFG_PCS_SEL; 434 #ifdef CONFIG_ARM64 435 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, 436 ®s->pcscntrl); 437 #endif 438 } 439 440 switch (priv->phydev->speed) { 441 case SPEED_1000: 442 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, 443 ®s->nwcfg); 444 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 445 break; 446 case SPEED_100: 447 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, 448 ®s->nwcfg); 449 clk_rate = ZYNQ_GEM_FREQUENCY_100; 450 break; 451 case SPEED_10: 452 clk_rate = ZYNQ_GEM_FREQUENCY_10; 453 break; 454 } 455 456 /* Change the rclk and clk only not using EMIO interface */ 457 if (!priv->emio) 458 zynq_slcr_gem_clk_setup((ulong)priv->iobase != 459 ZYNQ_GEM_BASEADDR0, clk_rate); 460 461 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 462 ZYNQ_GEM_NWCTRL_TXEN_MASK); 463 464 return 0; 465 } 466 467 static int zynq_gem_send(struct udevice *dev, void *ptr, int len) 468 { 469 u32 addr, size; 470 struct zynq_gem_priv *priv = dev_get_priv(dev); 471 struct zynq_gem_regs *regs = priv->iobase; 472 struct emac_bd *current_bd = &priv->tx_bd[1]; 473 474 /* Setup Tx BD */ 475 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 476 477 priv->tx_bd->addr = (ulong)ptr; 478 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 479 ZYNQ_GEM_TXBUF_LAST_MASK; 480 /* Dummy descriptor to mark it as the last in descriptor chain */ 481 current_bd->addr = 0x0; 482 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 483 ZYNQ_GEM_TXBUF_LAST_MASK| 484 ZYNQ_GEM_TXBUF_USED_MASK; 485 486 /* setup BD */ 487 writel((ulong)priv->tx_bd, ®s->txqbase); 488 489 addr = (ulong) ptr; 490 addr &= ~(ARCH_DMA_MINALIGN - 1); 491 size = roundup(len, ARCH_DMA_MINALIGN); 492 flush_dcache_range(addr, addr + size); 493 494 addr = (ulong)priv->rxbuffers; 495 addr &= ~(ARCH_DMA_MINALIGN - 1); 496 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 497 flush_dcache_range(addr, addr + size); 498 barrier(); 499 500 /* Start transmit */ 501 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 502 503 /* Read TX BD status */ 504 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 505 printf("TX buffers exhausted in mid frame\n"); 506 507 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 508 true, 20000, true); 509 } 510 511 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 512 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) 513 { 514 int frame_len; 515 u32 addr; 516 struct zynq_gem_priv *priv = dev_get_priv(dev); 517 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 518 519 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 520 return -1; 521 522 if (!(current_bd->status & 523 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 524 printf("GEM: SOF or EOF not set for last buffer received!\n"); 525 return -1; 526 } 527 528 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 529 if (!frame_len) { 530 printf("%s: Zero size packet?\n", __func__); 531 return -1; 532 } 533 534 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 535 addr &= ~(ARCH_DMA_MINALIGN - 1); 536 *packetp = (uchar *)(uintptr_t)addr; 537 538 return frame_len; 539 } 540 541 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) 542 { 543 struct zynq_gem_priv *priv = dev_get_priv(dev); 544 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 545 struct emac_bd *first_bd; 546 547 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { 548 priv->rx_first_buf = priv->rxbd_current; 549 } else { 550 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 551 current_bd->status = 0xF0000000; /* FIXME */ 552 } 553 554 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 555 first_bd = &priv->rx_bd[priv->rx_first_buf]; 556 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 557 first_bd->status = 0xF0000000; 558 } 559 560 if ((++priv->rxbd_current) >= RX_BUF) 561 priv->rxbd_current = 0; 562 563 return 0; 564 } 565 566 static void zynq_gem_halt(struct udevice *dev) 567 { 568 struct zynq_gem_priv *priv = dev_get_priv(dev); 569 struct zynq_gem_regs *regs = priv->iobase; 570 571 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 572 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 573 } 574 575 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 576 { 577 return -ENOSYS; 578 } 579 580 static int zynq_gem_read_rom_mac(struct udevice *dev) 581 { 582 int retval; 583 struct eth_pdata *pdata = dev_get_platdata(dev); 584 585 retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); 586 if (retval == -ENOSYS) 587 retval = 0; 588 589 return retval; 590 } 591 592 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, 593 int devad, int reg) 594 { 595 struct zynq_gem_priv *priv = bus->priv; 596 int ret; 597 u16 val; 598 599 ret = phyread(priv, addr, reg, &val); 600 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); 601 return val; 602 } 603 604 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, 605 int reg, u16 value) 606 { 607 struct zynq_gem_priv *priv = bus->priv; 608 609 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); 610 return phywrite(priv, addr, reg, value); 611 } 612 613 static int zynq_gem_probe(struct udevice *dev) 614 { 615 void *bd_space; 616 struct zynq_gem_priv *priv = dev_get_priv(dev); 617 int ret; 618 619 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 620 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 621 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 622 623 /* Align bd_space to MMU_SECTION_SHIFT */ 624 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 625 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 626 BD_SPACE, DCACHE_OFF); 627 628 /* Initialize the bd spaces for tx and rx bd's */ 629 priv->tx_bd = (struct emac_bd *)bd_space; 630 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 631 632 priv->bus = mdio_alloc(); 633 priv->bus->read = zynq_gem_miiphy_read; 634 priv->bus->write = zynq_gem_miiphy_write; 635 priv->bus->priv = priv; 636 637 ret = mdio_register_seq(priv->bus, dev->seq); 638 if (ret) 639 return ret; 640 641 return zynq_phy_init(dev); 642 } 643 644 static int zynq_gem_remove(struct udevice *dev) 645 { 646 struct zynq_gem_priv *priv = dev_get_priv(dev); 647 648 free(priv->phydev); 649 mdio_unregister(priv->bus); 650 mdio_free(priv->bus); 651 652 return 0; 653 } 654 655 static const struct eth_ops zynq_gem_ops = { 656 .start = zynq_gem_init, 657 .send = zynq_gem_send, 658 .recv = zynq_gem_recv, 659 .free_pkt = zynq_gem_free_pkt, 660 .stop = zynq_gem_halt, 661 .write_hwaddr = zynq_gem_setup_mac, 662 .read_rom_hwaddr = zynq_gem_read_rom_mac, 663 }; 664 665 static int zynq_gem_ofdata_to_platdata(struct udevice *dev) 666 { 667 struct eth_pdata *pdata = dev_get_platdata(dev); 668 struct zynq_gem_priv *priv = dev_get_priv(dev); 669 const char *phy_mode; 670 671 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 672 priv->iobase = (struct zynq_gem_regs *)pdata->iobase; 673 /* Hardcode for now */ 674 priv->emio = 0; 675 priv->phyaddr = -1; 676 677 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, 678 dev->of_offset, "phy-handle"); 679 if (priv->phy_of_handle > 0) 680 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, 681 priv->phy_of_handle, "reg", -1); 682 683 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 684 if (phy_mode) 685 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 686 if (pdata->phy_interface == -1) { 687 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 688 return -EINVAL; 689 } 690 priv->interface = pdata->phy_interface; 691 692 priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); 693 694 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, 695 priv->phyaddr, phy_string_for_interface(priv->interface)); 696 697 return 0; 698 } 699 700 static const struct udevice_id zynq_gem_ids[] = { 701 { .compatible = "cdns,zynqmp-gem" }, 702 { .compatible = "cdns,zynq-gem" }, 703 { .compatible = "cdns,gem" }, 704 { } 705 }; 706 707 U_BOOT_DRIVER(zynq_gem) = { 708 .name = "zynq_gem", 709 .id = UCLASS_ETH, 710 .of_match = zynq_gem_ids, 711 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, 712 .probe = zynq_gem_probe, 713 .remove = zynq_gem_remove, 714 .ops = &zynq_gem_ops, 715 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), 716 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 717 }; 718