1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <config.h> 16 #include <fdtdec.h> 17 #include <libfdt.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <watchdog.h> 23 #include <asm/system.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm-generic/errno.h> 27 28 #if !defined(CONFIG_PHYLIB) 29 # error XILINX_GEM_ETHERNET requires PHYLIB 30 #endif 31 32 /* Bit/mask specification */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 38 39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 42 43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 46 47 /* Wrap bit, last descriptor */ 48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 51 52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 56 57 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 59 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 60 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 62 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 63 64 #ifdef CONFIG_ARM64 65 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 66 #else 67 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 68 #endif 69 70 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 71 ZYNQ_GEM_NWCFG_FDEN | \ 72 ZYNQ_GEM_NWCFG_FSREM | \ 73 ZYNQ_GEM_NWCFG_MDCCLKDIV) 74 75 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 76 77 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 78 /* Use full configured addressable space (8 Kb) */ 79 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 80 /* Use full configured addressable space (4 Kb) */ 81 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 82 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 83 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 84 85 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 86 ZYNQ_GEM_DMACR_RXSIZE | \ 87 ZYNQ_GEM_DMACR_TXSIZE | \ 88 ZYNQ_GEM_DMACR_RXBUF) 89 90 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ 91 92 /* Use MII register 1 (MII status register) to detect PHY */ 93 #define PHY_DETECT_REG 1 94 95 /* Mask used to verify certain PHY features (or register contents) 96 * in the register above: 97 * 0x1000: 10Mbps full duplex support 98 * 0x0800: 10Mbps half duplex support 99 * 0x0008: Auto-negotiation support 100 */ 101 #define PHY_DETECT_MASK 0x1808 102 103 /* TX BD status masks */ 104 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 105 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 106 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 107 108 /* Clock frequencies for different speeds */ 109 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 110 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 111 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 112 113 /* Device registers */ 114 struct zynq_gem_regs { 115 u32 nwctrl; /* 0x0 - Network Control reg */ 116 u32 nwcfg; /* 0x4 - Network Config reg */ 117 u32 nwsr; /* 0x8 - Network Status reg */ 118 u32 reserved1; 119 u32 dmacr; /* 0x10 - DMA Control reg */ 120 u32 txsr; /* 0x14 - TX Status reg */ 121 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 122 u32 txqbase; /* 0x1c - TX Q Base address reg */ 123 u32 rxsr; /* 0x20 - RX Status reg */ 124 u32 reserved2[2]; 125 u32 idr; /* 0x2c - Interrupt Disable reg */ 126 u32 reserved3; 127 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 128 u32 reserved4[18]; 129 u32 hashl; /* 0x80 - Hash Low address reg */ 130 u32 hashh; /* 0x84 - Hash High address reg */ 131 #define LADDR_LOW 0 132 #define LADDR_HIGH 1 133 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 134 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 135 u32 reserved6[18]; 136 #define STAT_SIZE 44 137 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 138 u32 reserved7[164]; 139 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ 140 u32 reserved8[15]; 141 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ 142 }; 143 144 /* BD descriptors */ 145 struct emac_bd { 146 u32 addr; /* Next descriptor pointer */ 147 u32 status; 148 }; 149 150 #define RX_BUF 32 151 /* Page table entries are set to 1MB, or multiples of 1MB 152 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 153 */ 154 #define BD_SPACE 0x100000 155 /* BD separation space */ 156 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 157 158 /* Setup the first free TX descriptor */ 159 #define TX_FREE_DESC 2 160 161 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 162 struct zynq_gem_priv { 163 struct emac_bd *tx_bd; 164 struct emac_bd *rx_bd; 165 char *rxbuffers; 166 u32 rxbd_current; 167 u32 rx_first_buf; 168 int phyaddr; 169 u32 emio; 170 int init; 171 phy_interface_t interface; 172 struct phy_device *phydev; 173 struct mii_dev *bus; 174 }; 175 176 static inline int mdio_wait(struct eth_device *dev) 177 { 178 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 179 u32 timeout = 20000; 180 181 /* Wait till MDIO interface is ready to accept a new transaction. */ 182 while (--timeout) { 183 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 184 break; 185 WATCHDOG_RESET(); 186 } 187 188 if (!timeout) { 189 printf("%s: Timeout\n", __func__); 190 return 1; 191 } 192 193 return 0; 194 } 195 196 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 197 u32 op, u16 *data) 198 { 199 u32 mgtcr; 200 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 201 202 if (mdio_wait(dev)) 203 return 1; 204 205 /* Construct mgtcr mask for the operation */ 206 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 207 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 208 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 209 210 /* Write mgtcr and wait for completion */ 211 writel(mgtcr, ®s->phymntnc); 212 213 if (mdio_wait(dev)) 214 return 1; 215 216 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 217 *data = readl(®s->phymntnc); 218 219 return 0; 220 } 221 222 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 223 { 224 u32 ret; 225 226 ret = phy_setup_op(dev, phy_addr, regnum, 227 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 228 229 if (!ret) 230 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 231 phy_addr, regnum, *val); 232 233 return ret; 234 } 235 236 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 237 { 238 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 239 regnum, data); 240 241 return phy_setup_op(dev, phy_addr, regnum, 242 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 243 } 244 245 static void phy_detection(struct eth_device *dev) 246 { 247 int i; 248 u16 phyreg; 249 struct zynq_gem_priv *priv = dev->priv; 250 251 if (priv->phyaddr != -1) { 252 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 253 if ((phyreg != 0xFFFF) && 254 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 255 /* Found a valid PHY address */ 256 debug("Default phy address %d is valid\n", 257 priv->phyaddr); 258 return; 259 } else { 260 debug("PHY address is not setup correctly %d\n", 261 priv->phyaddr); 262 priv->phyaddr = -1; 263 } 264 } 265 266 debug("detecting phy address\n"); 267 if (priv->phyaddr == -1) { 268 /* detect the PHY address */ 269 for (i = 31; i >= 0; i--) { 270 phyread(dev, i, PHY_DETECT_REG, &phyreg); 271 if ((phyreg != 0xFFFF) && 272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 273 /* Found a valid PHY address */ 274 priv->phyaddr = i; 275 debug("Found valid phy address, %d\n", i); 276 return; 277 } 278 } 279 } 280 printf("PHY is not detected\n"); 281 } 282 283 static int zynq_gem_setup_mac(struct eth_device *dev) 284 { 285 u32 i, macaddrlow, macaddrhigh; 286 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 287 288 /* Set the MAC bits [31:0] in BOT */ 289 macaddrlow = dev->enetaddr[0]; 290 macaddrlow |= dev->enetaddr[1] << 8; 291 macaddrlow |= dev->enetaddr[2] << 16; 292 macaddrlow |= dev->enetaddr[3] << 24; 293 294 /* Set MAC bits [47:32] in TOP */ 295 macaddrhigh = dev->enetaddr[4]; 296 macaddrhigh |= dev->enetaddr[5] << 8; 297 298 for (i = 0; i < 4; i++) { 299 writel(0, ®s->laddr[i][LADDR_LOW]); 300 writel(0, ®s->laddr[i][LADDR_HIGH]); 301 /* Do not use MATCHx register */ 302 writel(0, ®s->match[i]); 303 } 304 305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 307 308 return 0; 309 } 310 311 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 312 { 313 u32 i; 314 unsigned long clk_rate = 0; 315 struct phy_device *phydev; 316 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 317 struct zynq_gem_priv *priv = dev->priv; 318 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; 319 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; 320 const u32 supported = SUPPORTED_10baseT_Half | 321 SUPPORTED_10baseT_Full | 322 SUPPORTED_100baseT_Half | 323 SUPPORTED_100baseT_Full | 324 SUPPORTED_1000baseT_Half | 325 SUPPORTED_1000baseT_Full; 326 327 if (!priv->init) { 328 /* Disable all interrupts */ 329 writel(0xFFFFFFFF, ®s->idr); 330 331 /* Disable the receiver & transmitter */ 332 writel(0, ®s->nwctrl); 333 writel(0, ®s->txsr); 334 writel(0, ®s->rxsr); 335 writel(0, ®s->phymntnc); 336 337 /* Clear the Hash registers for the mac address 338 * pointed by AddressPtr 339 */ 340 writel(0x0, ®s->hashl); 341 /* Write bits [63:32] in TOP */ 342 writel(0x0, ®s->hashh); 343 344 /* Clear all counters */ 345 for (i = 0; i < STAT_SIZE; i++) 346 readl(®s->stat[i]); 347 348 /* Setup RxBD space */ 349 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 350 351 for (i = 0; i < RX_BUF; i++) { 352 priv->rx_bd[i].status = 0xF0000000; 353 priv->rx_bd[i].addr = 354 ((ulong)(priv->rxbuffers) + 355 (i * PKTSIZE_ALIGN)); 356 } 357 /* WRAP bit to last BD */ 358 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 359 /* Write RxBDs to IP */ 360 writel((ulong)priv->rx_bd, ®s->rxqbase); 361 362 /* Setup for DMA Configuration register */ 363 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 364 365 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 366 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 367 368 /* Disable the second priority queue */ 369 dummy_tx_bd->addr = 0; 370 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 371 ZYNQ_GEM_TXBUF_LAST_MASK| 372 ZYNQ_GEM_TXBUF_USED_MASK; 373 374 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | 375 ZYNQ_GEM_RXBUF_NEW_MASK; 376 dummy_rx_bd->status = 0; 377 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + 378 sizeof(dummy_tx_bd)); 379 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + 380 sizeof(dummy_rx_bd)); 381 382 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); 383 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); 384 385 priv->init++; 386 } 387 388 phy_detection(dev); 389 390 /* interface - look at tsec */ 391 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 392 priv->interface); 393 394 phydev->supported = supported | ADVERTISED_Pause | 395 ADVERTISED_Asym_Pause; 396 phydev->advertising = phydev->supported; 397 priv->phydev = phydev; 398 phy_config(phydev); 399 phy_startup(phydev); 400 401 if (!phydev->link) { 402 printf("%s: No link.\n", phydev->dev->name); 403 return -1; 404 } 405 406 switch (phydev->speed) { 407 case SPEED_1000: 408 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 409 ®s->nwcfg); 410 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 411 break; 412 case SPEED_100: 413 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, 414 ®s->nwcfg); 415 clk_rate = ZYNQ_GEM_FREQUENCY_100; 416 break; 417 case SPEED_10: 418 clk_rate = ZYNQ_GEM_FREQUENCY_10; 419 break; 420 } 421 422 /* Change the rclk and clk only not using EMIO interface */ 423 if (!priv->emio) 424 zynq_slcr_gem_clk_setup(dev->iobase != 425 ZYNQ_GEM_BASEADDR0, clk_rate); 426 427 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 428 ZYNQ_GEM_NWCTRL_TXEN_MASK); 429 430 return 0; 431 } 432 433 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 434 bool set, unsigned int timeout) 435 { 436 u32 val; 437 unsigned long start = get_timer(0); 438 439 while (1) { 440 val = readl(reg); 441 442 if (!set) 443 val = ~val; 444 445 if ((val & mask) == mask) 446 return 0; 447 448 if (get_timer(start) > timeout) 449 break; 450 451 udelay(1); 452 } 453 454 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 455 func, reg, mask, set); 456 457 return -ETIMEDOUT; 458 } 459 460 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 461 { 462 u32 addr, size; 463 struct zynq_gem_priv *priv = dev->priv; 464 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 465 struct emac_bd *current_bd = &priv->tx_bd[1]; 466 467 /* Setup Tx BD */ 468 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 469 470 priv->tx_bd->addr = (ulong)ptr; 471 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 472 ZYNQ_GEM_TXBUF_LAST_MASK; 473 /* Dummy descriptor to mark it as the last in descriptor chain */ 474 current_bd->addr = 0x0; 475 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 476 ZYNQ_GEM_TXBUF_LAST_MASK| 477 ZYNQ_GEM_TXBUF_USED_MASK; 478 479 /* setup BD */ 480 writel((ulong)priv->tx_bd, ®s->txqbase); 481 482 addr = (ulong) ptr; 483 addr &= ~(ARCH_DMA_MINALIGN - 1); 484 size = roundup(len, ARCH_DMA_MINALIGN); 485 flush_dcache_range(addr, addr + size); 486 487 addr = (ulong)priv->rxbuffers; 488 addr &= ~(ARCH_DMA_MINALIGN - 1); 489 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 490 flush_dcache_range(addr, addr + size); 491 barrier(); 492 493 /* Start transmit */ 494 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 495 496 /* Read TX BD status */ 497 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 498 printf("TX buffers exhausted in mid frame\n"); 499 500 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, 501 true, 20000); 502 } 503 504 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 505 static int zynq_gem_recv(struct eth_device *dev) 506 { 507 int frame_len; 508 struct zynq_gem_priv *priv = dev->priv; 509 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 510 struct emac_bd *first_bd; 511 512 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 513 return 0; 514 515 if (!(current_bd->status & 516 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 517 printf("GEM: SOF or EOF not set for last buffer received!\n"); 518 return 0; 519 } 520 521 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 522 if (frame_len) { 523 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 524 addr &= ~(ARCH_DMA_MINALIGN - 1); 525 526 net_process_received_packet((u8 *)(ulong)addr, frame_len); 527 528 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 529 priv->rx_first_buf = priv->rxbd_current; 530 else { 531 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 532 current_bd->status = 0xF0000000; /* FIXME */ 533 } 534 535 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 536 first_bd = &priv->rx_bd[priv->rx_first_buf]; 537 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 538 first_bd->status = 0xF0000000; 539 } 540 541 if ((++priv->rxbd_current) >= RX_BUF) 542 priv->rxbd_current = 0; 543 } 544 545 return frame_len; 546 } 547 548 static void zynq_gem_halt(struct eth_device *dev) 549 { 550 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 551 552 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 553 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 554 } 555 556 static int zynq_gem_miiphyread(const char *devname, uchar addr, 557 uchar reg, ushort *val) 558 { 559 struct eth_device *dev = eth_get_dev(); 560 int ret; 561 562 ret = phyread(dev, addr, reg, val); 563 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 564 return ret; 565 } 566 567 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 568 uchar reg, ushort val) 569 { 570 struct eth_device *dev = eth_get_dev(); 571 572 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 573 return phywrite(dev, addr, reg, val); 574 } 575 576 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 577 int phy_addr, u32 emio) 578 { 579 struct eth_device *dev; 580 struct zynq_gem_priv *priv; 581 void *bd_space; 582 583 dev = calloc(1, sizeof(*dev)); 584 if (dev == NULL) 585 return -1; 586 587 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 588 if (dev->priv == NULL) { 589 free(dev); 590 return -1; 591 } 592 priv = dev->priv; 593 594 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 595 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 596 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 597 598 /* Align bd_space to MMU_SECTION_SHIFT */ 599 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 600 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 601 BD_SPACE, DCACHE_OFF); 602 603 /* Initialize the bd spaces for tx and rx bd's */ 604 priv->tx_bd = (struct emac_bd *)bd_space; 605 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 606 607 priv->phyaddr = phy_addr; 608 priv->emio = emio; 609 610 #ifndef CONFIG_ZYNQ_GEM_INTERFACE 611 priv->interface = PHY_INTERFACE_MODE_MII; 612 #else 613 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 614 #endif 615 616 sprintf(dev->name, "Gem.%lx", base_addr); 617 618 dev->iobase = base_addr; 619 620 dev->init = zynq_gem_init; 621 dev->halt = zynq_gem_halt; 622 dev->send = zynq_gem_send; 623 dev->recv = zynq_gem_recv; 624 dev->write_hwaddr = zynq_gem_setup_mac; 625 626 eth_register(dev); 627 628 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 629 priv->bus = miiphy_get_dev_by_name(dev->name); 630 631 return 1; 632 } 633 634 #if CONFIG_IS_ENABLED(OF_CONTROL) 635 int zynq_gem_of_init(const void *blob) 636 { 637 int offset = 0; 638 u32 ret = 0; 639 u32 reg, phy_reg; 640 641 debug("ZYNQ GEM: Initialization\n"); 642 643 do { 644 offset = fdt_node_offset_by_compatible(blob, offset, 645 "xlnx,ps7-ethernet-1.00.a"); 646 if (offset != -1) { 647 reg = fdtdec_get_addr(blob, offset, "reg"); 648 if (reg != FDT_ADDR_T_NONE) { 649 offset = fdtdec_lookup_phandle(blob, offset, 650 "phy-handle"); 651 if (offset != -1) 652 phy_reg = fdtdec_get_addr(blob, offset, 653 "reg"); 654 else 655 phy_reg = 0; 656 657 debug("ZYNQ GEM: addr %x, phyaddr %x\n", 658 reg, phy_reg); 659 660 ret |= zynq_gem_initialize(NULL, reg, 661 phy_reg, 0); 662 663 } else { 664 debug("ZYNQ GEM: Can't get base address\n"); 665 return -1; 666 } 667 } 668 } while (offset != -1); 669 670 return ret; 671 } 672 #endif 673