1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <config.h> 16 #include <fdtdec.h> 17 #include <libfdt.h> 18 #include <malloc.h> 19 #include <asm/io.h> 20 #include <phy.h> 21 #include <miiphy.h> 22 #include <watchdog.h> 23 #include <asm/system.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/sys_proto.h> 26 27 #if !defined(CONFIG_PHYLIB) 28 # error XILINX_GEM_ETHERNET requires PHYLIB 29 #endif 30 31 /* Bit/mask specification */ 32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 37 38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 41 42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 45 46 /* Wrap bit, last descriptor */ 47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ 50 51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 55 56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 62 63 #ifdef CONFIG_ARM64 64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ 65 #else 66 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ 67 #endif 68 69 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ 70 ZYNQ_GEM_NWCFG_FDEN | \ 71 ZYNQ_GEM_NWCFG_FSREM | \ 72 ZYNQ_GEM_NWCFG_MDCCLKDIV) 73 74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 75 76 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 77 /* Use full configured addressable space (8 Kb) */ 78 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 79 /* Use full configured addressable space (4 Kb) */ 80 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 82 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 83 84 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 85 ZYNQ_GEM_DMACR_RXSIZE | \ 86 ZYNQ_GEM_DMACR_TXSIZE | \ 87 ZYNQ_GEM_DMACR_RXBUF) 88 89 /* Use MII register 1 (MII status register) to detect PHY */ 90 #define PHY_DETECT_REG 1 91 92 /* Mask used to verify certain PHY features (or register contents) 93 * in the register above: 94 * 0x1000: 10Mbps full duplex support 95 * 0x0800: 10Mbps half duplex support 96 * 0x0008: Auto-negotiation support 97 */ 98 #define PHY_DETECT_MASK 0x1808 99 100 /* TX BD status masks */ 101 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff 102 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 103 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 104 105 /* Clock frequencies for different speeds */ 106 #define ZYNQ_GEM_FREQUENCY_10 2500000UL 107 #define ZYNQ_GEM_FREQUENCY_100 25000000UL 108 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL 109 110 /* Device registers */ 111 struct zynq_gem_regs { 112 u32 nwctrl; /* 0x0 - Network Control reg */ 113 u32 nwcfg; /* 0x4 - Network Config reg */ 114 u32 nwsr; /* 0x8 - Network Status reg */ 115 u32 reserved1; 116 u32 dmacr; /* 0x10 - DMA Control reg */ 117 u32 txsr; /* 0x14 - TX Status reg */ 118 u32 rxqbase; /* 0x18 - RX Q Base address reg */ 119 u32 txqbase; /* 0x1c - TX Q Base address reg */ 120 u32 rxsr; /* 0x20 - RX Status reg */ 121 u32 reserved2[2]; 122 u32 idr; /* 0x2c - Interrupt Disable reg */ 123 u32 reserved3; 124 u32 phymntnc; /* 0x34 - Phy Maintaince reg */ 125 u32 reserved4[18]; 126 u32 hashl; /* 0x80 - Hash Low address reg */ 127 u32 hashh; /* 0x84 - Hash High address reg */ 128 #define LADDR_LOW 0 129 #define LADDR_HIGH 1 130 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ 131 u32 match[4]; /* 0xa8 - Type ID1 Match reg */ 132 u32 reserved6[18]; 133 #define STAT_SIZE 44 134 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ 135 }; 136 137 /* BD descriptors */ 138 struct emac_bd { 139 u32 addr; /* Next descriptor pointer */ 140 u32 status; 141 }; 142 143 #define RX_BUF 32 144 /* Page table entries are set to 1MB, or multiples of 1MB 145 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 146 */ 147 #define BD_SPACE 0x100000 148 /* BD separation space */ 149 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) 150 151 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 152 struct zynq_gem_priv { 153 struct emac_bd *tx_bd; 154 struct emac_bd *rx_bd; 155 char *rxbuffers; 156 u32 rxbd_current; 157 u32 rx_first_buf; 158 int phyaddr; 159 u32 emio; 160 int init; 161 phy_interface_t interface; 162 struct phy_device *phydev; 163 struct mii_dev *bus; 164 }; 165 166 static inline int mdio_wait(struct eth_device *dev) 167 { 168 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 169 u32 timeout = 20000; 170 171 /* Wait till MDIO interface is ready to accept a new transaction. */ 172 while (--timeout) { 173 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 174 break; 175 WATCHDOG_RESET(); 176 } 177 178 if (!timeout) { 179 printf("%s: Timeout\n", __func__); 180 return 1; 181 } 182 183 return 0; 184 } 185 186 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 187 u32 op, u16 *data) 188 { 189 u32 mgtcr; 190 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 191 192 if (mdio_wait(dev)) 193 return 1; 194 195 /* Construct mgtcr mask for the operation */ 196 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 197 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 198 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 199 200 /* Write mgtcr and wait for completion */ 201 writel(mgtcr, ®s->phymntnc); 202 203 if (mdio_wait(dev)) 204 return 1; 205 206 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 207 *data = readl(®s->phymntnc); 208 209 return 0; 210 } 211 212 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 213 { 214 u32 ret; 215 216 ret = phy_setup_op(dev, phy_addr, regnum, 217 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 218 219 if (!ret) 220 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, 221 phy_addr, regnum, *val); 222 223 return ret; 224 } 225 226 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 227 { 228 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, 229 regnum, data); 230 231 return phy_setup_op(dev, phy_addr, regnum, 232 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 233 } 234 235 static void phy_detection(struct eth_device *dev) 236 { 237 int i; 238 u16 phyreg; 239 struct zynq_gem_priv *priv = dev->priv; 240 241 if (priv->phyaddr != -1) { 242 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); 243 if ((phyreg != 0xFFFF) && 244 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 245 /* Found a valid PHY address */ 246 debug("Default phy address %d is valid\n", 247 priv->phyaddr); 248 return; 249 } else { 250 debug("PHY address is not setup correctly %d\n", 251 priv->phyaddr); 252 priv->phyaddr = -1; 253 } 254 } 255 256 debug("detecting phy address\n"); 257 if (priv->phyaddr == -1) { 258 /* detect the PHY address */ 259 for (i = 31; i >= 0; i--) { 260 phyread(dev, i, PHY_DETECT_REG, &phyreg); 261 if ((phyreg != 0xFFFF) && 262 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 263 /* Found a valid PHY address */ 264 priv->phyaddr = i; 265 debug("Found valid phy address, %d\n", i); 266 return; 267 } 268 } 269 } 270 printf("PHY is not detected\n"); 271 } 272 273 static int zynq_gem_setup_mac(struct eth_device *dev) 274 { 275 u32 i, macaddrlow, macaddrhigh; 276 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 277 278 /* Set the MAC bits [31:0] in BOT */ 279 macaddrlow = dev->enetaddr[0]; 280 macaddrlow |= dev->enetaddr[1] << 8; 281 macaddrlow |= dev->enetaddr[2] << 16; 282 macaddrlow |= dev->enetaddr[3] << 24; 283 284 /* Set MAC bits [47:32] in TOP */ 285 macaddrhigh = dev->enetaddr[4]; 286 macaddrhigh |= dev->enetaddr[5] << 8; 287 288 for (i = 0; i < 4; i++) { 289 writel(0, ®s->laddr[i][LADDR_LOW]); 290 writel(0, ®s->laddr[i][LADDR_HIGH]); 291 /* Do not use MATCHx register */ 292 writel(0, ®s->match[i]); 293 } 294 295 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 296 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 297 298 return 0; 299 } 300 301 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 302 { 303 u32 i; 304 unsigned long clk_rate = 0; 305 struct phy_device *phydev; 306 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 307 struct zynq_gem_priv *priv = dev->priv; 308 const u32 supported = SUPPORTED_10baseT_Half | 309 SUPPORTED_10baseT_Full | 310 SUPPORTED_100baseT_Half | 311 SUPPORTED_100baseT_Full | 312 SUPPORTED_1000baseT_Half | 313 SUPPORTED_1000baseT_Full; 314 315 if (!priv->init) { 316 /* Disable all interrupts */ 317 writel(0xFFFFFFFF, ®s->idr); 318 319 /* Disable the receiver & transmitter */ 320 writel(0, ®s->nwctrl); 321 writel(0, ®s->txsr); 322 writel(0, ®s->rxsr); 323 writel(0, ®s->phymntnc); 324 325 /* Clear the Hash registers for the mac address 326 * pointed by AddressPtr 327 */ 328 writel(0x0, ®s->hashl); 329 /* Write bits [63:32] in TOP */ 330 writel(0x0, ®s->hashh); 331 332 /* Clear all counters */ 333 for (i = 0; i < STAT_SIZE; i++) 334 readl(®s->stat[i]); 335 336 /* Setup RxBD space */ 337 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); 338 339 for (i = 0; i < RX_BUF; i++) { 340 priv->rx_bd[i].status = 0xF0000000; 341 priv->rx_bd[i].addr = 342 ((ulong)(priv->rxbuffers) + 343 (i * PKTSIZE_ALIGN)); 344 } 345 /* WRAP bit to last BD */ 346 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 347 /* Write RxBDs to IP */ 348 writel((ulong)priv->rx_bd, ®s->rxqbase); 349 350 /* Setup for DMA Configuration register */ 351 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 352 353 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 354 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 355 356 priv->init++; 357 } 358 359 phy_detection(dev); 360 361 /* interface - look at tsec */ 362 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 363 priv->interface); 364 365 phydev->supported = supported | ADVERTISED_Pause | 366 ADVERTISED_Asym_Pause; 367 phydev->advertising = phydev->supported; 368 priv->phydev = phydev; 369 phy_config(phydev); 370 phy_startup(phydev); 371 372 if (!phydev->link) { 373 printf("%s: No link.\n", phydev->dev->name); 374 return -1; 375 } 376 377 switch (phydev->speed) { 378 case SPEED_1000: 379 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 380 ®s->nwcfg); 381 clk_rate = ZYNQ_GEM_FREQUENCY_1000; 382 break; 383 case SPEED_100: 384 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 385 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 386 clk_rate = ZYNQ_GEM_FREQUENCY_100; 387 break; 388 case SPEED_10: 389 clk_rate = ZYNQ_GEM_FREQUENCY_10; 390 break; 391 } 392 393 /* Change the rclk and clk only not using EMIO interface */ 394 if (!priv->emio) 395 zynq_slcr_gem_clk_setup(dev->iobase != 396 ZYNQ_GEM_BASEADDR0, clk_rate); 397 398 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 399 ZYNQ_GEM_NWCTRL_TXEN_MASK); 400 401 return 0; 402 } 403 404 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 405 { 406 u32 addr, size; 407 struct zynq_gem_priv *priv = dev->priv; 408 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 409 struct emac_bd *current_bd = &priv->tx_bd[1]; 410 411 /* Setup Tx BD */ 412 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); 413 414 priv->tx_bd->addr = (ulong)ptr; 415 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | 416 ZYNQ_GEM_TXBUF_LAST_MASK; 417 /* Dummy descriptor to mark it as the last in descriptor chain */ 418 current_bd->addr = 0x0; 419 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | 420 ZYNQ_GEM_TXBUF_LAST_MASK| 421 ZYNQ_GEM_TXBUF_USED_MASK; 422 423 /* setup BD */ 424 writel((ulong)priv->tx_bd, ®s->txqbase); 425 426 addr = (ulong) ptr; 427 addr &= ~(ARCH_DMA_MINALIGN - 1); 428 size = roundup(len, ARCH_DMA_MINALIGN); 429 flush_dcache_range(addr, addr + size); 430 431 addr = (ulong)priv->rxbuffers; 432 addr &= ~(ARCH_DMA_MINALIGN - 1); 433 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); 434 flush_dcache_range(addr, addr + size); 435 barrier(); 436 437 /* Start transmit */ 438 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 439 440 /* Read TX BD status */ 441 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) 442 printf("TX buffers exhausted in mid frame\n"); 443 444 return 0; 445 } 446 447 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 448 static int zynq_gem_recv(struct eth_device *dev) 449 { 450 int frame_len; 451 struct zynq_gem_priv *priv = dev->priv; 452 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 453 struct emac_bd *first_bd; 454 455 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 456 return 0; 457 458 if (!(current_bd->status & 459 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 460 printf("GEM: SOF or EOF not set for last buffer received!\n"); 461 return 0; 462 } 463 464 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 465 if (frame_len) { 466 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; 467 addr &= ~(ARCH_DMA_MINALIGN - 1); 468 469 net_process_received_packet((u8 *)(ulong)addr, frame_len); 470 471 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 472 priv->rx_first_buf = priv->rxbd_current; 473 else { 474 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 475 current_bd->status = 0xF0000000; /* FIXME */ 476 } 477 478 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 479 first_bd = &priv->rx_bd[priv->rx_first_buf]; 480 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 481 first_bd->status = 0xF0000000; 482 } 483 484 if ((++priv->rxbd_current) >= RX_BUF) 485 priv->rxbd_current = 0; 486 } 487 488 return frame_len; 489 } 490 491 static void zynq_gem_halt(struct eth_device *dev) 492 { 493 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 494 495 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 496 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 497 } 498 499 static int zynq_gem_miiphyread(const char *devname, uchar addr, 500 uchar reg, ushort *val) 501 { 502 struct eth_device *dev = eth_get_dev(); 503 int ret; 504 505 ret = phyread(dev, addr, reg, val); 506 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 507 return ret; 508 } 509 510 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 511 uchar reg, ushort val) 512 { 513 struct eth_device *dev = eth_get_dev(); 514 515 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 516 return phywrite(dev, addr, reg, val); 517 } 518 519 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, 520 int phy_addr, u32 emio) 521 { 522 struct eth_device *dev; 523 struct zynq_gem_priv *priv; 524 void *bd_space; 525 526 dev = calloc(1, sizeof(*dev)); 527 if (dev == NULL) 528 return -1; 529 530 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 531 if (dev->priv == NULL) { 532 free(dev); 533 return -1; 534 } 535 priv = dev->priv; 536 537 /* Align rxbuffers to ARCH_DMA_MINALIGN */ 538 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); 539 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); 540 541 /* Align bd_space to MMU_SECTION_SHIFT */ 542 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 543 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, 544 BD_SPACE, DCACHE_OFF); 545 546 /* Initialize the bd spaces for tx and rx bd's */ 547 priv->tx_bd = (struct emac_bd *)bd_space; 548 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); 549 550 priv->phyaddr = phy_addr; 551 priv->emio = emio; 552 553 #ifndef CONFIG_ZYNQ_GEM_INTERFACE 554 priv->interface = PHY_INTERFACE_MODE_MII; 555 #else 556 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; 557 #endif 558 559 sprintf(dev->name, "Gem.%lx", base_addr); 560 561 dev->iobase = base_addr; 562 563 dev->init = zynq_gem_init; 564 dev->halt = zynq_gem_halt; 565 dev->send = zynq_gem_send; 566 dev->recv = zynq_gem_recv; 567 dev->write_hwaddr = zynq_gem_setup_mac; 568 569 eth_register(dev); 570 571 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 572 priv->bus = miiphy_get_dev_by_name(dev->name); 573 574 return 1; 575 } 576 577 #if CONFIG_IS_ENABLED(OF_CONTROL) 578 int zynq_gem_of_init(const void *blob) 579 { 580 int offset = 0; 581 u32 ret = 0; 582 u32 reg, phy_reg; 583 584 debug("ZYNQ GEM: Initialization\n"); 585 586 do { 587 offset = fdt_node_offset_by_compatible(blob, offset, 588 "xlnx,ps7-ethernet-1.00.a"); 589 if (offset != -1) { 590 reg = fdtdec_get_addr(blob, offset, "reg"); 591 if (reg != FDT_ADDR_T_NONE) { 592 offset = fdtdec_lookup_phandle(blob, offset, 593 "phy-handle"); 594 if (offset != -1) 595 phy_reg = fdtdec_get_addr(blob, offset, 596 "reg"); 597 else 598 phy_reg = 0; 599 600 debug("ZYNQ GEM: addr %x, phyaddr %x\n", 601 reg, phy_reg); 602 603 ret |= zynq_gem_initialize(NULL, reg, 604 phy_reg, 0); 605 606 } else { 607 debug("ZYNQ GEM: Can't get base address\n"); 608 return -1; 609 } 610 } 611 } while (offset != -1); 612 613 return ret; 614 } 615 #endif 616