1 /* 2 * (C) Copyright 2011 Michal Simek 3 * 4 * Michal SIMEK <monstr@monstr.eu> 5 * 6 * Based on Xilinx gmac driver: 7 * (C) Copyright 2011 Xilinx 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <net.h> 30 #include <config.h> 31 #include <malloc.h> 32 #include <asm/io.h> 33 #include <phy.h> 34 #include <miiphy.h> 35 #include <watchdog.h> 36 #include <asm/arch/hardware.h> 37 #include <asm/arch/sys_proto.h> 38 39 #if !defined(CONFIG_PHYLIB) 40 # error XILINX_GEM_ETHERNET requires PHYLIB 41 #endif 42 43 /* Bit/mask specification */ 44 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ 45 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ 46 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ 47 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ 48 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ 49 50 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ 51 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ 52 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ 53 54 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ 55 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ 56 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ 57 58 /* Wrap bit, last descriptor */ 59 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 60 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ 61 62 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ 63 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ 64 /* Transmit buffs exhausted mid frame */ 65 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 66 67 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ 68 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ 69 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ 70 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ 71 72 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ 73 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ 74 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ 75 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ 76 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ 77 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ 78 79 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ 80 ZYNQ_GEM_NWCFG_FSREM | \ 81 ZYNQ_GEM_NWCFG_MDCCLKDIV) 82 83 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ 84 85 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ 86 /* Use full configured addressable space (8 Kb) */ 87 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 88 /* Use full configured addressable space (4 Kb) */ 89 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 90 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ 91 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 92 93 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ 94 ZYNQ_GEM_DMACR_RXSIZE | \ 95 ZYNQ_GEM_DMACR_TXSIZE | \ 96 ZYNQ_GEM_DMACR_RXBUF) 97 98 /* Device registers */ 99 struct zynq_gem_regs { 100 u32 nwctrl; /* Network Control reg */ 101 u32 nwcfg; /* Network Config reg */ 102 u32 nwsr; /* Network Status reg */ 103 u32 reserved1; 104 u32 dmacr; /* DMA Control reg */ 105 u32 txsr; /* TX Status reg */ 106 u32 rxqbase; /* RX Q Base address reg */ 107 u32 txqbase; /* TX Q Base address reg */ 108 u32 rxsr; /* RX Status reg */ 109 u32 reserved2[2]; 110 u32 idr; /* Interrupt Disable reg */ 111 u32 reserved3; 112 u32 phymntnc; /* Phy Maintaince reg */ 113 u32 reserved4[18]; 114 u32 hashl; /* Hash Low address reg */ 115 u32 hashh; /* Hash High address reg */ 116 #define LADDR_LOW 0 117 #define LADDR_HIGH 1 118 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ 119 u32 match[4]; /* Type ID1 Match reg */ 120 u32 reserved6[18]; 121 u32 stat[44]; /* Octects transmitted Low reg - stat start */ 122 }; 123 124 /* BD descriptors */ 125 struct emac_bd { 126 u32 addr; /* Next descriptor pointer */ 127 u32 status; 128 }; 129 130 #define RX_BUF 3 131 132 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ 133 struct zynq_gem_priv { 134 struct emac_bd tx_bd; 135 struct emac_bd rx_bd[RX_BUF]; 136 char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; 137 u32 rxbd_current; 138 u32 rx_first_buf; 139 int phyaddr; 140 u32 emio; 141 int init; 142 struct phy_device *phydev; 143 struct mii_dev *bus; 144 }; 145 146 static inline int mdio_wait(struct eth_device *dev) 147 { 148 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 149 u32 timeout = 200; 150 151 /* Wait till MDIO interface is ready to accept a new transaction. */ 152 while (--timeout) { 153 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) 154 break; 155 WATCHDOG_RESET(); 156 } 157 158 if (!timeout) { 159 printf("%s: Timeout\n", __func__); 160 return 1; 161 } 162 163 return 0; 164 } 165 166 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, 167 u32 op, u16 *data) 168 { 169 u32 mgtcr; 170 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 171 172 if (mdio_wait(dev)) 173 return 1; 174 175 /* Construct mgtcr mask for the operation */ 176 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | 177 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | 178 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; 179 180 /* Write mgtcr and wait for completion */ 181 writel(mgtcr, ®s->phymntnc); 182 183 if (mdio_wait(dev)) 184 return 1; 185 186 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) 187 *data = readl(®s->phymntnc); 188 189 return 0; 190 } 191 192 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) 193 { 194 return phy_setup_op(dev, phy_addr, regnum, 195 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); 196 } 197 198 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) 199 { 200 return phy_setup_op(dev, phy_addr, regnum, 201 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); 202 } 203 204 static int zynq_gem_setup_mac(struct eth_device *dev) 205 { 206 u32 i, macaddrlow, macaddrhigh; 207 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 208 209 /* Set the MAC bits [31:0] in BOT */ 210 macaddrlow = dev->enetaddr[0]; 211 macaddrlow |= dev->enetaddr[1] << 8; 212 macaddrlow |= dev->enetaddr[2] << 16; 213 macaddrlow |= dev->enetaddr[3] << 24; 214 215 /* Set MAC bits [47:32] in TOP */ 216 macaddrhigh = dev->enetaddr[4]; 217 macaddrhigh |= dev->enetaddr[5] << 8; 218 219 for (i = 0; i < 4; i++) { 220 writel(0, ®s->laddr[i][LADDR_LOW]); 221 writel(0, ®s->laddr[i][LADDR_HIGH]); 222 /* Do not use MATCHx register */ 223 writel(0, ®s->match[i]); 224 } 225 226 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); 227 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); 228 229 return 0; 230 } 231 232 static int zynq_gem_init(struct eth_device *dev, bd_t * bis) 233 { 234 u32 i, rclk, clk = 0; 235 struct phy_device *phydev; 236 const u32 stat_size = (sizeof(struct zynq_gem_regs) - 237 offsetof(struct zynq_gem_regs, stat)) / 4; 238 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 239 struct zynq_gem_priv *priv = dev->priv; 240 const u32 supported = SUPPORTED_10baseT_Half | 241 SUPPORTED_10baseT_Full | 242 SUPPORTED_100baseT_Half | 243 SUPPORTED_100baseT_Full | 244 SUPPORTED_1000baseT_Half | 245 SUPPORTED_1000baseT_Full; 246 247 if (!priv->init) { 248 /* Disable all interrupts */ 249 writel(0xFFFFFFFF, ®s->idr); 250 251 /* Disable the receiver & transmitter */ 252 writel(0, ®s->nwctrl); 253 writel(0, ®s->txsr); 254 writel(0, ®s->rxsr); 255 writel(0, ®s->phymntnc); 256 257 /* Clear the Hash registers for the mac address 258 * pointed by AddressPtr 259 */ 260 writel(0x0, ®s->hashl); 261 /* Write bits [63:32] in TOP */ 262 writel(0x0, ®s->hashh); 263 264 /* Clear all counters */ 265 for (i = 0; i <= stat_size; i++) 266 readl(®s->stat[i]); 267 268 /* Setup RxBD space */ 269 memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); 270 /* Create the RxBD ring */ 271 memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); 272 273 for (i = 0; i < RX_BUF; i++) { 274 priv->rx_bd[i].status = 0xF0000000; 275 priv->rx_bd[i].addr = 276 (u32)((char *)&(priv->rxbuffers) + 277 (i * PKTSIZE_ALIGN)); 278 } 279 /* WRAP bit to last BD */ 280 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; 281 /* Write RxBDs to IP */ 282 writel((u32)&(priv->rx_bd), ®s->rxqbase); 283 284 /* Setup for DMA Configuration register */ 285 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); 286 287 /* Setup for Network Control register, MDIO, Rx and Tx enable */ 288 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); 289 290 priv->init++; 291 } 292 293 /* interface - look at tsec */ 294 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 295 296 phydev->supported = supported | ADVERTISED_Pause | 297 ADVERTISED_Asym_Pause; 298 phydev->advertising = phydev->supported; 299 priv->phydev = phydev; 300 phy_config(phydev); 301 phy_startup(phydev); 302 303 switch (phydev->speed) { 304 case SPEED_1000: 305 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, 306 ®s->nwcfg); 307 rclk = (0 << 4) | (1 << 0); 308 clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 309 break; 310 case SPEED_100: 311 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, 312 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); 313 rclk = 1 << 0; 314 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 315 break; 316 case SPEED_10: 317 rclk = 1 << 0; 318 /* FIXME untested */ 319 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); 320 break; 321 } 322 323 /* Change the rclk and clk only not using EMIO interface */ 324 if (!priv->emio) 325 zynq_slcr_gem_clk_setup(dev->iobase != 326 ZYNQ_GEM_BASEADDR0, rclk, clk); 327 328 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 329 ZYNQ_GEM_NWCTRL_TXEN_MASK); 330 331 return 0; 332 } 333 334 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) 335 { 336 u32 status; 337 struct zynq_gem_priv *priv = dev->priv; 338 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 339 const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ 340 ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; 341 342 /* setup BD */ 343 writel((u32)&(priv->tx_bd), ®s->txqbase); 344 345 /* Setup Tx BD */ 346 memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); 347 348 priv->tx_bd.addr = (u32)ptr; 349 priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; 350 351 /* Start transmit */ 352 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); 353 354 /* Read the stat register to know if the packet has been transmitted */ 355 status = readl(®s->txsr); 356 if (status & mask) 357 printf("Something has gone wrong here!? Status is 0x%x.\n", 358 status); 359 360 /* Clear Tx status register before leaving . */ 361 writel(status, ®s->txsr); 362 return 0; 363 } 364 365 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ 366 static int zynq_gem_recv(struct eth_device *dev) 367 { 368 int frame_len; 369 struct zynq_gem_priv *priv = dev->priv; 370 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; 371 struct emac_bd *first_bd; 372 373 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) 374 return 0; 375 376 if (!(current_bd->status & 377 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { 378 printf("GEM: SOF or EOF not set for last buffer received!\n"); 379 return 0; 380 } 381 382 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; 383 if (frame_len) { 384 NetReceive((u8 *) (current_bd->addr & 385 ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); 386 387 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) 388 priv->rx_first_buf = priv->rxbd_current; 389 else { 390 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 391 current_bd->status = 0xF0000000; /* FIXME */ 392 } 393 394 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { 395 first_bd = &priv->rx_bd[priv->rx_first_buf]; 396 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; 397 first_bd->status = 0xF0000000; 398 } 399 400 if ((++priv->rxbd_current) >= RX_BUF) 401 priv->rxbd_current = 0; 402 } 403 404 return frame_len; 405 } 406 407 static void zynq_gem_halt(struct eth_device *dev) 408 { 409 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; 410 411 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | 412 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); 413 } 414 415 static int zynq_gem_miiphyread(const char *devname, uchar addr, 416 uchar reg, ushort *val) 417 { 418 struct eth_device *dev = eth_get_dev(); 419 int ret; 420 421 ret = phyread(dev, addr, reg, val); 422 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); 423 return ret; 424 } 425 426 static int zynq_gem_miiphy_write(const char *devname, uchar addr, 427 uchar reg, ushort val) 428 { 429 struct eth_device *dev = eth_get_dev(); 430 431 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); 432 return phywrite(dev, addr, reg, val); 433 } 434 435 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) 436 { 437 struct eth_device *dev; 438 struct zynq_gem_priv *priv; 439 440 dev = calloc(1, sizeof(*dev)); 441 if (dev == NULL) 442 return -1; 443 444 dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); 445 if (dev->priv == NULL) { 446 free(dev); 447 return -1; 448 } 449 priv = dev->priv; 450 451 priv->phyaddr = phy_addr; 452 priv->emio = emio; 453 454 sprintf(dev->name, "Gem.%x", base_addr); 455 456 dev->iobase = base_addr; 457 458 dev->init = zynq_gem_init; 459 dev->halt = zynq_gem_halt; 460 dev->send = zynq_gem_send; 461 dev->recv = zynq_gem_recv; 462 dev->write_hwaddr = zynq_gem_setup_mac; 463 464 eth_register(dev); 465 466 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); 467 priv->bus = miiphy_get_dev_by_name(dev->name); 468 469 return 1; 470 } 471