1 /* 2 * Xilinx xps_ll_temac ethernet driver for u-boot 3 * 4 * LL_TEMAC interface 5 * 6 * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net> 7 * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu> 8 * Copyright (C) 2008 - 2011 PetaLogix 9 * 10 * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver 11 * Copyright (C) 2008 Nissin Systems Co.,Ltd. 12 * March 2008 created 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 * [0]: http://www.xilinx.com/support/documentation 20 * 21 * [S]: [0]/ip_documentation/xps_ll_temac.pdf 22 * [A]: [0]/application_notes/xapp1041.pdf 23 */ 24 #ifndef _XILINX_LL_TEMAC_ 25 #define _XILINX_LL_TEMAC_ 26 27 #include <config.h> 28 #include <net.h> 29 #include <phy.h> 30 #include <miiphy.h> 31 32 #include <asm/types.h> 33 #include <asm/byteorder.h> 34 35 #include "xilinx_ll_temac_sdma.h" 36 37 #if !defined(__BIG_ENDIAN) 38 # error LL_TEMAC requires big endianess 39 #endif 40 41 /* 42 * TEMAC Memory and Register Definition 43 * 44 * [1]: [0]/ip_documentation/xps_ll_temac.pdf 45 * page 19, Memory and Register Descriptions 46 */ 47 struct temac_reg { 48 /* direct soft registers (low part) */ 49 u32 raf; /* Reset and Address Filter */ 50 u32 tpf; /* Transmit Pause Frame */ 51 u32 ifgp; /* Transmit Inter Frame Gap Adjustment */ 52 u32 is; /* Interrupt Status */ 53 u32 ip; /* Interrupt Pending */ 54 u32 ie; /* Interrupt Enable */ 55 u32 ttag; /* Transmit VLAN Tag */ 56 u32 rtag; /* Receive VLAN Tag */ 57 /* hard TEMAC registers */ 58 u32 msw; /* Most Significant Word Data */ 59 u32 lsw; /* Least Significant Word Data */ 60 u32 ctl; /* Control */ 61 u32 rdy; /* Ready Status */ 62 /* direct soft registers (high part) */ 63 u32 uawl; /* Unicast Address Word Lower */ 64 u32 uawu; /* Unicast Address Word Upper */ 65 u32 tpid0; /* VLAN TPID Word 0 */ 66 u32 tpid1; /* VLAN TPID Word 1 */ 67 }; 68 69 /* Reset and Address Filter Registers (raf), [1] p25 */ 70 #define RAF_SR (1 << 13) 71 #define RAF_EMFE (1 << 12) 72 #define RAF_NFE (1 << 11) 73 #define RAF_RVSTM_POS 9 74 #define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS) 75 #define RAF_TVSTM_POS 7 76 #define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS) 77 #define RAF_RVTM_POS 5 78 #define RAF_RVTM_MASK (3 << RAF_RVTM_POS) 79 #define RAF_TVTM_POS 3 80 #define RAF_TVTM_MASK (3 << RAF_TVTM_POS) 81 #define RAF_BCREJ (1 << 2) 82 #define RAF_MCREJ (1 << 1) 83 #define RAF_HTRST (1 << 0) 84 85 /* Transmit Pause Frame Registers (tpf), [1] p28 */ 86 #define TPF_TPFV_POS 0 87 #define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS) 88 89 /* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */ 90 #define IFGP_POS 0 91 #define IFGP_MASK (0xFF << IFGP_POS) 92 93 /* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */ 94 #define ISPE_MR (1 << 7) 95 #define ISPE_RDL (1 << 6) 96 #define ISPE_TC (1 << 5) 97 #define ISPE_RFO (1 << 4) 98 #define ISPE_RR (1 << 3) 99 #define ISPE_RC (1 << 2) 100 #define ISPE_AN (1 << 1) 101 #define ISPE_HAC (1 << 0) 102 103 /* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */ 104 #define TRTAG_TPID_POS 16 105 #define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS) 106 #define TRTAG_PRIO_POS 13 107 #define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS) 108 #define TRTAG_CFI (1 << 12) 109 #define TRTAG_VID_POS 0 110 #define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS) 111 112 /* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */ 113 #define MLSW_POS 0 114 #define MLSW_MASK (~0UL << MLSW_POS) 115 116 /* LSW Data Register for PHY addresses (lsw), [1] p66 */ 117 #define LSW_REGAD_POS 0 118 #define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS) 119 #define LSW_PHYAD_POS 5 120 #define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS) 121 122 /* LSW Data Register for PHY data (lsw), [1] p66 */ 123 #define LSW_REGDAT_POS 0 124 #define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS) 125 126 /* Control Register (ctl), [1] p47 */ 127 #define CTL_WEN (1 << 15) 128 #define CTL_ADDR_POS 0 129 #define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS) 130 131 /* Ready Status Register Ethernet (rdy), [1] p48 */ 132 #define RSE_HACS_RDY (1 << 14) 133 #define RSE_CFG_WR (1 << 6) 134 #define RSE_CFG_RR (1 << 5) 135 #define RSE_AF_WR (1 << 4) 136 #define RSE_AF_RR (1 << 3) 137 #define RSE_MIIM_WR (1 << 2) 138 #define RSE_MIIM_RR (1 << 1) 139 #define RSE_FABR_RR (1 << 0) 140 141 /* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */ 142 #define UAWL_UADDR_POS 0 143 #define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS) 144 #define UAWU_UADDR_POS 0 145 #define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS) 146 147 /* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */ 148 #define TPID0_V0_POS 0 149 #define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS) 150 #define TPID0_V1_POS 16 151 #define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS) 152 #define TPID1_V2_POS 0 153 #define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS) 154 #define TPID1_V3_POS 16 155 #define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS) 156 157 /* 158 * TEMAC Indirectly Addressable Register Index Enumeration 159 * 160 * [0]: http://www.xilinx.com/support/documentation 161 * 162 * [1]: [0]/ip_documentation/xps_ll_temac.pdf 163 * page 23, PLB Indirectly Addressable TEMAC Registers 164 */ 165 enum temac_ctrl { 166 TEMAC_RCW0 = 0x200, 167 TEMAC_RCW1 = 0x240, 168 TEMAC_TC = 0x280, 169 TEMAC_FCC = 0x2C0, 170 TEMAC_EMMC = 0x300, 171 TEMAC_PHYC = 0x320, 172 TEMAC_MC = 0x340, 173 TEMAC_UAW0 = 0x380, 174 TEMAC_UAW1 = 0x384, 175 TEMAC_MAW0 = 0x388, 176 TEMAC_MAW1 = 0x38C, 177 TEMAC_AFM = 0x390, 178 TEMAC_TIS = 0x3A0, 179 TEMAC_TIE = 0x3A4, 180 TEMAC_MIIMWD = 0x3B0, 181 TEMAC_MIIMAI = 0x3B4 182 }; 183 184 /* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */ 185 #define RCW0_PADDR_POS 0 186 #define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS) 187 #define RCW1_RST (1 << 31) 188 #define RCW1_JUM (1 << 30) 189 #define RCW1_FCS (1 << 29) 190 #define RCW1_RX (1 << 28) 191 #define RCW1_VLAN (1 << 27) 192 #define RCW1_HD (1 << 26) 193 #define RCW1_LT_DIS (1 << 25) 194 #define RCW1_PADDR_POS 0 195 #define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS) 196 197 /* Transmit Configuration Registers (TC), [1] p52 */ 198 #define TC_RST (1 << 31) 199 #define TC_JUM (1 << 30) 200 #define TC_FCS (1 << 29) 201 #define TC_TX (1 << 28) 202 #define TC_VLAN (1 << 27) 203 #define TC_HD (1 << 26) 204 #define TC_IFG (1 << 25) 205 206 /* Flow Control Configuration Registers (FCC), [1] p54 */ 207 #define FCC_FCTX (1 << 30) 208 #define FCC_FCRX (1 << 29) 209 210 /* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */ 211 #define EMMC_LSPD_POS 30 212 #define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS) 213 #define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS) 214 #define EMMC_LSPD_100 (1 << EMMC_LSPD_POS) 215 #define EMMC_LSPD_10 0 216 #define EMMC_RGMII (1 << 29) 217 #define EMMC_SGMII (1 << 28) 218 #define EMMC_GPCS (1 << 27) 219 #define EMMC_HOST (1 << 26) 220 #define EMMC_TX16 (1 << 25) 221 #define EMMC_RX16 (1 << 24) 222 223 /* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */ 224 #define PHYC_SLSPD_POS 30 225 #define PHYC_SLSPD_MASK (3 << EMMC_SLSPD_POS) 226 #define PHYC_SLSPD_1000 (2 << EMMC_SLSPD_POS) 227 #define PHYC_SLSPD_100 (1 << EMMC_SLSPD_POS) 228 #define PHYC_SLSPD_10 0 229 #define PHYC_RLSPD_POS 2 230 #define PHYC_RLSPD_MASK (3 << EMMC_RLSPD_POS) 231 #define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS) 232 #define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS) 233 #define PHYC_RLSPD_10 0 234 #define PHYC_RGMII_HD (1 << 1) 235 #define PHYC_RGMII_LINK (1 << 0) 236 237 /* Management Configuration Registers (MC), [1] p57 */ 238 #define MC_MDIOEN (1 << 6) 239 #define MC_CLKDIV_POS 0 240 #define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS) 241 242 /* 243 * fHOSTCLK fMDC = fHOSTCLK 244 * fMDC = ------------------- ---------> MC_CLKDIV = -------- - 1 245 * (1 + MC_CLKDIV) * 2 2.5 MHz 5MHz 246 */ 247 #define MC_CLKDIV(f, m) ((f / (2 * m)) - 1) 248 #define MC_CLKDIV_25(f) MC_CLKDIV(f, 2500000) 249 #define MC_CLKDIV_20(f) MC_CLKDIV(f, 2000000) 250 #define MC_CLKDIV_15(f) MC_CLKDIV(f, 1500000) 251 #define MC_CLKDIV_10(f) MC_CLKDIV(f, 1000000) 252 253 /* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */ 254 #define UAW0_UADDR_POS 0 255 #define UAW0_UADDR_MASK (~0UL << UAW0_UADDR_POS) 256 #define UAW1_UADDR_POS 0 257 #define UAW1_UADDR_MASK (0xFFFF << UAW1_UADDR_POS) 258 259 /* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */ 260 #define MAW0_MADDR_POS 0 261 #define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS) 262 #define MAW1_RNW (1 << 23) 263 #define MAW1_MAIDX_POS 16 264 #define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS) 265 #define MAW1_MADDR_POS 0 266 #define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS) 267 268 /* Address Filter Mode Registers (AFM), [1] p63 */ 269 #define AFM_PM (1 << 31) 270 271 /* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */ 272 #define TISE_CFG_W (1 << 6) 273 #define TISE_CFG_R (1 << 5) 274 #define TISE_AF_W (1 << 4) 275 #define TISE_AF_R (1 << 3) 276 #define TISE_MIIM_W (1 << 2) 277 #define TISE_MIIM_R (1 << 1) 278 #define TISE_FABR_R (1 << 0) 279 280 /* MII Management Write Data Registers (MIIMWD), [1] p66 */ 281 #define MIIMWD_DATA_POS 0 282 #define MIIMWD_DATA_MASK (0xFFFF << MIIMWD_DATA_POS) 283 284 /* Ethernet interface ready status */ 285 int ll_temac_check_status(struct temac_reg *regs, u32 mask); 286 287 /* Indirect write to ll_temac. */ 288 int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data); 289 290 /* Indirect read from ll_temac. */ 291 int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data); 292 293 struct ll_temac { 294 phys_addr_t ctrladdr; 295 phys_addr_t sdma_reg_addr[SDMA_CTRL_REGNUMS]; 296 297 unsigned (*in32)(phys_addr_t); 298 void (*out32)(phys_addr_t, unsigned); 299 300 int (*ctrlinit) (struct eth_device *); 301 int (*ctrlhalt) (struct eth_device *); 302 int (*ctrlreset) (struct eth_device *); 303 304 int phyaddr; 305 struct phy_device *phydev; 306 struct mii_dev *bus; 307 char mdio_busname[MDIO_NAME_LEN]; 308 }; 309 310 #endif /* _XILINX_LL_TEMAC_ */ 311