1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <net.h> 28 #include <config.h> 29 #include <malloc.h> 30 #include <asm/io.h> 31 32 #undef DEBUG 33 34 #define ENET_MAX_MTU PKTSIZE 35 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN 36 #define ENET_ADDR_LENGTH 6 37 38 /* EmacLite constants */ 39 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ 40 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 41 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 42 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 43 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 44 45 /* Xmit complete */ 46 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 47 /* Xmit interrupt enable bit */ 48 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 49 /* Buffer is active, SW bit only */ 50 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL 51 /* Program the MAC address */ 52 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 53 /* define for programming the MAC address into the EMAC Lite */ 54 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 55 56 /* Transmit packet length upper byte */ 57 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 58 /* Transmit packet length lower byte */ 59 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 60 61 /* Recv complete */ 62 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 63 /* Recv interrupt enable bit */ 64 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 65 66 typedef struct { 67 u32 nexttxbuffertouse; /* Next TX buffer to write to */ 68 u32 nextrxbuffertouse; /* Next RX buffer to read from */ 69 } xemaclite; 70 71 static xemaclite emaclite; 72 73 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ 74 75 static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount) 76 { 77 u32 i; 78 u32 alignbuffer; 79 u32 *to32ptr; 80 u32 *from32ptr; 81 u8 *to8ptr; 82 u8 *from8ptr; 83 84 from32ptr = (u32 *) srcptr; 85 86 /* Word aligned buffer, no correction needed. */ 87 to32ptr = (u32 *) destptr; 88 while (bytecount > 3) { 89 *to32ptr++ = *from32ptr++; 90 bytecount -= 4; 91 } 92 to8ptr = (u8 *) to32ptr; 93 94 alignbuffer = *from32ptr++; 95 from8ptr = (u8 *) & alignbuffer; 96 97 for (i = 0; i < bytecount; i++) { 98 *to8ptr++ = *from8ptr++; 99 } 100 } 101 102 static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount) 103 { 104 u32 i; 105 u32 alignbuffer; 106 u32 *to32ptr = (u32 *) destptr; 107 u32 *from32ptr; 108 u8 *to8ptr; 109 u8 *from8ptr; 110 111 from32ptr = (u32 *) srcptr; 112 while (bytecount > 3) { 113 114 *to32ptr++ = *from32ptr++; 115 bytecount -= 4; 116 } 117 118 alignbuffer = 0; 119 to8ptr = (u8 *) & alignbuffer; 120 from8ptr = (u8 *) from32ptr; 121 122 for (i = 0; i < bytecount; i++) { 123 *to8ptr++ = *from8ptr++; 124 } 125 126 *to32ptr++ = alignbuffer; 127 } 128 129 static void emaclite_halt(struct eth_device *dev) 130 { 131 debug ("eth_halt\n"); 132 } 133 134 static int emaclite_init(struct eth_device *dev, bd_t *bis) 135 { 136 debug ("EmacLite Initialization Started\n"); 137 memset (&emaclite, 0, sizeof (xemaclite)); 138 139 /* 140 * TX - TX_PING & TX_PONG initialization 141 */ 142 /* Restart PING TX */ 143 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); 144 /* Copy MAC address */ 145 xemaclite_alignedwrite (dev->enetaddr, 146 dev->iobase, ENET_ADDR_LENGTH); 147 /* Set the length */ 148 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); 149 /* Update the MAC address in the EMAC Lite */ 150 out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); 151 /* Wait for EMAC Lite to finish with the MAC address update */ 152 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & 153 XEL_TSR_PROG_MAC_ADDR) != 0) 154 ; 155 156 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 157 /* The same operation with PONG TX */ 158 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); 159 xemaclite_alignedwrite(dev->enetaddr, dev->iobase + 160 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); 161 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); 162 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 163 XEL_TSR_PROG_MAC_ADDR); 164 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + 165 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) 166 ; 167 #endif 168 169 /* 170 * RX - RX_PING & RX_PONG initialization 171 */ 172 /* Write out the value to flush the RX buffer */ 173 out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); 174 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 175 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, 176 XEL_RSR_RECV_IE_MASK); 177 #endif 178 179 debug ("EmacLite Initialization complete\n"); 180 return 0; 181 } 182 183 static int xemaclite_txbufferavailable (xemaclite *instanceptr) 184 { 185 u32 reg; 186 u32 txpingbusy; 187 u32 txpongbusy; 188 /* 189 * Read the other buffer register 190 * and determine if the other buffer is available 191 */ 192 reg = in_be32 (instanceptr->baseaddress + 193 instanceptr->nexttxbuffertouse + 0); 194 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == 195 XEL_TSR_XMIT_BUSY_MASK); 196 197 reg = in_be32 (instanceptr->baseaddress + 198 (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); 199 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == 200 XEL_TSR_XMIT_BUSY_MASK); 201 202 return (!(txpingbusy && txpongbusy)); 203 } 204 205 static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len) 206 { 207 u32 reg; 208 u32 baseaddress; 209 210 u32 maxtry = 1000; 211 212 if (len > ENET_MAX_MTU) 213 len = ENET_MAX_MTU; 214 215 while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { 216 udelay (10); 217 maxtry--; 218 } 219 220 if (!maxtry) { 221 printf ("Error: Timeout waiting for ethernet TX buffer\n"); 222 /* Restart PING TX */ 223 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); 224 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 225 out_be32 (dev->iobase + XEL_TSR_OFFSET + 226 XEL_BUFFER_OFFSET, 0); 227 #endif 228 return -1; 229 } 230 231 /* Determine the expected TX buffer address */ 232 baseaddress = (dev->iobase + emaclite.nexttxbuffertouse); 233 234 /* Determine if the expected buffer address is empty */ 235 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 236 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) 237 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) 238 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { 239 240 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 241 emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; 242 #endif 243 debug ("Send packet from 0x%x\n", baseaddress); 244 /* Write the frame to the buffer */ 245 xemaclite_alignedwrite ((void *) ptr, baseaddress, len); 246 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & 247 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); 248 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 249 reg |= XEL_TSR_XMIT_BUSY_MASK; 250 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { 251 reg |= XEL_TSR_XMIT_ACTIVE_MASK; 252 } 253 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 254 return 0; 255 } 256 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 257 /* Switch to second buffer */ 258 baseaddress ^= XEL_BUFFER_OFFSET; 259 /* Determine if the expected buffer address is empty */ 260 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 261 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) 262 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) 263 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { 264 debug("Send packet from 0x%x\n", baseaddress); 265 /* Write the frame to the buffer */ 266 xemaclite_alignedwrite ((void *) ptr, baseaddress, len); 267 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & 268 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); 269 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 270 reg |= XEL_TSR_XMIT_BUSY_MASK; 271 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { 272 reg |= XEL_TSR_XMIT_ACTIVE_MASK; 273 } 274 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 275 return 0; 276 } 277 #endif 278 puts ("Error while sending frame\n"); 279 return -1; 280 } 281 282 static int emaclite_recv(struct eth_device *dev) 283 { 284 u32 length; 285 u32 reg; 286 u32 baseaddress; 287 288 baseaddress = dev->iobase + emaclite.nextrxbuffertouse; 289 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 290 debug ("Testing data at address 0x%x\n", baseaddress); 291 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 292 #ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 293 emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; 294 #endif 295 } else { 296 #ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG 297 debug ("No data was available - address 0x%x\n", baseaddress); 298 return 0; 299 #else 300 baseaddress ^= XEL_BUFFER_OFFSET; 301 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 302 if ((reg & XEL_RSR_RECV_DONE_MASK) != 303 XEL_RSR_RECV_DONE_MASK) { 304 debug ("No data was available - address 0x%x\n", 305 baseaddress); 306 return 0; 307 } 308 #endif 309 } 310 /* Get the length of the frame that arrived */ 311 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & 312 0xFFFF0000 ) >> 16) { 313 case 0x806: 314 length = 42 + 20; /* FIXME size of ARP */ 315 debug ("ARP Packet\n"); 316 break; 317 case 0x800: 318 length = 14 + 14 + 319 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) & 320 0xFFFF0000) >> 16); /* FIXME size of IP packet */ 321 debug ("IP Packet\n"); 322 break; 323 default: 324 debug ("Other Packet\n"); 325 length = ENET_MAX_MTU; 326 break; 327 } 328 329 xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), 330 etherrxbuff, length); 331 332 /* Acknowledge the frame */ 333 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 334 reg &= ~XEL_RSR_RECV_DONE_MASK; 335 out_be32 (baseaddress + XEL_RSR_OFFSET, reg); 336 337 debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length); 338 NetReceive ((uchar *) etherrxbuff, length); 339 return length; 340 341 } 342 343 int xilinx_emaclite_initialize (bd_t *bis, int base_addr) 344 { 345 struct eth_device *dev; 346 347 dev = calloc(1, sizeof(*dev)); 348 if (dev == NULL) 349 return -1; 350 351 sprintf(dev->name, "Xelite.%x", base_addr); 352 353 dev->iobase = base_addr; 354 dev->priv = 0; 355 dev->init = emaclite_init; 356 dev->halt = emaclite_halt; 357 dev->send = emaclite_send; 358 dev->recv = emaclite_recv; 359 360 eth_register(dev); 361 362 return 1; 363 } 364