1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <config.h> 13 #include <console.h> 14 #include <malloc.h> 15 #include <asm/io.h> 16 #include <phy.h> 17 #include <miiphy.h> 18 #include <fdtdec.h> 19 #include <asm-generic/errno.h> 20 #include <linux/kernel.h> 21 22 #undef DEBUG 23 24 #define ENET_ADDR_LENGTH 6 25 #define ETH_FCS_LEN 4 /* Octets in the FCS */ 26 27 /* Xmit complete */ 28 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 29 /* Xmit interrupt enable bit */ 30 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 31 /* Program the MAC address */ 32 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 33 /* define for programming the MAC address into the EMAC Lite */ 34 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 35 36 /* Transmit packet length upper byte */ 37 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 38 /* Transmit packet length lower byte */ 39 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 40 41 /* Recv complete */ 42 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 43 /* Recv interrupt enable bit */ 44 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 45 46 /* MDIO Address Register Bit Masks */ 47 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 48 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 49 #define XEL_MDIOADDR_PHYADR_SHIFT 5 50 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 51 52 /* MDIO Write Data Register Bit Masks */ 53 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 54 55 /* MDIO Read Data Register Bit Masks */ 56 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 57 58 /* MDIO Control Register Bit Masks */ 59 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 60 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 61 62 struct emaclite_regs { 63 u32 tx_ping; /* 0x0 - TX Ping buffer */ 64 u32 reserved1[504]; 65 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ 66 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ 67 u32 mdiord;/* 0x7ec - MDIO Read Data Register */ 68 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ 69 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ 70 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ 71 u32 tx_ping_tsr; /* 0x7fc - Tx status */ 72 u32 tx_pong; /* 0x800 - TX Pong buffer */ 73 u32 reserved2[508]; 74 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ 75 u32 reserved3; /* 0xff8 */ 76 u32 tx_pong_tsr; /* 0xffc - Tx status */ 77 u32 rx_ping; /* 0x1000 - Receive Buffer */ 78 u32 reserved4[510]; 79 u32 rx_ping_rsr; /* 0x17fc - Rx status */ 80 u32 rx_pong; /* 0x1800 - Receive Buffer */ 81 u32 reserved5[510]; 82 u32 rx_pong_rsr; /* 0x1ffc - Rx status */ 83 }; 84 85 struct xemaclite { 86 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ 87 u32 txpp; /* TX ping pong buffer */ 88 u32 rxpp; /* RX ping pong buffer */ 89 int phyaddr; 90 struct emaclite_regs *regs; 91 struct phy_device *phydev; 92 struct mii_dev *bus; 93 }; 94 95 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ 96 97 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) 98 { 99 u32 i; 100 u32 alignbuffer; 101 u32 *to32ptr; 102 u32 *from32ptr; 103 u8 *to8ptr; 104 u8 *from8ptr; 105 106 from32ptr = (u32 *) srcptr; 107 108 /* Word aligned buffer, no correction needed. */ 109 to32ptr = (u32 *) destptr; 110 while (bytecount > 3) { 111 *to32ptr++ = *from32ptr++; 112 bytecount -= 4; 113 } 114 to8ptr = (u8 *) to32ptr; 115 116 alignbuffer = *from32ptr++; 117 from8ptr = (u8 *) &alignbuffer; 118 119 for (i = 0; i < bytecount; i++) 120 *to8ptr++ = *from8ptr++; 121 } 122 123 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) 124 { 125 u32 i; 126 u32 alignbuffer; 127 u32 *to32ptr = (u32 *) destptr; 128 u32 *from32ptr; 129 u8 *to8ptr; 130 u8 *from8ptr; 131 132 from32ptr = (u32 *) srcptr; 133 while (bytecount > 3) { 134 135 *to32ptr++ = *from32ptr++; 136 bytecount -= 4; 137 } 138 139 alignbuffer = 0; 140 to8ptr = (u8 *) &alignbuffer; 141 from8ptr = (u8 *) from32ptr; 142 143 for (i = 0; i < bytecount; i++) 144 *to8ptr++ = *from8ptr++; 145 146 *to32ptr++ = alignbuffer; 147 } 148 149 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 151 bool set, unsigned int timeout) 152 { 153 u32 val; 154 unsigned long start = get_timer(0); 155 156 while (1) { 157 val = readl(reg); 158 159 if (!set) 160 val = ~val; 161 162 if ((val & mask) == mask) 163 return 0; 164 165 if (get_timer(start) > timeout) 166 break; 167 168 if (ctrlc()) { 169 puts("Abort\n"); 170 return -EINTR; 171 } 172 173 udelay(1); 174 } 175 176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 177 func, reg, mask, set); 178 179 return -ETIMEDOUT; 180 } 181 182 static int mdio_wait(struct emaclite_regs *regs) 183 { 184 return wait_for_bit(__func__, ®s->mdioctrl, 185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); 186 } 187 188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 189 u16 *data) 190 { 191 struct emaclite_regs *regs = emaclite->regs; 192 193 if (mdio_wait(regs)) 194 return 1; 195 196 u32 ctrl_reg = in_be32(®s->mdioctrl); 197 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | 198 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 199 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 200 201 if (mdio_wait(regs)) 202 return 1; 203 204 /* Read data */ 205 *data = in_be32(®s->mdiord); 206 return 0; 207 } 208 209 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 210 u16 data) 211 { 212 struct emaclite_regs *regs = emaclite->regs; 213 214 if (mdio_wait(regs)) 215 return 1; 216 217 /* 218 * Write the PHY address, register number and clear the OP bit in the 219 * MDIO Address register and then write the value into the MDIO Write 220 * Data register. Finally, set the Status bit in the MDIO Control 221 * register to start a MDIO write transaction. 222 */ 223 u32 ctrl_reg = in_be32(®s->mdioctrl); 224 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & 225 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 226 out_be32(®s->mdiowr, data); 227 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 228 229 if (mdio_wait(regs)) 230 return 1; 231 232 return 0; 233 } 234 #endif 235 236 static void emaclite_halt(struct eth_device *dev) 237 { 238 debug("eth_halt\n"); 239 } 240 241 /* Use MII register 1 (MII status register) to detect PHY */ 242 #define PHY_DETECT_REG 1 243 244 /* Mask used to verify certain PHY features (or register contents) 245 * in the register above: 246 * 0x1000: 10Mbps full duplex support 247 * 0x0800: 10Mbps half duplex support 248 * 0x0008: Auto-negotiation support 249 */ 250 #define PHY_DETECT_MASK 0x1808 251 252 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 253 static int setup_phy(struct eth_device *dev) 254 { 255 int i; 256 u16 phyreg; 257 struct xemaclite *emaclite = dev->priv; 258 struct phy_device *phydev; 259 260 u32 supported = SUPPORTED_10baseT_Half | 261 SUPPORTED_10baseT_Full | 262 SUPPORTED_100baseT_Half | 263 SUPPORTED_100baseT_Full; 264 265 if (emaclite->phyaddr != -1) { 266 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); 267 if ((phyreg != 0xFFFF) && 268 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 269 /* Found a valid PHY address */ 270 debug("Default phy address %d is valid\n", 271 emaclite->phyaddr); 272 } else { 273 debug("PHY address is not setup correctly %d\n", 274 emaclite->phyaddr); 275 emaclite->phyaddr = -1; 276 } 277 } 278 279 if (emaclite->phyaddr == -1) { 280 /* detect the PHY address */ 281 for (i = 31; i >= 0; i--) { 282 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); 283 if ((phyreg != 0xFFFF) && 284 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 285 /* Found a valid PHY address */ 286 emaclite->phyaddr = i; 287 debug("emaclite: Found valid phy address, %d\n", 288 i); 289 break; 290 } 291 } 292 } 293 294 /* interface - look at tsec */ 295 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, 296 PHY_INTERFACE_MODE_MII); 297 /* 298 * Phy can support 1000baseT but device NOT that's why phydev->supported 299 * must be setup for 1000baseT. phydev->advertising setups what speeds 300 * will be used for autonegotiation where 1000baseT must be disabled. 301 */ 302 phydev->supported = supported | SUPPORTED_1000baseT_Half | 303 SUPPORTED_1000baseT_Full; 304 phydev->advertising = supported; 305 emaclite->phydev = phydev; 306 phy_config(phydev); 307 phy_startup(phydev); 308 309 if (!phydev->link) { 310 printf("%s: No link.\n", phydev->dev->name); 311 return 0; 312 } 313 314 /* Do not setup anything */ 315 return 1; 316 } 317 #endif 318 319 static int emaclite_init(struct eth_device *dev, bd_t *bis) 320 { 321 struct xemaclite *emaclite = dev->priv; 322 struct emaclite_regs *regs = emaclite->regs; 323 324 debug("EmacLite Initialization Started\n"); 325 326 /* 327 * TX - TX_PING & TX_PONG initialization 328 */ 329 /* Restart PING TX */ 330 out_be32(®s->tx_ping_tsr, 0); 331 /* Copy MAC address */ 332 xemaclite_alignedwrite(dev->enetaddr, ®s->tx_ping, 333 ENET_ADDR_LENGTH); 334 /* Set the length */ 335 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); 336 /* Update the MAC address in the EMAC Lite */ 337 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); 338 /* Wait for EMAC Lite to finish with the MAC address update */ 339 while ((in_be32 (®s->tx_ping_tsr) & 340 XEL_TSR_PROG_MAC_ADDR) != 0) 341 ; 342 343 if (emaclite->txpp) { 344 /* The same operation with PONG TX */ 345 out_be32(®s->tx_pong_tsr, 0); 346 xemaclite_alignedwrite(dev->enetaddr, ®s->tx_pong, 347 ENET_ADDR_LENGTH); 348 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); 349 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); 350 while ((in_be32(®s->tx_pong_tsr) & 351 XEL_TSR_PROG_MAC_ADDR) != 0) 352 ; 353 } 354 355 /* 356 * RX - RX_PING & RX_PONG initialization 357 */ 358 /* Write out the value to flush the RX buffer */ 359 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); 360 361 if (emaclite->rxpp) 362 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); 363 364 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 365 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 366 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) 367 if (!setup_phy(dev)) 368 return -1; 369 #endif 370 debug("EmacLite Initialization complete\n"); 371 return 0; 372 } 373 374 static int xemaclite_txbufferavailable(struct xemaclite *emaclite) 375 { 376 u32 tmp; 377 struct emaclite_regs *regs = emaclite->regs; 378 379 /* 380 * Read the other buffer register 381 * and determine if the other buffer is available 382 */ 383 tmp = ~in_be32(®s->tx_ping_tsr); 384 if (emaclite->txpp) 385 tmp |= ~in_be32(®s->tx_pong_tsr); 386 387 return !(tmp & XEL_TSR_XMIT_BUSY_MASK); 388 } 389 390 static int emaclite_send(struct eth_device *dev, void *ptr, int len) 391 { 392 u32 reg; 393 struct xemaclite *emaclite = dev->priv; 394 struct emaclite_regs *regs = emaclite->regs; 395 396 u32 maxtry = 1000; 397 398 if (len > PKTSIZE) 399 len = PKTSIZE; 400 401 while (xemaclite_txbufferavailable(emaclite) && maxtry) { 402 udelay(10); 403 maxtry--; 404 } 405 406 if (!maxtry) { 407 printf("Error: Timeout waiting for ethernet TX buffer\n"); 408 /* Restart PING TX */ 409 out_be32(®s->tx_ping_tsr, 0); 410 if (emaclite->txpp) { 411 out_be32(®s->tx_pong_tsr, 0); 412 } 413 return -1; 414 } 415 416 /* Determine if the expected buffer address is empty */ 417 reg = in_be32(®s->tx_ping_tsr); 418 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 419 debug("Send packet from tx_ping buffer\n"); 420 /* Write the frame to the buffer */ 421 xemaclite_alignedwrite(ptr, ®s->tx_ping, len); 422 out_be32(®s->tx_ping_tplr, len & 423 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); 424 reg = in_be32(®s->tx_ping_tsr); 425 reg |= XEL_TSR_XMIT_BUSY_MASK; 426 out_be32(®s->tx_ping_tsr, reg); 427 return 0; 428 } 429 430 if (emaclite->txpp) { 431 /* Determine if the expected buffer address is empty */ 432 reg = in_be32(®s->tx_pong_tsr); 433 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 434 debug("Send packet from tx_pong buffer\n"); 435 /* Write the frame to the buffer */ 436 xemaclite_alignedwrite(ptr, ®s->tx_pong, len); 437 out_be32(®s->tx_pong_tplr, len & 438 (XEL_TPLR_LENGTH_MASK_HI | 439 XEL_TPLR_LENGTH_MASK_LO)); 440 reg = in_be32(®s->tx_pong_tsr); 441 reg |= XEL_TSR_XMIT_BUSY_MASK; 442 out_be32(®s->tx_pong_tsr, reg); 443 return 0; 444 } 445 } 446 447 puts("Error while sending frame\n"); 448 return -1; 449 } 450 451 static int emaclite_recv(struct eth_device *dev) 452 { 453 u32 length, first_read, reg, attempt = 0; 454 void *addr, *ack; 455 struct xemaclite *emaclite = dev->priv; 456 struct emaclite_regs *regs = emaclite->regs; 457 struct ethernet_hdr *eth; 458 struct ip_udp_hdr *ip; 459 460 try_again: 461 if (!emaclite->use_rx_pong_buffer_next) { 462 reg = in_be32(®s->rx_ping_rsr); 463 debug("Testing data at rx_ping\n"); 464 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 465 debug("Data found in rx_ping buffer\n"); 466 addr = ®s->rx_ping; 467 ack = ®s->rx_ping_rsr; 468 } else { 469 debug("Data not found in rx_ping buffer\n"); 470 /* Pong buffer is not available - return immediately */ 471 if (!emaclite->rxpp) 472 return -1; 473 474 /* Try pong buffer if this is first attempt */ 475 if (attempt++) 476 return -1; 477 emaclite->use_rx_pong_buffer_next = 478 !emaclite->use_rx_pong_buffer_next; 479 goto try_again; 480 } 481 } else { 482 reg = in_be32(®s->rx_pong_rsr); 483 debug("Testing data at rx_pong\n"); 484 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 485 debug("Data found in rx_pong buffer\n"); 486 addr = ®s->rx_pong; 487 ack = ®s->rx_pong_rsr; 488 } else { 489 debug("Data not found in rx_pong buffer\n"); 490 /* Try ping buffer if this is first attempt */ 491 if (attempt++) 492 return -1; 493 emaclite->use_rx_pong_buffer_next = 494 !emaclite->use_rx_pong_buffer_next; 495 goto try_again; 496 } 497 } 498 499 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ 500 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); 501 xemaclite_alignedread(addr, etherrxbuff, first_read); 502 503 /* Detect real packet size */ 504 eth = (struct ethernet_hdr *)etherrxbuff; 505 switch (ntohs(eth->et_protlen)) { 506 case PROT_ARP: 507 length = first_read; 508 debug("ARP Packet %x\n", length); 509 break; 510 case PROT_IP: 511 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); 512 length = ntohs(ip->ip_len); 513 length += ETHER_HDR_SIZE + ETH_FCS_LEN; 514 debug("IP Packet %x\n", length); 515 break; 516 default: 517 debug("Other Packet\n"); 518 length = PKTSIZE; 519 break; 520 } 521 522 /* Read the rest of the packet which is longer then first read */ 523 if (length != first_read) 524 xemaclite_alignedread(addr + first_read, 525 etherrxbuff + first_read, 526 length - first_read); 527 528 /* Acknowledge the frame */ 529 reg = in_be32(ack); 530 reg &= ~XEL_RSR_RECV_DONE_MASK; 531 out_be32(ack, reg); 532 533 debug("Packet receive from 0x%p, length %dB\n", addr, length); 534 net_process_received_packet((uchar *)etherrxbuff, length); 535 return length; 536 537 } 538 539 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 540 static int emaclite_miiphy_read(const char *devname, uchar addr, 541 uchar reg, ushort *val) 542 { 543 u32 ret; 544 struct eth_device *dev = eth_get_dev(); 545 546 ret = phyread(dev->priv, addr, reg, val); 547 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); 548 return ret; 549 } 550 551 static int emaclite_miiphy_write(const char *devname, uchar addr, 552 uchar reg, ushort val) 553 { 554 struct eth_device *dev = eth_get_dev(); 555 556 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); 557 return phywrite(dev->priv, addr, reg, val); 558 } 559 #endif 560 561 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, 562 int txpp, int rxpp) 563 { 564 struct eth_device *dev; 565 struct xemaclite *emaclite; 566 struct emaclite_regs *regs; 567 568 dev = calloc(1, sizeof(*dev)); 569 if (dev == NULL) 570 return -1; 571 572 emaclite = calloc(1, sizeof(struct xemaclite)); 573 if (emaclite == NULL) { 574 free(dev); 575 return -1; 576 } 577 578 dev->priv = emaclite; 579 580 emaclite->txpp = txpp; 581 emaclite->rxpp = rxpp; 582 583 sprintf(dev->name, "Xelite.%lx", base_addr); 584 585 emaclite->regs = (struct emaclite_regs *)base_addr; 586 regs = emaclite->regs; 587 dev->iobase = base_addr; 588 dev->init = emaclite_init; 589 dev->halt = emaclite_halt; 590 dev->send = emaclite_send; 591 dev->recv = emaclite_recv; 592 593 #ifdef CONFIG_PHY_ADDR 594 emaclite->phyaddr = CONFIG_PHY_ADDR; 595 #else 596 emaclite->phyaddr = -1; 597 #endif 598 599 eth_register(dev); 600 601 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 602 miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); 603 emaclite->bus = miiphy_get_dev_by_name(dev->name); 604 605 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 606 #endif 607 608 return 1; 609 } 610