1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <config.h> 13 #include <console.h> 14 #include <malloc.h> 15 #include <asm/io.h> 16 #include <phy.h> 17 #include <miiphy.h> 18 #include <fdtdec.h> 19 #include <asm-generic/errno.h> 20 21 #undef DEBUG 22 23 #define ENET_ADDR_LENGTH 6 24 25 /* EmacLite constants */ 26 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ 27 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 28 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 29 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 30 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 31 32 /* Xmit complete */ 33 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 34 /* Xmit interrupt enable bit */ 35 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 36 /* Program the MAC address */ 37 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 38 /* define for programming the MAC address into the EMAC Lite */ 39 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 40 41 /* Transmit packet length upper byte */ 42 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 43 /* Transmit packet length lower byte */ 44 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 45 46 /* Recv complete */ 47 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 48 /* Recv interrupt enable bit */ 49 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 50 51 /* MDIO Address Register Bit Masks */ 52 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 53 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 54 #define XEL_MDIOADDR_PHYADR_SHIFT 5 55 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 56 57 /* MDIO Write Data Register Bit Masks */ 58 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 59 60 /* MDIO Read Data Register Bit Masks */ 61 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 62 63 /* MDIO Control Register Bit Masks */ 64 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 65 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 66 67 struct emaclite_regs { 68 u32 tx_ping; /* 0x0 - TX Ping buffer */ 69 u32 reserved1[504]; 70 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ 71 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ 72 u32 mdiord;/* 0x7ec - MDIO Read Data Register */ 73 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ 74 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ 75 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ 76 u32 tx_ping_tsr; /* 0x7fc - Tx status */ 77 u32 tx_pong; /* 0x800 - TX Pong buffer */ 78 u32 reserved2[508]; 79 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ 80 u32 reserved3; /* 0xff8 */ 81 u32 tx_pong_tsr; /* 0xffc - Tx status */ 82 u32 rx_ping; /* 0x1000 - Receive Buffer */ 83 u32 reserved4[510]; 84 u32 rx_ping_rsr; /* 0x17fc - Rx status */ 85 u32 rx_pong; /* 0x1800 - Receive Buffer */ 86 u32 reserved5[510]; 87 u32 rx_pong_rsr; /* 0x1ffc - Rx status */ 88 }; 89 90 struct xemaclite { 91 u32 nexttxbuffertouse; /* Next TX buffer to write to */ 92 u32 nextrxbuffertouse; /* Next RX buffer to read from */ 93 u32 txpp; /* TX ping pong buffer */ 94 u32 rxpp; /* RX ping pong buffer */ 95 int phyaddr; 96 struct emaclite_regs *regs; 97 struct phy_device *phydev; 98 struct mii_dev *bus; 99 }; 100 101 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ 102 103 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) 104 { 105 u32 i; 106 u32 alignbuffer; 107 u32 *to32ptr; 108 u32 *from32ptr; 109 u8 *to8ptr; 110 u8 *from8ptr; 111 112 from32ptr = (u32 *) srcptr; 113 114 /* Word aligned buffer, no correction needed. */ 115 to32ptr = (u32 *) destptr; 116 while (bytecount > 3) { 117 *to32ptr++ = *from32ptr++; 118 bytecount -= 4; 119 } 120 to8ptr = (u8 *) to32ptr; 121 122 alignbuffer = *from32ptr++; 123 from8ptr = (u8 *) &alignbuffer; 124 125 for (i = 0; i < bytecount; i++) 126 *to8ptr++ = *from8ptr++; 127 } 128 129 static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) 130 { 131 u32 i; 132 u32 alignbuffer; 133 u32 *to32ptr = (u32 *) destptr; 134 u32 *from32ptr; 135 u8 *to8ptr; 136 u8 *from8ptr; 137 138 from32ptr = (u32 *) srcptr; 139 while (bytecount > 3) { 140 141 *to32ptr++ = *from32ptr++; 142 bytecount -= 4; 143 } 144 145 alignbuffer = 0; 146 to8ptr = (u8 *) &alignbuffer; 147 from8ptr = (u8 *) from32ptr; 148 149 for (i = 0; i < bytecount; i++) 150 *to8ptr++ = *from8ptr++; 151 152 *to32ptr++ = alignbuffer; 153 } 154 155 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 156 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 157 bool set, unsigned int timeout) 158 { 159 u32 val; 160 unsigned long start = get_timer(0); 161 162 while (1) { 163 val = readl(reg); 164 165 if (!set) 166 val = ~val; 167 168 if ((val & mask) == mask) 169 return 0; 170 171 if (get_timer(start) > timeout) 172 break; 173 174 if (ctrlc()) { 175 puts("Abort\n"); 176 return -EINTR; 177 } 178 179 udelay(1); 180 } 181 182 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 183 func, reg, mask, set); 184 185 return -ETIMEDOUT; 186 } 187 188 static int mdio_wait(struct emaclite_regs *regs) 189 { 190 return wait_for_bit(__func__, ®s->mdioctrl, 191 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); 192 } 193 194 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 195 u16 *data) 196 { 197 struct emaclite_regs *regs = emaclite->regs; 198 199 if (mdio_wait(regs)) 200 return 1; 201 202 u32 ctrl_reg = in_be32(®s->mdioctrl); 203 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | 204 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 205 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 206 207 if (mdio_wait(regs)) 208 return 1; 209 210 /* Read data */ 211 *data = in_be32(®s->mdiord); 212 return 0; 213 } 214 215 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 216 u16 data) 217 { 218 struct emaclite_regs *regs = emaclite->regs; 219 220 if (mdio_wait(regs)) 221 return 1; 222 223 /* 224 * Write the PHY address, register number and clear the OP bit in the 225 * MDIO Address register and then write the value into the MDIO Write 226 * Data register. Finally, set the Status bit in the MDIO Control 227 * register to start a MDIO write transaction. 228 */ 229 u32 ctrl_reg = in_be32(®s->mdioctrl); 230 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & 231 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 232 out_be32(®s->mdiowr, data); 233 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 234 235 if (mdio_wait(regs)) 236 return 1; 237 238 return 0; 239 } 240 #endif 241 242 static void emaclite_halt(struct eth_device *dev) 243 { 244 debug("eth_halt\n"); 245 } 246 247 /* Use MII register 1 (MII status register) to detect PHY */ 248 #define PHY_DETECT_REG 1 249 250 /* Mask used to verify certain PHY features (or register contents) 251 * in the register above: 252 * 0x1000: 10Mbps full duplex support 253 * 0x0800: 10Mbps half duplex support 254 * 0x0008: Auto-negotiation support 255 */ 256 #define PHY_DETECT_MASK 0x1808 257 258 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 259 static int setup_phy(struct eth_device *dev) 260 { 261 int i; 262 u16 phyreg; 263 struct xemaclite *emaclite = dev->priv; 264 struct phy_device *phydev; 265 266 u32 supported = SUPPORTED_10baseT_Half | 267 SUPPORTED_10baseT_Full | 268 SUPPORTED_100baseT_Half | 269 SUPPORTED_100baseT_Full; 270 271 if (emaclite->phyaddr != -1) { 272 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); 273 if ((phyreg != 0xFFFF) && 274 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 275 /* Found a valid PHY address */ 276 debug("Default phy address %d is valid\n", 277 emaclite->phyaddr); 278 } else { 279 debug("PHY address is not setup correctly %d\n", 280 emaclite->phyaddr); 281 emaclite->phyaddr = -1; 282 } 283 } 284 285 if (emaclite->phyaddr == -1) { 286 /* detect the PHY address */ 287 for (i = 31; i >= 0; i--) { 288 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); 289 if ((phyreg != 0xFFFF) && 290 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 291 /* Found a valid PHY address */ 292 emaclite->phyaddr = i; 293 debug("emaclite: Found valid phy address, %d\n", 294 i); 295 break; 296 } 297 } 298 } 299 300 /* interface - look at tsec */ 301 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, 302 PHY_INTERFACE_MODE_MII); 303 /* 304 * Phy can support 1000baseT but device NOT that's why phydev->supported 305 * must be setup for 1000baseT. phydev->advertising setups what speeds 306 * will be used for autonegotiation where 1000baseT must be disabled. 307 */ 308 phydev->supported = supported | SUPPORTED_1000baseT_Half | 309 SUPPORTED_1000baseT_Full; 310 phydev->advertising = supported; 311 emaclite->phydev = phydev; 312 phy_config(phydev); 313 phy_startup(phydev); 314 315 if (!phydev->link) { 316 printf("%s: No link.\n", phydev->dev->name); 317 return 0; 318 } 319 320 /* Do not setup anything */ 321 return 1; 322 } 323 #endif 324 325 static int emaclite_init(struct eth_device *dev, bd_t *bis) 326 { 327 struct xemaclite *emaclite = dev->priv; 328 struct emaclite_regs *regs = emaclite->regs; 329 330 debug("EmacLite Initialization Started\n"); 331 332 /* 333 * TX - TX_PING & TX_PONG initialization 334 */ 335 /* Restart PING TX */ 336 out_be32(®s->tx_ping_tsr, 0); 337 /* Copy MAC address */ 338 xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_ping, 339 ENET_ADDR_LENGTH); 340 /* Set the length */ 341 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); 342 /* Update the MAC address in the EMAC Lite */ 343 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); 344 /* Wait for EMAC Lite to finish with the MAC address update */ 345 while ((in_be32 (®s->tx_ping_tsr) & 346 XEL_TSR_PROG_MAC_ADDR) != 0) 347 ; 348 349 if (emaclite->txpp) { 350 /* The same operation with PONG TX */ 351 out_be32(®s->tx_pong_tsr, 0); 352 xemaclite_alignedwrite(dev->enetaddr, (u32)®s->tx_pong, 353 ENET_ADDR_LENGTH); 354 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); 355 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); 356 while ((in_be32(®s->tx_pong_tsr) & 357 XEL_TSR_PROG_MAC_ADDR) != 0) 358 ; 359 } 360 361 /* 362 * RX - RX_PING & RX_PONG initialization 363 */ 364 /* Write out the value to flush the RX buffer */ 365 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); 366 367 if (emaclite->rxpp) 368 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); 369 370 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 371 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 372 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) 373 if (!setup_phy(dev)) 374 return -1; 375 #endif 376 debug("EmacLite Initialization complete\n"); 377 return 0; 378 } 379 380 static int xemaclite_txbufferavailable(struct xemaclite *emaclite) 381 { 382 u32 tmp; 383 struct emaclite_regs *regs = emaclite->regs; 384 385 /* 386 * Read the other buffer register 387 * and determine if the other buffer is available 388 */ 389 tmp = ~in_be32(®s->tx_ping_tsr); 390 if (emaclite->txpp) 391 tmp |= ~in_be32(®s->tx_pong_tsr); 392 393 return !(tmp & XEL_TSR_XMIT_BUSY_MASK); 394 } 395 396 static int emaclite_send(struct eth_device *dev, void *ptr, int len) 397 { 398 u32 reg; 399 u32 baseaddress; 400 struct xemaclite *emaclite = dev->priv; 401 struct emaclite_regs *regs = emaclite->regs; 402 403 u32 maxtry = 1000; 404 405 if (len > PKTSIZE) 406 len = PKTSIZE; 407 408 while (xemaclite_txbufferavailable(emaclite) && maxtry) { 409 udelay(10); 410 maxtry--; 411 } 412 413 if (!maxtry) { 414 printf("Error: Timeout waiting for ethernet TX buffer\n"); 415 /* Restart PING TX */ 416 out_be32(®s->tx_ping_tsr, 0); 417 if (emaclite->txpp) { 418 out_be32(®s->tx_pong_tsr, 0); 419 } 420 return -1; 421 } 422 423 /* Determine the expected TX buffer address */ 424 baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); 425 426 /* Determine if the expected buffer address is empty */ 427 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 428 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 429 if (emaclite->txpp) 430 emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; 431 432 debug("Send packet from 0x%x\n", baseaddress); 433 /* Write the frame to the buffer */ 434 xemaclite_alignedwrite(ptr, baseaddress, len); 435 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & 436 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); 437 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 438 reg |= XEL_TSR_XMIT_BUSY_MASK; 439 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 440 return 0; 441 } 442 443 if (emaclite->txpp) { 444 /* Switch to second buffer */ 445 baseaddress ^= XEL_BUFFER_OFFSET; 446 /* Determine if the expected buffer address is empty */ 447 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 448 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 449 debug("Send packet from 0x%x\n", baseaddress); 450 /* Write the frame to the buffer */ 451 xemaclite_alignedwrite(ptr, baseaddress, len); 452 out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & 453 (XEL_TPLR_LENGTH_MASK_HI | 454 XEL_TPLR_LENGTH_MASK_LO))); 455 reg = in_be32 (baseaddress + XEL_TSR_OFFSET); 456 reg |= XEL_TSR_XMIT_BUSY_MASK; 457 out_be32 (baseaddress + XEL_TSR_OFFSET, reg); 458 return 0; 459 } 460 } 461 462 puts("Error while sending frame\n"); 463 return -1; 464 } 465 466 static int emaclite_recv(struct eth_device *dev) 467 { 468 u32 length; 469 u32 reg; 470 u32 baseaddress; 471 struct xemaclite *emaclite = dev->priv; 472 473 baseaddress = dev->iobase + emaclite->nextrxbuffertouse; 474 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 475 debug("Testing data at address 0x%x\n", baseaddress); 476 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 477 if (emaclite->rxpp) 478 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; 479 } else { 480 481 if (!emaclite->rxpp) { 482 debug("No data was available - address 0x%x\n", 483 baseaddress); 484 return 0; 485 } else { 486 baseaddress ^= XEL_BUFFER_OFFSET; 487 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 488 if ((reg & XEL_RSR_RECV_DONE_MASK) != 489 XEL_RSR_RECV_DONE_MASK) { 490 debug("No data was available - address 0x%x\n", 491 baseaddress); 492 return 0; 493 } 494 } 495 } 496 /* Get the length of the frame that arrived */ 497 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & 498 0xFFFF0000 ) >> 16) { 499 case 0x806: 500 length = 42 + 20; /* FIXME size of ARP */ 501 debug("ARP Packet\n"); 502 break; 503 case 0x800: 504 length = 14 + 14 + 505 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 506 0x10))) & 0xFFFF0000) >> 16); 507 /* FIXME size of IP packet */ 508 debug ("IP Packet\n"); 509 break; 510 default: 511 debug("Other Packet\n"); 512 length = PKTSIZE; 513 break; 514 } 515 516 xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), 517 etherrxbuff, length); 518 519 /* Acknowledge the frame */ 520 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 521 reg &= ~XEL_RSR_RECV_DONE_MASK; 522 out_be32 (baseaddress + XEL_RSR_OFFSET, reg); 523 524 debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); 525 net_process_received_packet((uchar *)etherrxbuff, length); 526 return length; 527 528 } 529 530 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 531 static int emaclite_miiphy_read(const char *devname, uchar addr, 532 uchar reg, ushort *val) 533 { 534 u32 ret; 535 struct eth_device *dev = eth_get_dev(); 536 537 ret = phyread(dev->priv, addr, reg, val); 538 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); 539 return ret; 540 } 541 542 static int emaclite_miiphy_write(const char *devname, uchar addr, 543 uchar reg, ushort val) 544 { 545 struct eth_device *dev = eth_get_dev(); 546 547 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); 548 return phywrite(dev->priv, addr, reg, val); 549 } 550 #endif 551 552 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, 553 int txpp, int rxpp) 554 { 555 struct eth_device *dev; 556 struct xemaclite *emaclite; 557 struct emaclite_regs *regs; 558 559 dev = calloc(1, sizeof(*dev)); 560 if (dev == NULL) 561 return -1; 562 563 emaclite = calloc(1, sizeof(struct xemaclite)); 564 if (emaclite == NULL) { 565 free(dev); 566 return -1; 567 } 568 569 dev->priv = emaclite; 570 571 emaclite->txpp = txpp; 572 emaclite->rxpp = rxpp; 573 574 sprintf(dev->name, "Xelite.%lx", base_addr); 575 576 emaclite->regs = (struct emaclite_regs *)base_addr; 577 regs = emaclite->regs; 578 dev->iobase = base_addr; 579 dev->init = emaclite_init; 580 dev->halt = emaclite_halt; 581 dev->send = emaclite_send; 582 dev->recv = emaclite_recv; 583 584 #ifdef CONFIG_PHY_ADDR 585 emaclite->phyaddr = CONFIG_PHY_ADDR; 586 #else 587 emaclite->phyaddr = -1; 588 #endif 589 590 eth_register(dev); 591 592 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 593 miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); 594 emaclite->bus = miiphy_get_dev_by_name(dev->name); 595 596 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 597 #endif 598 599 return 1; 600 } 601