1 /* 2 * (C) Copyright 2007-2009 Michal Simek 3 * (C) Copyright 2003 Xilinx Inc. 4 * 5 * Michal SIMEK <monstr@monstr.eu> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <net.h> 12 #include <config.h> 13 #include <console.h> 14 #include <malloc.h> 15 #include <asm/io.h> 16 #include <phy.h> 17 #include <miiphy.h> 18 #include <fdtdec.h> 19 #include <asm-generic/errno.h> 20 21 #undef DEBUG 22 23 #define ENET_ADDR_LENGTH 6 24 25 /* EmacLite constants */ 26 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ 27 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 28 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 29 30 /* Xmit complete */ 31 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL 32 /* Xmit interrupt enable bit */ 33 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL 34 /* Program the MAC address */ 35 #define XEL_TSR_PROGRAM_MASK 0x00000002UL 36 /* define for programming the MAC address into the EMAC Lite */ 37 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 38 39 /* Transmit packet length upper byte */ 40 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL 41 /* Transmit packet length lower byte */ 42 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL 43 44 /* Recv complete */ 45 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL 46 /* Recv interrupt enable bit */ 47 #define XEL_RSR_RECV_IE_MASK 0x00000008UL 48 49 /* MDIO Address Register Bit Masks */ 50 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 51 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 52 #define XEL_MDIOADDR_PHYADR_SHIFT 5 53 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 54 55 /* MDIO Write Data Register Bit Masks */ 56 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 57 58 /* MDIO Read Data Register Bit Masks */ 59 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 60 61 /* MDIO Control Register Bit Masks */ 62 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 63 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 64 65 struct emaclite_regs { 66 u32 tx_ping; /* 0x0 - TX Ping buffer */ 67 u32 reserved1[504]; 68 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ 69 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ 70 u32 mdiord;/* 0x7ec - MDIO Read Data Register */ 71 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ 72 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ 73 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ 74 u32 tx_ping_tsr; /* 0x7fc - Tx status */ 75 u32 tx_pong; /* 0x800 - TX Pong buffer */ 76 u32 reserved2[508]; 77 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ 78 u32 reserved3; /* 0xff8 */ 79 u32 tx_pong_tsr; /* 0xffc - Tx status */ 80 u32 rx_ping; /* 0x1000 - Receive Buffer */ 81 u32 reserved4[510]; 82 u32 rx_ping_rsr; /* 0x17fc - Rx status */ 83 u32 rx_pong; /* 0x1800 - Receive Buffer */ 84 u32 reserved5[510]; 85 u32 rx_pong_rsr; /* 0x1ffc - Rx status */ 86 }; 87 88 struct xemaclite { 89 u32 nextrxbuffertouse; /* Next RX buffer to read from */ 90 u32 txpp; /* TX ping pong buffer */ 91 u32 rxpp; /* RX ping pong buffer */ 92 int phyaddr; 93 struct emaclite_regs *regs; 94 struct phy_device *phydev; 95 struct mii_dev *bus; 96 }; 97 98 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ 99 100 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) 101 { 102 u32 i; 103 u32 alignbuffer; 104 u32 *to32ptr; 105 u32 *from32ptr; 106 u8 *to8ptr; 107 u8 *from8ptr; 108 109 from32ptr = (u32 *) srcptr; 110 111 /* Word aligned buffer, no correction needed. */ 112 to32ptr = (u32 *) destptr; 113 while (bytecount > 3) { 114 *to32ptr++ = *from32ptr++; 115 bytecount -= 4; 116 } 117 to8ptr = (u8 *) to32ptr; 118 119 alignbuffer = *from32ptr++; 120 from8ptr = (u8 *) &alignbuffer; 121 122 for (i = 0; i < bytecount; i++) 123 *to8ptr++ = *from8ptr++; 124 } 125 126 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) 127 { 128 u32 i; 129 u32 alignbuffer; 130 u32 *to32ptr = (u32 *) destptr; 131 u32 *from32ptr; 132 u8 *to8ptr; 133 u8 *from8ptr; 134 135 from32ptr = (u32 *) srcptr; 136 while (bytecount > 3) { 137 138 *to32ptr++ = *from32ptr++; 139 bytecount -= 4; 140 } 141 142 alignbuffer = 0; 143 to8ptr = (u8 *) &alignbuffer; 144 from8ptr = (u8 *) from32ptr; 145 146 for (i = 0; i < bytecount; i++) 147 *to8ptr++ = *from8ptr++; 148 149 *to32ptr++ = alignbuffer; 150 } 151 152 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 153 static int wait_for_bit(const char *func, u32 *reg, const u32 mask, 154 bool set, unsigned int timeout) 155 { 156 u32 val; 157 unsigned long start = get_timer(0); 158 159 while (1) { 160 val = readl(reg); 161 162 if (!set) 163 val = ~val; 164 165 if ((val & mask) == mask) 166 return 0; 167 168 if (get_timer(start) > timeout) 169 break; 170 171 if (ctrlc()) { 172 puts("Abort\n"); 173 return -EINTR; 174 } 175 176 udelay(1); 177 } 178 179 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", 180 func, reg, mask, set); 181 182 return -ETIMEDOUT; 183 } 184 185 static int mdio_wait(struct emaclite_regs *regs) 186 { 187 return wait_for_bit(__func__, ®s->mdioctrl, 188 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); 189 } 190 191 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 192 u16 *data) 193 { 194 struct emaclite_regs *regs = emaclite->regs; 195 196 if (mdio_wait(regs)) 197 return 1; 198 199 u32 ctrl_reg = in_be32(®s->mdioctrl); 200 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | 201 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 202 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 203 204 if (mdio_wait(regs)) 205 return 1; 206 207 /* Read data */ 208 *data = in_be32(®s->mdiord); 209 return 0; 210 } 211 212 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, 213 u16 data) 214 { 215 struct emaclite_regs *regs = emaclite->regs; 216 217 if (mdio_wait(regs)) 218 return 1; 219 220 /* 221 * Write the PHY address, register number and clear the OP bit in the 222 * MDIO Address register and then write the value into the MDIO Write 223 * Data register. Finally, set the Status bit in the MDIO Control 224 * register to start a MDIO write transaction. 225 */ 226 u32 ctrl_reg = in_be32(®s->mdioctrl); 227 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & 228 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); 229 out_be32(®s->mdiowr, data); 230 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); 231 232 if (mdio_wait(regs)) 233 return 1; 234 235 return 0; 236 } 237 #endif 238 239 static void emaclite_halt(struct eth_device *dev) 240 { 241 debug("eth_halt\n"); 242 } 243 244 /* Use MII register 1 (MII status register) to detect PHY */ 245 #define PHY_DETECT_REG 1 246 247 /* Mask used to verify certain PHY features (or register contents) 248 * in the register above: 249 * 0x1000: 10Mbps full duplex support 250 * 0x0800: 10Mbps half duplex support 251 * 0x0008: Auto-negotiation support 252 */ 253 #define PHY_DETECT_MASK 0x1808 254 255 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 256 static int setup_phy(struct eth_device *dev) 257 { 258 int i; 259 u16 phyreg; 260 struct xemaclite *emaclite = dev->priv; 261 struct phy_device *phydev; 262 263 u32 supported = SUPPORTED_10baseT_Half | 264 SUPPORTED_10baseT_Full | 265 SUPPORTED_100baseT_Half | 266 SUPPORTED_100baseT_Full; 267 268 if (emaclite->phyaddr != -1) { 269 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); 270 if ((phyreg != 0xFFFF) && 271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 272 /* Found a valid PHY address */ 273 debug("Default phy address %d is valid\n", 274 emaclite->phyaddr); 275 } else { 276 debug("PHY address is not setup correctly %d\n", 277 emaclite->phyaddr); 278 emaclite->phyaddr = -1; 279 } 280 } 281 282 if (emaclite->phyaddr == -1) { 283 /* detect the PHY address */ 284 for (i = 31; i >= 0; i--) { 285 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); 286 if ((phyreg != 0xFFFF) && 287 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 288 /* Found a valid PHY address */ 289 emaclite->phyaddr = i; 290 debug("emaclite: Found valid phy address, %d\n", 291 i); 292 break; 293 } 294 } 295 } 296 297 /* interface - look at tsec */ 298 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, 299 PHY_INTERFACE_MODE_MII); 300 /* 301 * Phy can support 1000baseT but device NOT that's why phydev->supported 302 * must be setup for 1000baseT. phydev->advertising setups what speeds 303 * will be used for autonegotiation where 1000baseT must be disabled. 304 */ 305 phydev->supported = supported | SUPPORTED_1000baseT_Half | 306 SUPPORTED_1000baseT_Full; 307 phydev->advertising = supported; 308 emaclite->phydev = phydev; 309 phy_config(phydev); 310 phy_startup(phydev); 311 312 if (!phydev->link) { 313 printf("%s: No link.\n", phydev->dev->name); 314 return 0; 315 } 316 317 /* Do not setup anything */ 318 return 1; 319 } 320 #endif 321 322 static int emaclite_init(struct eth_device *dev, bd_t *bis) 323 { 324 struct xemaclite *emaclite = dev->priv; 325 struct emaclite_regs *regs = emaclite->regs; 326 327 debug("EmacLite Initialization Started\n"); 328 329 /* 330 * TX - TX_PING & TX_PONG initialization 331 */ 332 /* Restart PING TX */ 333 out_be32(®s->tx_ping_tsr, 0); 334 /* Copy MAC address */ 335 xemaclite_alignedwrite(dev->enetaddr, ®s->tx_ping, 336 ENET_ADDR_LENGTH); 337 /* Set the length */ 338 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); 339 /* Update the MAC address in the EMAC Lite */ 340 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); 341 /* Wait for EMAC Lite to finish with the MAC address update */ 342 while ((in_be32 (®s->tx_ping_tsr) & 343 XEL_TSR_PROG_MAC_ADDR) != 0) 344 ; 345 346 if (emaclite->txpp) { 347 /* The same operation with PONG TX */ 348 out_be32(®s->tx_pong_tsr, 0); 349 xemaclite_alignedwrite(dev->enetaddr, ®s->tx_pong, 350 ENET_ADDR_LENGTH); 351 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); 352 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); 353 while ((in_be32(®s->tx_pong_tsr) & 354 XEL_TSR_PROG_MAC_ADDR) != 0) 355 ; 356 } 357 358 /* 359 * RX - RX_PING & RX_PONG initialization 360 */ 361 /* Write out the value to flush the RX buffer */ 362 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); 363 364 if (emaclite->rxpp) 365 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); 366 367 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 368 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 369 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) 370 if (!setup_phy(dev)) 371 return -1; 372 #endif 373 debug("EmacLite Initialization complete\n"); 374 return 0; 375 } 376 377 static int xemaclite_txbufferavailable(struct xemaclite *emaclite) 378 { 379 u32 tmp; 380 struct emaclite_regs *regs = emaclite->regs; 381 382 /* 383 * Read the other buffer register 384 * and determine if the other buffer is available 385 */ 386 tmp = ~in_be32(®s->tx_ping_tsr); 387 if (emaclite->txpp) 388 tmp |= ~in_be32(®s->tx_pong_tsr); 389 390 return !(tmp & XEL_TSR_XMIT_BUSY_MASK); 391 } 392 393 static int emaclite_send(struct eth_device *dev, void *ptr, int len) 394 { 395 u32 reg; 396 struct xemaclite *emaclite = dev->priv; 397 struct emaclite_regs *regs = emaclite->regs; 398 399 u32 maxtry = 1000; 400 401 if (len > PKTSIZE) 402 len = PKTSIZE; 403 404 while (xemaclite_txbufferavailable(emaclite) && maxtry) { 405 udelay(10); 406 maxtry--; 407 } 408 409 if (!maxtry) { 410 printf("Error: Timeout waiting for ethernet TX buffer\n"); 411 /* Restart PING TX */ 412 out_be32(®s->tx_ping_tsr, 0); 413 if (emaclite->txpp) { 414 out_be32(®s->tx_pong_tsr, 0); 415 } 416 return -1; 417 } 418 419 /* Determine if the expected buffer address is empty */ 420 reg = in_be32(®s->tx_ping_tsr); 421 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 422 debug("Send packet from tx_ping buffer\n"); 423 /* Write the frame to the buffer */ 424 xemaclite_alignedwrite(ptr, ®s->tx_ping, len); 425 out_be32(®s->tx_ping_tplr, len & 426 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); 427 reg = in_be32(®s->tx_ping_tsr); 428 reg |= XEL_TSR_XMIT_BUSY_MASK; 429 out_be32(®s->tx_ping_tsr, reg); 430 return 0; 431 } 432 433 if (emaclite->txpp) { 434 /* Determine if the expected buffer address is empty */ 435 reg = in_be32(®s->tx_pong_tsr); 436 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { 437 debug("Send packet from tx_pong buffer\n"); 438 /* Write the frame to the buffer */ 439 xemaclite_alignedwrite(ptr, ®s->tx_pong, len); 440 out_be32(®s->tx_pong_tplr, len & 441 (XEL_TPLR_LENGTH_MASK_HI | 442 XEL_TPLR_LENGTH_MASK_LO)); 443 reg = in_be32(®s->tx_pong_tsr); 444 reg |= XEL_TSR_XMIT_BUSY_MASK; 445 out_be32(®s->tx_pong_tsr, reg); 446 return 0; 447 } 448 } 449 450 puts("Error while sending frame\n"); 451 return -1; 452 } 453 454 static int emaclite_recv(struct eth_device *dev) 455 { 456 u32 length; 457 u32 reg; 458 u32 baseaddress; 459 struct xemaclite *emaclite = dev->priv; 460 461 baseaddress = dev->iobase + emaclite->nextrxbuffertouse; 462 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 463 debug("Testing data at address 0x%x\n", baseaddress); 464 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 465 if (emaclite->rxpp) 466 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; 467 } else { 468 469 if (!emaclite->rxpp) { 470 debug("No data was available - address 0x%x\n", 471 baseaddress); 472 return 0; 473 } else { 474 baseaddress ^= XEL_BUFFER_OFFSET; 475 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 476 if ((reg & XEL_RSR_RECV_DONE_MASK) != 477 XEL_RSR_RECV_DONE_MASK) { 478 debug("No data was available - address 0x%x\n", 479 baseaddress); 480 return 0; 481 } 482 } 483 } 484 /* Get the length of the frame that arrived */ 485 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & 486 0xFFFF0000 ) >> 16) { 487 case 0x806: 488 length = 42 + 20; /* FIXME size of ARP */ 489 debug("ARP Packet\n"); 490 break; 491 case 0x800: 492 length = 14 + 14 + 493 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 494 0x10))) & 0xFFFF0000) >> 16); 495 /* FIXME size of IP packet */ 496 debug ("IP Packet\n"); 497 break; 498 default: 499 debug("Other Packet\n"); 500 length = PKTSIZE; 501 break; 502 } 503 504 xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), 505 etherrxbuff, length); 506 507 /* Acknowledge the frame */ 508 reg = in_be32 (baseaddress + XEL_RSR_OFFSET); 509 reg &= ~XEL_RSR_RECV_DONE_MASK; 510 out_be32 (baseaddress + XEL_RSR_OFFSET, reg); 511 512 debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); 513 net_process_received_packet((uchar *)etherrxbuff, length); 514 return length; 515 516 } 517 518 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 519 static int emaclite_miiphy_read(const char *devname, uchar addr, 520 uchar reg, ushort *val) 521 { 522 u32 ret; 523 struct eth_device *dev = eth_get_dev(); 524 525 ret = phyread(dev->priv, addr, reg, val); 526 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); 527 return ret; 528 } 529 530 static int emaclite_miiphy_write(const char *devname, uchar addr, 531 uchar reg, ushort val) 532 { 533 struct eth_device *dev = eth_get_dev(); 534 535 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); 536 return phywrite(dev->priv, addr, reg, val); 537 } 538 #endif 539 540 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, 541 int txpp, int rxpp) 542 { 543 struct eth_device *dev; 544 struct xemaclite *emaclite; 545 struct emaclite_regs *regs; 546 547 dev = calloc(1, sizeof(*dev)); 548 if (dev == NULL) 549 return -1; 550 551 emaclite = calloc(1, sizeof(struct xemaclite)); 552 if (emaclite == NULL) { 553 free(dev); 554 return -1; 555 } 556 557 dev->priv = emaclite; 558 559 emaclite->txpp = txpp; 560 emaclite->rxpp = rxpp; 561 562 sprintf(dev->name, "Xelite.%lx", base_addr); 563 564 emaclite->regs = (struct emaclite_regs *)base_addr; 565 regs = emaclite->regs; 566 dev->iobase = base_addr; 567 dev->init = emaclite_init; 568 dev->halt = emaclite_halt; 569 dev->send = emaclite_send; 570 dev->recv = emaclite_recv; 571 572 #ifdef CONFIG_PHY_ADDR 573 emaclite->phyaddr = CONFIG_PHY_ADDR; 574 #else 575 emaclite->phyaddr = -1; 576 #endif 577 578 eth_register(dev); 579 580 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 581 miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); 582 emaclite->bus = miiphy_get_dev_by_name(dev->name); 583 584 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); 585 #endif 586 587 return 1; 588 } 589