1 /* 2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011 PetaLogix 4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <net.h> 12 #include <malloc.h> 13 #include <asm/io.h> 14 #include <phy.h> 15 #include <miiphy.h> 16 17 #if !defined(CONFIG_PHYLIB) 18 # error AXI_ETHERNET requires PHYLIB 19 #endif 20 21 /* Link setup */ 22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 26 27 /* Interrupt Status/Enable/Mask Registers bit definitions */ 28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 30 31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 33 34 /* Transmitter Configuration (TC) Register bit definitions */ 35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 36 37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 38 39 /* MDIO Management Configuration (MC) Register bit definitions */ 40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 41 42 /* MDIO Management Control Register (MCR) Register bit definitions */ 43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 51 52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 53 54 /* DMA macros */ 55 /* Bitmasks of XAXIDMA_CR_OFFSET register */ 56 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 57 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 58 59 /* Bitmasks of XAXIDMA_SR_OFFSET register */ 60 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 61 62 /* Bitmask for interrupts */ 63 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 64 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 65 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 66 67 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 68 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 69 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 70 71 #define DMAALIGN 128 72 73 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 74 75 /* Reflect dma offsets */ 76 struct axidma_reg { 77 u32 control; /* DMACR */ 78 u32 status; /* DMASR */ 79 u32 current; /* CURDESC */ 80 u32 reserved; 81 u32 tail; /* TAILDESC */ 82 }; 83 84 /* Private driver structures */ 85 struct axidma_priv { 86 struct axidma_reg *dmatx; 87 struct axidma_reg *dmarx; 88 int phyaddr; 89 struct axi_regs *iobase; 90 struct phy_device *phydev; 91 struct mii_dev *bus; 92 }; 93 94 /* BD descriptors */ 95 struct axidma_bd { 96 u32 next; /* Next descriptor pointer */ 97 u32 reserved1; 98 u32 phys; /* Buffer address */ 99 u32 reserved2; 100 u32 reserved3; 101 u32 reserved4; 102 u32 cntrl; /* Control */ 103 u32 status; /* Status */ 104 u32 app0; 105 u32 app1; /* TX start << 16 | insert */ 106 u32 app2; /* TX csum seed */ 107 u32 app3; 108 u32 app4; 109 u32 sw_id_offset; 110 u32 reserved5; 111 u32 reserved6; 112 }; 113 114 /* Static BDs - driver uses only one BD */ 115 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 116 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 117 118 struct axi_regs { 119 u32 reserved[3]; 120 u32 is; /* 0xC: Interrupt status */ 121 u32 reserved2; 122 u32 ie; /* 0x14: Interrupt enable */ 123 u32 reserved3[251]; 124 u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 125 u32 tc; /* 0x408: Tx Configuration */ 126 u32 reserved4; 127 u32 emmc; /* 0x410: EMAC mode configuration */ 128 u32 reserved5[59]; 129 u32 mdio_mc; /* 0x500: MII Management Config */ 130 u32 mdio_mcr; /* 0x504: MII Management Control */ 131 u32 mdio_mwd; /* 0x508: MII Management Write Data */ 132 u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 133 u32 reserved6[124]; 134 u32 uaw0; /* 0x700: Unicast address word 0 */ 135 u32 uaw1; /* 0x704: Unicast address word 1 */ 136 }; 137 138 /* Use MII register 1 (MII status register) to detect PHY */ 139 #define PHY_DETECT_REG 1 140 141 /* 142 * Mask used to verify certain PHY features (or register contents) 143 * in the register above: 144 * 0x1000: 10Mbps full duplex support 145 * 0x0800: 10Mbps half duplex support 146 * 0x0008: Auto-negotiation support 147 */ 148 #define PHY_DETECT_MASK 0x1808 149 150 static inline int mdio_wait(struct axi_regs *regs) 151 { 152 u32 timeout = 200; 153 154 /* Wait till MDIO interface is ready to accept a new transaction. */ 155 while (timeout && (!(in_be32(®s->mdio_mcr) 156 & XAE_MDIO_MCR_READY_MASK))) { 157 timeout--; 158 udelay(1); 159 } 160 if (!timeout) { 161 printf("%s: Timeout\n", __func__); 162 return 1; 163 } 164 return 0; 165 } 166 167 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 168 u16 *val) 169 { 170 struct axi_regs *regs = priv->iobase; 171 u32 mdioctrlreg = 0; 172 173 if (mdio_wait(regs)) 174 return 1; 175 176 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 177 XAE_MDIO_MCR_PHYAD_MASK) | 178 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 179 & XAE_MDIO_MCR_REGAD_MASK) | 180 XAE_MDIO_MCR_INITIATE_MASK | 181 XAE_MDIO_MCR_OP_READ_MASK; 182 183 out_be32(®s->mdio_mcr, mdioctrlreg); 184 185 if (mdio_wait(regs)) 186 return 1; 187 188 /* Read data */ 189 *val = in_be32(®s->mdio_mrd); 190 return 0; 191 } 192 193 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 194 u32 data) 195 { 196 struct axi_regs *regs = priv->iobase; 197 u32 mdioctrlreg = 0; 198 199 if (mdio_wait(regs)) 200 return 1; 201 202 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 203 XAE_MDIO_MCR_PHYAD_MASK) | 204 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 205 & XAE_MDIO_MCR_REGAD_MASK) | 206 XAE_MDIO_MCR_INITIATE_MASK | 207 XAE_MDIO_MCR_OP_WRITE_MASK; 208 209 /* Write data */ 210 out_be32(®s->mdio_mwd, data); 211 212 out_be32(®s->mdio_mcr, mdioctrlreg); 213 214 if (mdio_wait(regs)) 215 return 1; 216 217 return 0; 218 } 219 220 /* Setting axi emac and phy to proper setting */ 221 static int setup_phy(struct eth_device *dev) 222 { 223 u16 phyreg; 224 u32 i, speed, emmc_reg, ret; 225 struct axidma_priv *priv = dev->priv; 226 struct axi_regs *regs = priv->iobase; 227 struct phy_device *phydev; 228 229 u32 supported = SUPPORTED_10baseT_Half | 230 SUPPORTED_10baseT_Full | 231 SUPPORTED_100baseT_Half | 232 SUPPORTED_100baseT_Full | 233 SUPPORTED_1000baseT_Half | 234 SUPPORTED_1000baseT_Full; 235 236 if (priv->phyaddr == -1) { 237 /* Detect the PHY address */ 238 for (i = 31; i >= 0; i--) { 239 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); 240 if (!ret && (phyreg != 0xFFFF) && 241 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 242 /* Found a valid PHY address */ 243 priv->phyaddr = i; 244 debug("axiemac: Found valid phy address, %x\n", 245 i); 246 break; 247 } 248 } 249 } 250 251 /* Interface - look at tsec */ 252 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 253 254 phydev->supported &= supported; 255 phydev->advertising = phydev->supported; 256 priv->phydev = phydev; 257 phy_config(phydev); 258 if (phy_startup(phydev)) { 259 printf("axiemac: could not initialize PHY %s\n", 260 phydev->dev->name); 261 return 0; 262 } 263 if (!phydev->link) { 264 printf("%s: No link.\n", phydev->dev->name); 265 return 0; 266 } 267 268 switch (phydev->speed) { 269 case 1000: 270 speed = XAE_EMMC_LINKSPD_1000; 271 break; 272 case 100: 273 speed = XAE_EMMC_LINKSPD_100; 274 break; 275 case 10: 276 speed = XAE_EMMC_LINKSPD_10; 277 break; 278 default: 279 return 0; 280 } 281 282 /* Setup the emac for the phy speed */ 283 emmc_reg = in_be32(®s->emmc); 284 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 285 emmc_reg |= speed; 286 287 /* Write new speed setting out to Axi Ethernet */ 288 out_be32(®s->emmc, emmc_reg); 289 290 /* 291 * Setting the operating speed of the MAC needs a delay. There 292 * doesn't seem to be register to poll, so please consider this 293 * during your application design. 294 */ 295 udelay(1); 296 297 return 1; 298 } 299 300 /* STOP DMA transfers */ 301 static void axiemac_halt(struct eth_device *dev) 302 { 303 struct axidma_priv *priv = dev->priv; 304 u32 temp; 305 306 /* Stop the hardware */ 307 temp = in_be32(&priv->dmatx->control); 308 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 309 out_be32(&priv->dmatx->control, temp); 310 311 temp = in_be32(&priv->dmarx->control); 312 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 313 out_be32(&priv->dmarx->control, temp); 314 315 debug("axiemac: Halted\n"); 316 } 317 318 static int axi_ethernet_init(struct axidma_priv *priv) 319 { 320 struct axi_regs *regs = priv->iobase; 321 u32 timeout = 200; 322 323 /* 324 * Check the status of the MgtRdy bit in the interrupt status 325 * registers. This must be done to allow the MGT clock to become stable 326 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 327 * will be valid until this bit is valid. 328 * The bit is always a 1 for all other PHY interfaces. 329 */ 330 while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) { 331 timeout--; 332 udelay(1); 333 } 334 if (!timeout) { 335 printf("%s: Timeout\n", __func__); 336 return 1; 337 } 338 339 /* Stop the device and reset HW */ 340 /* Disable interrupts */ 341 out_be32(®s->ie, 0); 342 343 /* Disable the receiver */ 344 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); 345 346 /* 347 * Stopping the receiver in mid-packet causes a dropped packet 348 * indication from HW. Clear it. 349 */ 350 /* Set the interrupt status register to clear the interrupt */ 351 out_be32(®s->is, XAE_INT_RXRJECT_MASK); 352 353 /* Setup HW */ 354 /* Set default MDIO divisor */ 355 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 356 357 debug("axiemac: InitHw done\n"); 358 return 0; 359 } 360 361 static int axiemac_setup_mac(struct eth_device *dev) 362 { 363 struct axi_regs *regs = (struct axi_regs *)dev->iobase; 364 365 /* Set the MAC address */ 366 int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | 367 (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); 368 out_be32(®s->uaw0, val); 369 370 val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; 371 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 372 out_be32(®s->uaw1, val); 373 return 0; 374 } 375 376 /* Reset DMA engine */ 377 static void axi_dma_init(struct axidma_priv *priv) 378 { 379 u32 timeout = 500; 380 381 /* Reset the engine so the hardware starts from a known state */ 382 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); 383 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); 384 385 /* At the initialization time, hardware should finish reset quickly */ 386 while (timeout--) { 387 /* Check transmit/receive channel */ 388 /* Reset is done when the reset bit is low */ 389 if (!((in_be32(&priv->dmatx->control) | 390 in_be32(&priv->dmarx->control)) 391 & XAXIDMA_CR_RESET_MASK)) { 392 break; 393 } 394 } 395 if (!timeout) 396 printf("%s: Timeout\n", __func__); 397 } 398 399 static int axiemac_init(struct eth_device *dev, bd_t * bis) 400 { 401 struct axidma_priv *priv = dev->priv; 402 struct axi_regs *regs = (struct axi_regs *)dev->iobase; 403 u32 temp; 404 405 debug("axiemac: Init started\n"); 406 /* 407 * Initialize AXIDMA engine. AXIDMA engine must be initialized before 408 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 409 * reset, and since AXIDMA reset line is connected to AxiEthernet, this 410 * would ensure a reset of AxiEthernet. 411 */ 412 axi_dma_init(priv); 413 414 /* Initialize AxiEthernet hardware. */ 415 if (axi_ethernet_init(priv)) 416 return -1; 417 418 /* Disable all RX interrupts before RxBD space setup */ 419 temp = in_be32(&priv->dmarx->control); 420 temp &= ~XAXIDMA_IRQ_ALL_MASK; 421 out_be32(&priv->dmarx->control, temp); 422 423 /* Start DMA RX channel. Now it's ready to receive data.*/ 424 out_be32(&priv->dmarx->current, (u32)&rx_bd); 425 426 /* Setup the BD. */ 427 memset(&rx_bd, 0, sizeof(rx_bd)); 428 rx_bd.next = (u32)&rx_bd; 429 rx_bd.phys = (u32)&rxframe; 430 rx_bd.cntrl = sizeof(rxframe); 431 /* Flush the last BD so DMA core could see the updates */ 432 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 433 434 /* It is necessary to flush rxframe because if you don't do it 435 * then cache can contain uninitialized data */ 436 flush_cache((u32)&rxframe, sizeof(rxframe)); 437 438 /* Start the hardware */ 439 temp = in_be32(&priv->dmarx->control); 440 temp |= XAXIDMA_CR_RUNSTOP_MASK; 441 out_be32(&priv->dmarx->control, temp); 442 443 /* Rx BD is ready - start */ 444 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 445 446 /* Enable TX */ 447 out_be32(®s->tc, XAE_TC_TX_MASK); 448 /* Enable RX */ 449 out_be32(®s->rcw1, XAE_RCW1_RX_MASK); 450 451 /* PHY setup */ 452 if (!setup_phy(dev)) { 453 axiemac_halt(dev); 454 return -1; 455 } 456 457 debug("axiemac: Init complete\n"); 458 return 0; 459 } 460 461 static int axiemac_send(struct eth_device *dev, void *ptr, int len) 462 { 463 struct axidma_priv *priv = dev->priv; 464 u32 timeout; 465 466 if (len > PKTSIZE_ALIGN) 467 len = PKTSIZE_ALIGN; 468 469 /* Flush packet to main memory to be trasfered by DMA */ 470 flush_cache((u32)ptr, len); 471 472 /* Setup Tx BD */ 473 memset(&tx_bd, 0, sizeof(tx_bd)); 474 /* At the end of the ring, link the last BD back to the top */ 475 tx_bd.next = (u32)&tx_bd; 476 tx_bd.phys = (u32)ptr; 477 /* Save len */ 478 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 479 XAXIDMA_BD_CTRL_TXEOF_MASK; 480 481 /* Flush the last BD so DMA core could see the updates */ 482 flush_cache((u32)&tx_bd, sizeof(tx_bd)); 483 484 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 485 u32 temp; 486 out_be32(&priv->dmatx->current, (u32)&tx_bd); 487 /* Start the hardware */ 488 temp = in_be32(&priv->dmatx->control); 489 temp |= XAXIDMA_CR_RUNSTOP_MASK; 490 out_be32(&priv->dmatx->control, temp); 491 } 492 493 /* Start transfer */ 494 out_be32(&priv->dmatx->tail, (u32)&tx_bd); 495 496 /* Wait for transmission to complete */ 497 debug("axiemac: Waiting for tx to be done\n"); 498 timeout = 200; 499 while (timeout && (!(in_be32(&priv->dmatx->status) & 500 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { 501 timeout--; 502 udelay(1); 503 } 504 if (!timeout) { 505 printf("%s: Timeout\n", __func__); 506 return 1; 507 } 508 509 debug("axiemac: Sending complete\n"); 510 return 0; 511 } 512 513 static int isrxready(struct axidma_priv *priv) 514 { 515 u32 status; 516 517 /* Read pending interrupts */ 518 status = in_be32(&priv->dmarx->status); 519 520 /* Acknowledge pending interrupts */ 521 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); 522 523 /* 524 * If Reception done interrupt is asserted, call RX call back function 525 * to handle the processed BDs and then raise the according flag. 526 */ 527 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 528 return 1; 529 530 return 0; 531 } 532 533 static int axiemac_recv(struct eth_device *dev) 534 { 535 u32 length; 536 struct axidma_priv *priv = dev->priv; 537 u32 temp; 538 539 /* Wait for an incoming packet */ 540 if (!isrxready(priv)) 541 return 0; 542 543 debug("axiemac: RX data ready\n"); 544 545 /* Disable IRQ for a moment till packet is handled */ 546 temp = in_be32(&priv->dmarx->control); 547 temp &= ~XAXIDMA_IRQ_ALL_MASK; 548 out_be32(&priv->dmarx->control, temp); 549 550 length = rx_bd.app4 & 0xFFFF; /* max length mask */ 551 #ifdef DEBUG 552 print_buffer(&rxframe, &rxframe[0], 1, length, 16); 553 #endif 554 /* Pass the received frame up for processing */ 555 if (length) 556 net_process_received_packet(rxframe, length); 557 558 #ifdef DEBUG 559 /* It is useful to clear buffer to be sure that it is consistent */ 560 memset(rxframe, 0, sizeof(rxframe)); 561 #endif 562 /* Setup RxBD */ 563 /* Clear the whole buffer and setup it again - all flags are cleared */ 564 memset(&rx_bd, 0, sizeof(rx_bd)); 565 rx_bd.next = (u32)&rx_bd; 566 rx_bd.phys = (u32)&rxframe; 567 rx_bd.cntrl = sizeof(rxframe); 568 569 /* Write bd to HW */ 570 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 571 572 /* It is necessary to flush rxframe because if you don't do it 573 * then cache will contain previous packet */ 574 flush_cache((u32)&rxframe, sizeof(rxframe)); 575 576 /* Rx BD is ready - start again */ 577 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 578 579 debug("axiemac: RX completed, framelength = %d\n", length); 580 581 return length; 582 } 583 584 static int axiemac_miiphy_read(const char *devname, uchar addr, 585 uchar reg, ushort *val) 586 { 587 struct eth_device *dev = eth_get_dev(); 588 u32 ret; 589 590 ret = phyread(dev->priv, addr, reg, val); 591 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); 592 return ret; 593 } 594 595 static int axiemac_miiphy_write(const char *devname, uchar addr, 596 uchar reg, ushort val) 597 { 598 struct eth_device *dev = eth_get_dev(); 599 600 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); 601 return phywrite(dev->priv, addr, reg, val); 602 } 603 604 static int axiemac_bus_reset(struct mii_dev *bus) 605 { 606 debug("axiemac: Bus reset\n"); 607 return 0; 608 } 609 610 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, 611 unsigned long dma_addr) 612 { 613 struct eth_device *dev; 614 struct axidma_priv *priv; 615 616 dev = calloc(1, sizeof(struct eth_device)); 617 if (dev == NULL) 618 return -1; 619 620 dev->priv = calloc(1, sizeof(struct axidma_priv)); 621 if (dev->priv == NULL) { 622 free(dev); 623 return -1; 624 } 625 priv = dev->priv; 626 627 sprintf(dev->name, "aximac.%lx", base_addr); 628 629 dev->iobase = base_addr; 630 priv->iobase = (struct axi_regs *)base_addr; 631 priv->dmatx = (struct axidma_reg *)dma_addr; 632 /* RX channel offset is 0x30 */ 633 priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); 634 dev->init = axiemac_init; 635 dev->halt = axiemac_halt; 636 dev->send = axiemac_send; 637 dev->recv = axiemac_recv; 638 dev->write_hwaddr = axiemac_setup_mac; 639 640 #ifdef CONFIG_PHY_ADDR 641 priv->phyaddr = CONFIG_PHY_ADDR; 642 #else 643 priv->phyaddr = -1; 644 #endif 645 646 eth_register(dev); 647 648 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 649 miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); 650 priv->bus = miiphy_get_dev_by_name(dev->name); 651 priv->bus->reset = axiemac_bus_reset; 652 #endif 653 return 1; 654 } 655