1 /* 2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011 PetaLogix 4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <net.h> 13 #include <malloc.h> 14 #include <asm/io.h> 15 #include <phy.h> 16 #include <miiphy.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #if !defined(CONFIG_PHYLIB) 21 # error AXI_ETHERNET requires PHYLIB 22 #endif 23 24 /* Link setup */ 25 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 26 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 27 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 28 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 29 30 /* Interrupt Status/Enable/Mask Registers bit definitions */ 31 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 32 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 33 34 /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 35 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 36 37 /* Transmitter Configuration (TC) Register bit definitions */ 38 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 39 40 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 41 42 /* MDIO Management Configuration (MC) Register bit definitions */ 43 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 44 45 /* MDIO Management Control Register (MCR) Register bit definitions */ 46 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 47 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 48 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 49 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 50 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 51 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 52 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 53 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 54 55 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 56 57 /* DMA macros */ 58 /* Bitmasks of XAXIDMA_CR_OFFSET register */ 59 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 60 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 61 62 /* Bitmasks of XAXIDMA_SR_OFFSET register */ 63 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 64 65 /* Bitmask for interrupts */ 66 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 67 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 68 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 69 70 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 71 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 72 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 73 74 #define DMAALIGN 128 75 76 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 77 78 /* Reflect dma offsets */ 79 struct axidma_reg { 80 u32 control; /* DMACR */ 81 u32 status; /* DMASR */ 82 u32 current; /* CURDESC */ 83 u32 reserved; 84 u32 tail; /* TAILDESC */ 85 }; 86 87 /* Private driver structures */ 88 struct axidma_priv { 89 struct axidma_reg *dmatx; 90 struct axidma_reg *dmarx; 91 int phyaddr; 92 struct axi_regs *iobase; 93 phy_interface_t interface; 94 struct phy_device *phydev; 95 struct mii_dev *bus; 96 }; 97 98 /* BD descriptors */ 99 struct axidma_bd { 100 u32 next; /* Next descriptor pointer */ 101 u32 reserved1; 102 u32 phys; /* Buffer address */ 103 u32 reserved2; 104 u32 reserved3; 105 u32 reserved4; 106 u32 cntrl; /* Control */ 107 u32 status; /* Status */ 108 u32 app0; 109 u32 app1; /* TX start << 16 | insert */ 110 u32 app2; /* TX csum seed */ 111 u32 app3; 112 u32 app4; 113 u32 sw_id_offset; 114 u32 reserved5; 115 u32 reserved6; 116 }; 117 118 /* Static BDs - driver uses only one BD */ 119 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 120 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 121 122 struct axi_regs { 123 u32 reserved[3]; 124 u32 is; /* 0xC: Interrupt status */ 125 u32 reserved2; 126 u32 ie; /* 0x14: Interrupt enable */ 127 u32 reserved3[251]; 128 u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 129 u32 tc; /* 0x408: Tx Configuration */ 130 u32 reserved4; 131 u32 emmc; /* 0x410: EMAC mode configuration */ 132 u32 reserved5[59]; 133 u32 mdio_mc; /* 0x500: MII Management Config */ 134 u32 mdio_mcr; /* 0x504: MII Management Control */ 135 u32 mdio_mwd; /* 0x508: MII Management Write Data */ 136 u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 137 u32 reserved6[124]; 138 u32 uaw0; /* 0x700: Unicast address word 0 */ 139 u32 uaw1; /* 0x704: Unicast address word 1 */ 140 }; 141 142 /* Use MII register 1 (MII status register) to detect PHY */ 143 #define PHY_DETECT_REG 1 144 145 /* 146 * Mask used to verify certain PHY features (or register contents) 147 * in the register above: 148 * 0x1000: 10Mbps full duplex support 149 * 0x0800: 10Mbps half duplex support 150 * 0x0008: Auto-negotiation support 151 */ 152 #define PHY_DETECT_MASK 0x1808 153 154 static inline int mdio_wait(struct axi_regs *regs) 155 { 156 u32 timeout = 200; 157 158 /* Wait till MDIO interface is ready to accept a new transaction. */ 159 while (timeout && (!(in_be32(®s->mdio_mcr) 160 & XAE_MDIO_MCR_READY_MASK))) { 161 timeout--; 162 udelay(1); 163 } 164 if (!timeout) { 165 printf("%s: Timeout\n", __func__); 166 return 1; 167 } 168 return 0; 169 } 170 171 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 172 u16 *val) 173 { 174 struct axi_regs *regs = priv->iobase; 175 u32 mdioctrlreg = 0; 176 177 if (mdio_wait(regs)) 178 return 1; 179 180 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 181 XAE_MDIO_MCR_PHYAD_MASK) | 182 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 183 & XAE_MDIO_MCR_REGAD_MASK) | 184 XAE_MDIO_MCR_INITIATE_MASK | 185 XAE_MDIO_MCR_OP_READ_MASK; 186 187 out_be32(®s->mdio_mcr, mdioctrlreg); 188 189 if (mdio_wait(regs)) 190 return 1; 191 192 /* Read data */ 193 *val = in_be32(®s->mdio_mrd); 194 return 0; 195 } 196 197 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 198 u32 data) 199 { 200 struct axi_regs *regs = priv->iobase; 201 u32 mdioctrlreg = 0; 202 203 if (mdio_wait(regs)) 204 return 1; 205 206 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 207 XAE_MDIO_MCR_PHYAD_MASK) | 208 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 209 & XAE_MDIO_MCR_REGAD_MASK) | 210 XAE_MDIO_MCR_INITIATE_MASK | 211 XAE_MDIO_MCR_OP_WRITE_MASK; 212 213 /* Write data */ 214 out_be32(®s->mdio_mwd, data); 215 216 out_be32(®s->mdio_mcr, mdioctrlreg); 217 218 if (mdio_wait(regs)) 219 return 1; 220 221 return 0; 222 } 223 224 static int axiemac_phy_init(struct udevice *dev) 225 { 226 u16 phyreg; 227 u32 i, ret; 228 struct axidma_priv *priv = dev_get_priv(dev); 229 struct axi_regs *regs = priv->iobase; 230 struct phy_device *phydev; 231 232 u32 supported = SUPPORTED_10baseT_Half | 233 SUPPORTED_10baseT_Full | 234 SUPPORTED_100baseT_Half | 235 SUPPORTED_100baseT_Full | 236 SUPPORTED_1000baseT_Half | 237 SUPPORTED_1000baseT_Full; 238 239 /* Set default MDIO divisor */ 240 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 241 242 if (priv->phyaddr == -1) { 243 /* Detect the PHY address */ 244 for (i = 31; i >= 0; i--) { 245 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); 246 if (!ret && (phyreg != 0xFFFF) && 247 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 248 /* Found a valid PHY address */ 249 priv->phyaddr = i; 250 debug("axiemac: Found valid phy address, %x\n", 251 i); 252 break; 253 } 254 } 255 } 256 257 /* Interface - look at tsec */ 258 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); 259 260 phydev->supported &= supported; 261 phydev->advertising = phydev->supported; 262 priv->phydev = phydev; 263 phy_config(phydev); 264 265 return 0; 266 } 267 268 /* Setting axi emac and phy to proper setting */ 269 static int setup_phy(struct udevice *dev) 270 { 271 u32 speed, emmc_reg; 272 struct axidma_priv *priv = dev_get_priv(dev); 273 struct axi_regs *regs = priv->iobase; 274 struct phy_device *phydev = priv->phydev; 275 276 if (phy_startup(phydev)) { 277 printf("axiemac: could not initialize PHY %s\n", 278 phydev->dev->name); 279 return 0; 280 } 281 if (!phydev->link) { 282 printf("%s: No link.\n", phydev->dev->name); 283 return 0; 284 } 285 286 switch (phydev->speed) { 287 case 1000: 288 speed = XAE_EMMC_LINKSPD_1000; 289 break; 290 case 100: 291 speed = XAE_EMMC_LINKSPD_100; 292 break; 293 case 10: 294 speed = XAE_EMMC_LINKSPD_10; 295 break; 296 default: 297 return 0; 298 } 299 300 /* Setup the emac for the phy speed */ 301 emmc_reg = in_be32(®s->emmc); 302 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 303 emmc_reg |= speed; 304 305 /* Write new speed setting out to Axi Ethernet */ 306 out_be32(®s->emmc, emmc_reg); 307 308 /* 309 * Setting the operating speed of the MAC needs a delay. There 310 * doesn't seem to be register to poll, so please consider this 311 * during your application design. 312 */ 313 udelay(1); 314 315 return 1; 316 } 317 318 /* STOP DMA transfers */ 319 static void axiemac_halt(struct udevice *dev) 320 { 321 struct axidma_priv *priv = dev_get_priv(dev); 322 u32 temp; 323 324 /* Stop the hardware */ 325 temp = in_be32(&priv->dmatx->control); 326 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 327 out_be32(&priv->dmatx->control, temp); 328 329 temp = in_be32(&priv->dmarx->control); 330 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 331 out_be32(&priv->dmarx->control, temp); 332 333 debug("axiemac: Halted\n"); 334 } 335 336 static int axi_ethernet_init(struct axidma_priv *priv) 337 { 338 struct axi_regs *regs = priv->iobase; 339 u32 timeout = 200; 340 341 /* 342 * Check the status of the MgtRdy bit in the interrupt status 343 * registers. This must be done to allow the MGT clock to become stable 344 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 345 * will be valid until this bit is valid. 346 * The bit is always a 1 for all other PHY interfaces. 347 */ 348 while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) { 349 timeout--; 350 udelay(1); 351 } 352 if (!timeout) { 353 printf("%s: Timeout\n", __func__); 354 return 1; 355 } 356 357 /* Stop the device and reset HW */ 358 /* Disable interrupts */ 359 out_be32(®s->ie, 0); 360 361 /* Disable the receiver */ 362 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); 363 364 /* 365 * Stopping the receiver in mid-packet causes a dropped packet 366 * indication from HW. Clear it. 367 */ 368 /* Set the interrupt status register to clear the interrupt */ 369 out_be32(®s->is, XAE_INT_RXRJECT_MASK); 370 371 /* Setup HW */ 372 /* Set default MDIO divisor */ 373 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 374 375 debug("axiemac: InitHw done\n"); 376 return 0; 377 } 378 379 static int axiemac_setup_mac(struct udevice *dev) 380 { 381 struct eth_pdata *pdata = dev_get_platdata(dev); 382 struct axidma_priv *priv = dev_get_priv(dev); 383 struct axi_regs *regs = priv->iobase; 384 385 /* Set the MAC address */ 386 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | 387 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); 388 out_be32(®s->uaw0, val); 389 390 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; 391 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 392 out_be32(®s->uaw1, val); 393 return 0; 394 } 395 396 /* Reset DMA engine */ 397 static void axi_dma_init(struct axidma_priv *priv) 398 { 399 u32 timeout = 500; 400 401 /* Reset the engine so the hardware starts from a known state */ 402 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); 403 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); 404 405 /* At the initialization time, hardware should finish reset quickly */ 406 while (timeout--) { 407 /* Check transmit/receive channel */ 408 /* Reset is done when the reset bit is low */ 409 if (!((in_be32(&priv->dmatx->control) | 410 in_be32(&priv->dmarx->control)) 411 & XAXIDMA_CR_RESET_MASK)) { 412 break; 413 } 414 } 415 if (!timeout) 416 printf("%s: Timeout\n", __func__); 417 } 418 419 static int axiemac_init(struct udevice *dev) 420 { 421 struct axidma_priv *priv = dev_get_priv(dev); 422 struct axi_regs *regs = priv->iobase; 423 u32 temp; 424 425 debug("axiemac: Init started\n"); 426 /* 427 * Initialize AXIDMA engine. AXIDMA engine must be initialized before 428 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 429 * reset, and since AXIDMA reset line is connected to AxiEthernet, this 430 * would ensure a reset of AxiEthernet. 431 */ 432 axi_dma_init(priv); 433 434 /* Initialize AxiEthernet hardware. */ 435 if (axi_ethernet_init(priv)) 436 return -1; 437 438 /* Disable all RX interrupts before RxBD space setup */ 439 temp = in_be32(&priv->dmarx->control); 440 temp &= ~XAXIDMA_IRQ_ALL_MASK; 441 out_be32(&priv->dmarx->control, temp); 442 443 /* Start DMA RX channel. Now it's ready to receive data.*/ 444 out_be32(&priv->dmarx->current, (u32)&rx_bd); 445 446 /* Setup the BD. */ 447 memset(&rx_bd, 0, sizeof(rx_bd)); 448 rx_bd.next = (u32)&rx_bd; 449 rx_bd.phys = (u32)&rxframe; 450 rx_bd.cntrl = sizeof(rxframe); 451 /* Flush the last BD so DMA core could see the updates */ 452 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 453 454 /* It is necessary to flush rxframe because if you don't do it 455 * then cache can contain uninitialized data */ 456 flush_cache((u32)&rxframe, sizeof(rxframe)); 457 458 /* Start the hardware */ 459 temp = in_be32(&priv->dmarx->control); 460 temp |= XAXIDMA_CR_RUNSTOP_MASK; 461 out_be32(&priv->dmarx->control, temp); 462 463 /* Rx BD is ready - start */ 464 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 465 466 /* Enable TX */ 467 out_be32(®s->tc, XAE_TC_TX_MASK); 468 /* Enable RX */ 469 out_be32(®s->rcw1, XAE_RCW1_RX_MASK); 470 471 /* PHY setup */ 472 if (!setup_phy(dev)) { 473 axiemac_halt(dev); 474 return -1; 475 } 476 477 debug("axiemac: Init complete\n"); 478 return 0; 479 } 480 481 static int axiemac_send(struct udevice *dev, void *ptr, int len) 482 { 483 struct axidma_priv *priv = dev_get_priv(dev); 484 u32 timeout; 485 486 if (len > PKTSIZE_ALIGN) 487 len = PKTSIZE_ALIGN; 488 489 /* Flush packet to main memory to be trasfered by DMA */ 490 flush_cache((u32)ptr, len); 491 492 /* Setup Tx BD */ 493 memset(&tx_bd, 0, sizeof(tx_bd)); 494 /* At the end of the ring, link the last BD back to the top */ 495 tx_bd.next = (u32)&tx_bd; 496 tx_bd.phys = (u32)ptr; 497 /* Save len */ 498 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 499 XAXIDMA_BD_CTRL_TXEOF_MASK; 500 501 /* Flush the last BD so DMA core could see the updates */ 502 flush_cache((u32)&tx_bd, sizeof(tx_bd)); 503 504 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 505 u32 temp; 506 out_be32(&priv->dmatx->current, (u32)&tx_bd); 507 /* Start the hardware */ 508 temp = in_be32(&priv->dmatx->control); 509 temp |= XAXIDMA_CR_RUNSTOP_MASK; 510 out_be32(&priv->dmatx->control, temp); 511 } 512 513 /* Start transfer */ 514 out_be32(&priv->dmatx->tail, (u32)&tx_bd); 515 516 /* Wait for transmission to complete */ 517 debug("axiemac: Waiting for tx to be done\n"); 518 timeout = 200; 519 while (timeout && (!(in_be32(&priv->dmatx->status) & 520 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { 521 timeout--; 522 udelay(1); 523 } 524 if (!timeout) { 525 printf("%s: Timeout\n", __func__); 526 return 1; 527 } 528 529 debug("axiemac: Sending complete\n"); 530 return 0; 531 } 532 533 static int isrxready(struct axidma_priv *priv) 534 { 535 u32 status; 536 537 /* Read pending interrupts */ 538 status = in_be32(&priv->dmarx->status); 539 540 /* Acknowledge pending interrupts */ 541 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); 542 543 /* 544 * If Reception done interrupt is asserted, call RX call back function 545 * to handle the processed BDs and then raise the according flag. 546 */ 547 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 548 return 1; 549 550 return 0; 551 } 552 553 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) 554 { 555 u32 length; 556 struct axidma_priv *priv = dev_get_priv(dev); 557 u32 temp; 558 559 /* Wait for an incoming packet */ 560 if (!isrxready(priv)) 561 return -1; 562 563 debug("axiemac: RX data ready\n"); 564 565 /* Disable IRQ for a moment till packet is handled */ 566 temp = in_be32(&priv->dmarx->control); 567 temp &= ~XAXIDMA_IRQ_ALL_MASK; 568 out_be32(&priv->dmarx->control, temp); 569 570 length = rx_bd.app4 & 0xFFFF; /* max length mask */ 571 #ifdef DEBUG 572 print_buffer(&rxframe, &rxframe[0], 1, length, 16); 573 #endif 574 575 *packetp = rxframe; 576 return length; 577 } 578 579 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) 580 { 581 struct axidma_priv *priv = dev_get_priv(dev); 582 583 #ifdef DEBUG 584 /* It is useful to clear buffer to be sure that it is consistent */ 585 memset(rxframe, 0, sizeof(rxframe)); 586 #endif 587 /* Setup RxBD */ 588 /* Clear the whole buffer and setup it again - all flags are cleared */ 589 memset(&rx_bd, 0, sizeof(rx_bd)); 590 rx_bd.next = (u32)&rx_bd; 591 rx_bd.phys = (u32)&rxframe; 592 rx_bd.cntrl = sizeof(rxframe); 593 594 /* Write bd to HW */ 595 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 596 597 /* It is necessary to flush rxframe because if you don't do it 598 * then cache will contain previous packet */ 599 flush_cache((u32)&rxframe, sizeof(rxframe)); 600 601 /* Rx BD is ready - start again */ 602 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 603 604 debug("axiemac: RX completed, framelength = %d\n", length); 605 606 return 0; 607 } 608 609 static int axiemac_miiphy_read(struct mii_dev *bus, int addr, 610 int devad, int reg) 611 { 612 int ret; 613 u16 value; 614 615 ret = phyread(bus->priv, addr, reg, &value); 616 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, 617 value, ret); 618 return value; 619 } 620 621 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, 622 int reg, u16 value) 623 { 624 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 625 return phywrite(bus->priv, addr, reg, value); 626 } 627 628 static int axi_emac_probe(struct udevice *dev) 629 { 630 struct axidma_priv *priv = dev_get_priv(dev); 631 int ret; 632 633 priv->bus = mdio_alloc(); 634 priv->bus->read = axiemac_miiphy_read; 635 priv->bus->write = axiemac_miiphy_write; 636 priv->bus->priv = priv; 637 strcpy(priv->bus->name, "axi_emac"); 638 639 ret = mdio_register(priv->bus); 640 if (ret) 641 return ret; 642 643 axiemac_phy_init(dev); 644 645 return 0; 646 } 647 648 static int axi_emac_remove(struct udevice *dev) 649 { 650 struct axidma_priv *priv = dev_get_priv(dev); 651 652 free(priv->phydev); 653 mdio_unregister(priv->bus); 654 mdio_free(priv->bus); 655 656 return 0; 657 } 658 659 static const struct eth_ops axi_emac_ops = { 660 .start = axiemac_init, 661 .send = axiemac_send, 662 .recv = axiemac_recv, 663 .free_pkt = axiemac_free_pkt, 664 .stop = axiemac_halt, 665 .write_hwaddr = axiemac_setup_mac, 666 }; 667 668 static int axi_emac_ofdata_to_platdata(struct udevice *dev) 669 { 670 struct eth_pdata *pdata = dev_get_platdata(dev); 671 struct axidma_priv *priv = dev_get_priv(dev); 672 int offset = 0; 673 const char *phy_mode; 674 675 pdata->iobase = (phys_addr_t)dev_get_addr(dev); 676 priv->iobase = (struct axi_regs *)pdata->iobase; 677 678 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 679 "axistream-connected"); 680 if (offset <= 0) { 681 printf("%s: axistream is not found\n", __func__); 682 return -EINVAL; 683 } 684 priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, 685 offset, "reg", 0); 686 if (!priv->dmatx) { 687 printf("%s: axi_dma register space not found\n", __func__); 688 return -EINVAL; 689 } 690 /* RX channel offset is 0x30 */ 691 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); 692 693 priv->phyaddr = -1; 694 695 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 696 "phy-handle"); 697 if (offset > 0) 698 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 699 700 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 701 if (phy_mode) 702 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 703 if (pdata->phy_interface == -1) { 704 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 705 return -EINVAL; 706 } 707 priv->interface = pdata->phy_interface; 708 709 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 710 priv->phyaddr, phy_string_for_interface(priv->interface)); 711 712 return 0; 713 } 714 715 static const struct udevice_id axi_emac_ids[] = { 716 { .compatible = "xlnx,axi-ethernet-1.00.a" }, 717 { } 718 }; 719 720 U_BOOT_DRIVER(axi_emac) = { 721 .name = "axi_emac", 722 .id = UCLASS_ETH, 723 .of_match = axi_emac_ids, 724 .ofdata_to_platdata = axi_emac_ofdata_to_platdata, 725 .probe = axi_emac_probe, 726 .remove = axi_emac_remove, 727 .ops = &axi_emac_ops, 728 .priv_auto_alloc_size = sizeof(struct axidma_priv), 729 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 730 }; 731