1 /* 2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2011 PetaLogix 4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <net.h> 13 #include <malloc.h> 14 #include <asm/io.h> 15 #include <phy.h> 16 #include <miiphy.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* Link setup */ 21 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ 22 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ 23 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ 24 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ 25 26 /* Interrupt Status/Enable/Mask Registers bit definitions */ 27 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ 28 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ 29 30 /* Receive Configuration Word 1 (RCW1) Register bit definitions */ 31 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ 32 33 /* Transmitter Configuration (TC) Register bit definitions */ 34 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ 35 36 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF 37 38 /* MDIO Management Configuration (MC) Register bit definitions */ 39 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ 40 41 /* MDIO Management Control Register (MCR) Register bit definitions */ 42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ 43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ 44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ 45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ 46 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ 47 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ 48 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ 49 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ 50 51 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ 52 53 /* DMA macros */ 54 /* Bitmasks of XAXIDMA_CR_OFFSET register */ 55 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ 56 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ 57 58 /* Bitmasks of XAXIDMA_SR_OFFSET register */ 59 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ 60 61 /* Bitmask for interrupts */ 62 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ 63 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ 64 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ 65 66 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ 67 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ 68 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ 69 70 #define DMAALIGN 128 71 72 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); 73 74 /* Reflect dma offsets */ 75 struct axidma_reg { 76 u32 control; /* DMACR */ 77 u32 status; /* DMASR */ 78 u32 current; /* CURDESC */ 79 u32 reserved; 80 u32 tail; /* TAILDESC */ 81 }; 82 83 /* Private driver structures */ 84 struct axidma_priv { 85 struct axidma_reg *dmatx; 86 struct axidma_reg *dmarx; 87 int phyaddr; 88 struct axi_regs *iobase; 89 phy_interface_t interface; 90 struct phy_device *phydev; 91 struct mii_dev *bus; 92 }; 93 94 /* BD descriptors */ 95 struct axidma_bd { 96 u32 next; /* Next descriptor pointer */ 97 u32 reserved1; 98 u32 phys; /* Buffer address */ 99 u32 reserved2; 100 u32 reserved3; 101 u32 reserved4; 102 u32 cntrl; /* Control */ 103 u32 status; /* Status */ 104 u32 app0; 105 u32 app1; /* TX start << 16 | insert */ 106 u32 app2; /* TX csum seed */ 107 u32 app3; 108 u32 app4; 109 u32 sw_id_offset; 110 u32 reserved5; 111 u32 reserved6; 112 }; 113 114 /* Static BDs - driver uses only one BD */ 115 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); 116 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); 117 118 struct axi_regs { 119 u32 reserved[3]; 120 u32 is; /* 0xC: Interrupt status */ 121 u32 reserved2; 122 u32 ie; /* 0x14: Interrupt enable */ 123 u32 reserved3[251]; 124 u32 rcw1; /* 0x404: Rx Configuration Word 1 */ 125 u32 tc; /* 0x408: Tx Configuration */ 126 u32 reserved4; 127 u32 emmc; /* 0x410: EMAC mode configuration */ 128 u32 reserved5[59]; 129 u32 mdio_mc; /* 0x500: MII Management Config */ 130 u32 mdio_mcr; /* 0x504: MII Management Control */ 131 u32 mdio_mwd; /* 0x508: MII Management Write Data */ 132 u32 mdio_mrd; /* 0x50C: MII Management Read Data */ 133 u32 reserved6[124]; 134 u32 uaw0; /* 0x700: Unicast address word 0 */ 135 u32 uaw1; /* 0x704: Unicast address word 1 */ 136 }; 137 138 /* Use MII register 1 (MII status register) to detect PHY */ 139 #define PHY_DETECT_REG 1 140 141 /* 142 * Mask used to verify certain PHY features (or register contents) 143 * in the register above: 144 * 0x1000: 10Mbps full duplex support 145 * 0x0800: 10Mbps half duplex support 146 * 0x0008: Auto-negotiation support 147 */ 148 #define PHY_DETECT_MASK 0x1808 149 150 static inline int mdio_wait(struct axi_regs *regs) 151 { 152 u32 timeout = 200; 153 154 /* Wait till MDIO interface is ready to accept a new transaction. */ 155 while (timeout && (!(in_be32(®s->mdio_mcr) 156 & XAE_MDIO_MCR_READY_MASK))) { 157 timeout--; 158 udelay(1); 159 } 160 if (!timeout) { 161 printf("%s: Timeout\n", __func__); 162 return 1; 163 } 164 return 0; 165 } 166 167 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 168 u16 *val) 169 { 170 struct axi_regs *regs = priv->iobase; 171 u32 mdioctrlreg = 0; 172 173 if (mdio_wait(regs)) 174 return 1; 175 176 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 177 XAE_MDIO_MCR_PHYAD_MASK) | 178 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 179 & XAE_MDIO_MCR_REGAD_MASK) | 180 XAE_MDIO_MCR_INITIATE_MASK | 181 XAE_MDIO_MCR_OP_READ_MASK; 182 183 out_be32(®s->mdio_mcr, mdioctrlreg); 184 185 if (mdio_wait(regs)) 186 return 1; 187 188 /* Read data */ 189 *val = in_be32(®s->mdio_mrd); 190 return 0; 191 } 192 193 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, 194 u32 data) 195 { 196 struct axi_regs *regs = priv->iobase; 197 u32 mdioctrlreg = 0; 198 199 if (mdio_wait(regs)) 200 return 1; 201 202 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & 203 XAE_MDIO_MCR_PHYAD_MASK) | 204 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT) 205 & XAE_MDIO_MCR_REGAD_MASK) | 206 XAE_MDIO_MCR_INITIATE_MASK | 207 XAE_MDIO_MCR_OP_WRITE_MASK; 208 209 /* Write data */ 210 out_be32(®s->mdio_mwd, data); 211 212 out_be32(®s->mdio_mcr, mdioctrlreg); 213 214 if (mdio_wait(regs)) 215 return 1; 216 217 return 0; 218 } 219 220 static int axiemac_phy_init(struct udevice *dev) 221 { 222 u16 phyreg; 223 u32 i, ret; 224 struct axidma_priv *priv = dev_get_priv(dev); 225 struct axi_regs *regs = priv->iobase; 226 struct phy_device *phydev; 227 228 u32 supported = SUPPORTED_10baseT_Half | 229 SUPPORTED_10baseT_Full | 230 SUPPORTED_100baseT_Half | 231 SUPPORTED_100baseT_Full | 232 SUPPORTED_1000baseT_Half | 233 SUPPORTED_1000baseT_Full; 234 235 /* Set default MDIO divisor */ 236 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 237 238 if (priv->phyaddr == -1) { 239 /* Detect the PHY address */ 240 for (i = 31; i >= 0; i--) { 241 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); 242 if (!ret && (phyreg != 0xFFFF) && 243 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { 244 /* Found a valid PHY address */ 245 priv->phyaddr = i; 246 debug("axiemac: Found valid phy address, %x\n", 247 i); 248 break; 249 } 250 } 251 } 252 253 /* Interface - look at tsec */ 254 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 255 256 phydev->supported &= supported; 257 phydev->advertising = phydev->supported; 258 priv->phydev = phydev; 259 phy_config(phydev); 260 261 return 0; 262 } 263 264 /* Setting axi emac and phy to proper setting */ 265 static int setup_phy(struct udevice *dev) 266 { 267 u16 temp; 268 u32 speed, emmc_reg, ret; 269 struct axidma_priv *priv = dev_get_priv(dev); 270 struct axi_regs *regs = priv->iobase; 271 struct phy_device *phydev = priv->phydev; 272 273 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { 274 /* 275 * In SGMII cases the isolate bit might set 276 * after DMA and ethernet resets and hence 277 * check and clear if set. 278 */ 279 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); 280 if (ret) 281 return 0; 282 if (temp & BMCR_ISOLATE) { 283 temp &= ~BMCR_ISOLATE; 284 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); 285 if (ret) 286 return 0; 287 } 288 } 289 290 if (phy_startup(phydev)) { 291 printf("axiemac: could not initialize PHY %s\n", 292 phydev->dev->name); 293 return 0; 294 } 295 if (!phydev->link) { 296 printf("%s: No link.\n", phydev->dev->name); 297 return 0; 298 } 299 300 switch (phydev->speed) { 301 case 1000: 302 speed = XAE_EMMC_LINKSPD_1000; 303 break; 304 case 100: 305 speed = XAE_EMMC_LINKSPD_100; 306 break; 307 case 10: 308 speed = XAE_EMMC_LINKSPD_10; 309 break; 310 default: 311 return 0; 312 } 313 314 /* Setup the emac for the phy speed */ 315 emmc_reg = in_be32(®s->emmc); 316 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; 317 emmc_reg |= speed; 318 319 /* Write new speed setting out to Axi Ethernet */ 320 out_be32(®s->emmc, emmc_reg); 321 322 /* 323 * Setting the operating speed of the MAC needs a delay. There 324 * doesn't seem to be register to poll, so please consider this 325 * during your application design. 326 */ 327 udelay(1); 328 329 return 1; 330 } 331 332 /* STOP DMA transfers */ 333 static void axiemac_stop(struct udevice *dev) 334 { 335 struct axidma_priv *priv = dev_get_priv(dev); 336 u32 temp; 337 338 /* Stop the hardware */ 339 temp = in_be32(&priv->dmatx->control); 340 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 341 out_be32(&priv->dmatx->control, temp); 342 343 temp = in_be32(&priv->dmarx->control); 344 temp &= ~XAXIDMA_CR_RUNSTOP_MASK; 345 out_be32(&priv->dmarx->control, temp); 346 347 debug("axiemac: Halted\n"); 348 } 349 350 static int axi_ethernet_init(struct axidma_priv *priv) 351 { 352 struct axi_regs *regs = priv->iobase; 353 u32 timeout = 200; 354 355 /* 356 * Check the status of the MgtRdy bit in the interrupt status 357 * registers. This must be done to allow the MGT clock to become stable 358 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads 359 * will be valid until this bit is valid. 360 * The bit is always a 1 for all other PHY interfaces. 361 */ 362 if (!priv->eth_hasnobuf) { 363 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK, 364 true, 200, false); 365 if (err) { 366 printf("%s: Timeout\n", __func__); 367 return 1; 368 } 369 370 /* 371 * Stop the device and reset HW 372 * Disable interrupts 373 */ 374 writel(0, ®s->ie); 375 } 376 377 /* Stop the device and reset HW */ 378 /* Disable interrupts */ 379 out_be32(®s->ie, 0); 380 381 /* Disable the receiver */ 382 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK); 383 384 /* 385 * Stopping the receiver in mid-packet causes a dropped packet 386 * indication from HW. Clear it. 387 */ 388 /* Set the interrupt status register to clear the interrupt */ 389 out_be32(®s->is, XAE_INT_RXRJECT_MASK); 390 391 /* Setup HW */ 392 /* Set default MDIO divisor */ 393 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); 394 395 debug("axiemac: InitHw done\n"); 396 return 0; 397 } 398 399 static int axiemac_write_hwaddr(struct udevice *dev) 400 { 401 struct eth_pdata *pdata = dev_get_platdata(dev); 402 struct axidma_priv *priv = dev_get_priv(dev); 403 struct axi_regs *regs = priv->iobase; 404 405 /* Set the MAC address */ 406 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | 407 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); 408 out_be32(®s->uaw0, val); 409 410 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; 411 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; 412 out_be32(®s->uaw1, val); 413 return 0; 414 } 415 416 /* Reset DMA engine */ 417 static void axi_dma_init(struct axidma_priv *priv) 418 { 419 u32 timeout = 500; 420 421 /* Reset the engine so the hardware starts from a known state */ 422 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); 423 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); 424 425 /* At the initialization time, hardware should finish reset quickly */ 426 while (timeout--) { 427 /* Check transmit/receive channel */ 428 /* Reset is done when the reset bit is low */ 429 if (!((in_be32(&priv->dmatx->control) | 430 in_be32(&priv->dmarx->control)) 431 & XAXIDMA_CR_RESET_MASK)) { 432 break; 433 } 434 } 435 if (!timeout) 436 printf("%s: Timeout\n", __func__); 437 } 438 439 static int axiemac_start(struct udevice *dev) 440 { 441 struct axidma_priv *priv = dev_get_priv(dev); 442 struct axi_regs *regs = priv->iobase; 443 u32 temp; 444 445 debug("axiemac: Init started\n"); 446 /* 447 * Initialize AXIDMA engine. AXIDMA engine must be initialized before 448 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is 449 * reset, and since AXIDMA reset line is connected to AxiEthernet, this 450 * would ensure a reset of AxiEthernet. 451 */ 452 axi_dma_init(priv); 453 454 /* Initialize AxiEthernet hardware. */ 455 if (axi_ethernet_init(priv)) 456 return -1; 457 458 /* Disable all RX interrupts before RxBD space setup */ 459 temp = in_be32(&priv->dmarx->control); 460 temp &= ~XAXIDMA_IRQ_ALL_MASK; 461 out_be32(&priv->dmarx->control, temp); 462 463 /* Start DMA RX channel. Now it's ready to receive data.*/ 464 out_be32(&priv->dmarx->current, (u32)&rx_bd); 465 466 /* Setup the BD. */ 467 memset(&rx_bd, 0, sizeof(rx_bd)); 468 rx_bd.next = (u32)&rx_bd; 469 rx_bd.phys = (u32)&rxframe; 470 rx_bd.cntrl = sizeof(rxframe); 471 /* Flush the last BD so DMA core could see the updates */ 472 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 473 474 /* It is necessary to flush rxframe because if you don't do it 475 * then cache can contain uninitialized data */ 476 flush_cache((u32)&rxframe, sizeof(rxframe)); 477 478 /* Start the hardware */ 479 temp = in_be32(&priv->dmarx->control); 480 temp |= XAXIDMA_CR_RUNSTOP_MASK; 481 out_be32(&priv->dmarx->control, temp); 482 483 /* Rx BD is ready - start */ 484 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 485 486 /* Enable TX */ 487 out_be32(®s->tc, XAE_TC_TX_MASK); 488 /* Enable RX */ 489 out_be32(®s->rcw1, XAE_RCW1_RX_MASK); 490 491 /* PHY setup */ 492 if (!setup_phy(dev)) { 493 axiemac_stop(dev); 494 return -1; 495 } 496 497 debug("axiemac: Init complete\n"); 498 return 0; 499 } 500 501 static int axiemac_send(struct udevice *dev, void *ptr, int len) 502 { 503 struct axidma_priv *priv = dev_get_priv(dev); 504 u32 timeout; 505 506 if (len > PKTSIZE_ALIGN) 507 len = PKTSIZE_ALIGN; 508 509 /* Flush packet to main memory to be trasfered by DMA */ 510 flush_cache((u32)ptr, len); 511 512 /* Setup Tx BD */ 513 memset(&tx_bd, 0, sizeof(tx_bd)); 514 /* At the end of the ring, link the last BD back to the top */ 515 tx_bd.next = (u32)&tx_bd; 516 tx_bd.phys = (u32)ptr; 517 /* Save len */ 518 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | 519 XAXIDMA_BD_CTRL_TXEOF_MASK; 520 521 /* Flush the last BD so DMA core could see the updates */ 522 flush_cache((u32)&tx_bd, sizeof(tx_bd)); 523 524 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { 525 u32 temp; 526 out_be32(&priv->dmatx->current, (u32)&tx_bd); 527 /* Start the hardware */ 528 temp = in_be32(&priv->dmatx->control); 529 temp |= XAXIDMA_CR_RUNSTOP_MASK; 530 out_be32(&priv->dmatx->control, temp); 531 } 532 533 /* Start transfer */ 534 out_be32(&priv->dmatx->tail, (u32)&tx_bd); 535 536 /* Wait for transmission to complete */ 537 debug("axiemac: Waiting for tx to be done\n"); 538 timeout = 200; 539 while (timeout && (!(in_be32(&priv->dmatx->status) & 540 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { 541 timeout--; 542 udelay(1); 543 } 544 if (!timeout) { 545 printf("%s: Timeout\n", __func__); 546 return 1; 547 } 548 549 debug("axiemac: Sending complete\n"); 550 return 0; 551 } 552 553 static int isrxready(struct axidma_priv *priv) 554 { 555 u32 status; 556 557 /* Read pending interrupts */ 558 status = in_be32(&priv->dmarx->status); 559 560 /* Acknowledge pending interrupts */ 561 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK); 562 563 /* 564 * If Reception done interrupt is asserted, call RX call back function 565 * to handle the processed BDs and then raise the according flag. 566 */ 567 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) 568 return 1; 569 570 return 0; 571 } 572 573 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) 574 { 575 u32 length; 576 struct axidma_priv *priv = dev_get_priv(dev); 577 u32 temp; 578 579 /* Wait for an incoming packet */ 580 if (!isrxready(priv)) 581 return -1; 582 583 debug("axiemac: RX data ready\n"); 584 585 /* Disable IRQ for a moment till packet is handled */ 586 temp = in_be32(&priv->dmarx->control); 587 temp &= ~XAXIDMA_IRQ_ALL_MASK; 588 out_be32(&priv->dmarx->control, temp); 589 590 length = rx_bd.app4 & 0xFFFF; /* max length mask */ 591 #ifdef DEBUG 592 print_buffer(&rxframe, &rxframe[0], 1, length, 16); 593 #endif 594 595 *packetp = rxframe; 596 return length; 597 } 598 599 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) 600 { 601 struct axidma_priv *priv = dev_get_priv(dev); 602 603 #ifdef DEBUG 604 /* It is useful to clear buffer to be sure that it is consistent */ 605 memset(rxframe, 0, sizeof(rxframe)); 606 #endif 607 /* Setup RxBD */ 608 /* Clear the whole buffer and setup it again - all flags are cleared */ 609 memset(&rx_bd, 0, sizeof(rx_bd)); 610 rx_bd.next = (u32)&rx_bd; 611 rx_bd.phys = (u32)&rxframe; 612 rx_bd.cntrl = sizeof(rxframe); 613 614 /* Write bd to HW */ 615 flush_cache((u32)&rx_bd, sizeof(rx_bd)); 616 617 /* It is necessary to flush rxframe because if you don't do it 618 * then cache will contain previous packet */ 619 flush_cache((u32)&rxframe, sizeof(rxframe)); 620 621 /* Rx BD is ready - start again */ 622 out_be32(&priv->dmarx->tail, (u32)&rx_bd); 623 624 debug("axiemac: RX completed, framelength = %d\n", length); 625 626 return 0; 627 } 628 629 static int axiemac_miiphy_read(struct mii_dev *bus, int addr, 630 int devad, int reg) 631 { 632 int ret; 633 u16 value; 634 635 ret = phyread(bus->priv, addr, reg, &value); 636 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, 637 value, ret); 638 return value; 639 } 640 641 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, 642 int reg, u16 value) 643 { 644 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); 645 return phywrite(bus->priv, addr, reg, value); 646 } 647 648 static int axi_emac_probe(struct udevice *dev) 649 { 650 struct axidma_priv *priv = dev_get_priv(dev); 651 int ret; 652 653 priv->bus = mdio_alloc(); 654 priv->bus->read = axiemac_miiphy_read; 655 priv->bus->write = axiemac_miiphy_write; 656 priv->bus->priv = priv; 657 658 ret = mdio_register_seq(priv->bus, dev->seq); 659 if (ret) 660 return ret; 661 662 axiemac_phy_init(dev); 663 664 return 0; 665 } 666 667 static int axi_emac_remove(struct udevice *dev) 668 { 669 struct axidma_priv *priv = dev_get_priv(dev); 670 671 free(priv->phydev); 672 mdio_unregister(priv->bus); 673 mdio_free(priv->bus); 674 675 return 0; 676 } 677 678 static const struct eth_ops axi_emac_ops = { 679 .start = axiemac_start, 680 .send = axiemac_send, 681 .recv = axiemac_recv, 682 .free_pkt = axiemac_free_pkt, 683 .stop = axiemac_stop, 684 .write_hwaddr = axiemac_write_hwaddr, 685 }; 686 687 static int axi_emac_ofdata_to_platdata(struct udevice *dev) 688 { 689 struct eth_pdata *pdata = dev_get_platdata(dev); 690 struct axidma_priv *priv = dev_get_priv(dev); 691 int node = dev_of_offset(dev); 692 int offset = 0; 693 const char *phy_mode; 694 695 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); 696 priv->iobase = (struct axi_regs *)pdata->iobase; 697 698 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, 699 "axistream-connected"); 700 if (offset <= 0) { 701 printf("%s: axistream is not found\n", __func__); 702 return -EINVAL; 703 } 704 priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, 705 offset, "reg", 0); 706 if (!priv->dmatx) { 707 printf("%s: axi_dma register space not found\n", __func__); 708 return -EINVAL; 709 } 710 /* RX channel offset is 0x30 */ 711 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); 712 713 priv->phyaddr = -1; 714 715 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); 716 if (offset > 0) 717 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); 718 719 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); 720 if (phy_mode) 721 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 722 if (pdata->phy_interface == -1) { 723 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 724 return -EINVAL; 725 } 726 priv->interface = pdata->phy_interface; 727 728 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, 729 priv->phyaddr, phy_string_for_interface(priv->interface)); 730 731 return 0; 732 } 733 734 static const struct udevice_id axi_emac_ids[] = { 735 { .compatible = "xlnx,axi-ethernet-1.00.a" }, 736 { } 737 }; 738 739 U_BOOT_DRIVER(axi_emac) = { 740 .name = "axi_emac", 741 .id = UCLASS_ETH, 742 .of_match = axi_emac_ids, 743 .ofdata_to_platdata = axi_emac_ofdata_to_platdata, 744 .probe = axi_emac_probe, 745 .remove = axi_emac_remove, 746 .ops = &axi_emac_ops, 747 .priv_auto_alloc_size = sizeof(struct axidma_priv), 748 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 749 }; 750