1 /*********************************************************************** 2 * 3 * Copyright (c) 2005 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * Description: 24 * Ethernet interface for Tundra TSI108 bridge chip 25 * 26 ***********************************************************************/ 27 28 #include <config.h> 29 30 #if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) 31 #error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" 32 #endif 33 34 #include <common.h> 35 #include <malloc.h> 36 #include <net.h> 37 #include <asm/cache.h> 38 39 #ifdef DEBUG 40 #define TSI108_ETH_DEBUG 7 41 #else 42 #define TSI108_ETH_DEBUG 0 43 #endif 44 45 #if TSI108_ETH_DEBUG > 0 46 #define debug_lev(lev, fmt, args...) \ 47 if (lev <= TSI108_ETH_DEBUG) \ 48 printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) 49 #else 50 #define debug_lev(lev, fmt, args...) do{}while(0) 51 #endif 52 53 #define RX_PRINT_ERRORS 54 #define TX_PRINT_ERRORS 55 56 #define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000) 57 58 #define ETH_PORT_OFFSET 0x400 59 60 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) 61 62 #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) 63 #define MAC_CONFIG_1_TX_ENABLE (0x00000001) 64 #define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) 65 #define MAC_CONFIG_1_RX_ENABLE (0x00000004) 66 #define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) 67 #define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) 68 #define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) 69 #define MAC_CONFIG_1_LOOP_BACK (0x00000100) 70 #define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) 71 #define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) 72 #define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) 73 #define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) 74 #define MAC_CONFIG_1_SIM_RESET (0x40000000) 75 #define MAC_CONFIG_1_SOFT_RESET (0x80000000) 76 77 #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) 78 #define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) 79 #define MAC_CONFIG_2_CRC_ENABLE (0x00000002) 80 #define MAC_CONFIG_2_PAD_CRC (0x00000004) 81 #define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) 82 #define MAC_CONFIG_2_HUGE_FRAME (0x00000020) 83 #define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) 84 #define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) 85 #define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ 86 #define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ 87 88 #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) 89 90 #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) 91 #define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) 92 #define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) 93 #define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) 94 #define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) 95 96 #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) 97 #define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) 98 #define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) 99 100 #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) 101 #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) 102 #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) 103 104 #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) 105 #define MII_MGMT_INDICATORS_BUSY (0x00000001) 106 #define MII_MGMT_INDICATORS_SCAN (0x00000002) 107 #define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) 108 109 #define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) 110 #define INTERFACE_STATUS_LINK_FAIL (0x00000008) 111 #define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) 112 113 #define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) 114 #define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) 115 116 #define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) 117 #define PORT_CONTROL_PRI (0x00000001) 118 #define PORT_CONTROL_BPT (0x00010000) 119 #define PORT_CONTROL_SPD (0x00040000) 120 #define PORT_CONTROL_RBC (0x00080000) 121 #define PORT_CONTROL_PRB (0x00200000) 122 #define PORT_CONTROL_DIS (0x00400000) 123 #define PORT_CONTROL_TBI (0x00800000) 124 #define PORT_CONTROL_STE (0x10000000) 125 #define PORT_CONTROL_ZOR (0x20000000) 126 #define PORT_CONTROL_CLR (0x40000000) 127 #define PORT_CONTROL_SRT (0x80000000) 128 129 #define reg_TX_CONFIG(base) __REG32(base, 0x00000220) 130 #define TX_CONFIG_START_Q (0x00000003) 131 #define TX_CONFIG_EHP (0x00400000) 132 #define TX_CONFIG_CHP (0x00800000) 133 #define TX_CONFIG_RST (0x80000000) 134 135 #define reg_TX_CONTROL(base) __REG32(base, 0x00000224) 136 #define TX_CONTROL_GO (0x00008000) 137 #define TX_CONTROL_MP (0x01000000) 138 #define TX_CONTROL_EAI (0x20000000) 139 #define TX_CONTROL_ABT (0x40000000) 140 #define TX_CONTROL_EII (0x80000000) 141 142 #define reg_TX_STATUS(base) __REG32(base, 0x00000228) 143 #define TX_STATUS_QUEUE_USABLE (0x0000000f) 144 #define TX_STATUS_CURR_Q (0x00000300) 145 #define TX_STATUS_ACT (0x00008000) 146 #define TX_STATUS_QUEUE_IDLE (0x000f0000) 147 #define TX_STATUS_EOQ_PENDING (0x0f000000) 148 149 #define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) 150 #define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) 151 #define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) 152 #define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) 153 #define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) 154 155 #define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) 156 157 #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) 158 #define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) 159 #define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) 160 #define TX_DIAGNOSTIC_ADDR_AI (0x80000000) 161 162 #define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) 163 164 #define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) 165 #define TX_ERROR_STATUS (0x00000278) 166 #define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) 167 #define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) 168 #define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) 169 #define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) 170 #define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) 171 #define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) 172 #define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) 173 #define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) 174 #define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) 175 #define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) 176 #define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) 177 #define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) 178 #define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) 179 #define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) 180 #define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) 181 #define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) 182 #define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) 183 #define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) 184 #define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) 185 #define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) 186 187 #define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) 188 #define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) 189 #define TX_QUEUE_0_CONFIG_BSWP (0x00000400) 190 #define TX_QUEUE_0_CONFIG_WSWP (0x00000800) 191 #define TX_QUEUE_0_CONFIG_AM (0x00004000) 192 #define TX_QUEUE_0_CONFIG_GVI (0x00008000) 193 #define TX_QUEUE_0_CONFIG_EEI (0x00010000) 194 #define TX_QUEUE_0_CONFIG_ELI (0x00020000) 195 #define TX_QUEUE_0_CONFIG_ENI (0x00040000) 196 #define TX_QUEUE_0_CONFIG_ESI (0x00080000) 197 #define TX_QUEUE_0_CONFIG_EDI (0x00100000) 198 199 #define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) 200 #define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) 201 #define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) 202 #define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) 203 #define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) 204 205 #define OCN_PORT_HLP 0 /* HLP Interface */ 206 #define OCN_PORT_PCI_X 1 /* PCI-X Interface */ 207 #define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ 208 #define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ 209 #define OCN_PORT_MEMORY 4 /* Memory Controller */ 210 #define OCN_PORT_DMA 5 /* DMA Controller */ 211 #define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ 212 #define OCN_PORT_PRINT 7 /* Print Engine Interface */ 213 214 #define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) 215 216 #define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) 217 #define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) 218 219 #define reg_RX_CONFIG(base) __REG32(base, 0x00000320) 220 #define RX_CONFIG_DEF_Q (0x00000003) 221 #define RX_CONFIG_EMF (0x00000100) 222 #define RX_CONFIG_EUF (0x00000200) 223 #define RX_CONFIG_BFE (0x00000400) 224 #define RX_CONFIG_MFE (0x00000800) 225 #define RX_CONFIG_UFE (0x00001000) 226 #define RX_CONFIG_SE (0x00002000) 227 #define RX_CONFIG_ABF (0x00200000) 228 #define RX_CONFIG_APE (0x00400000) 229 #define RX_CONFIG_CHP (0x00800000) 230 #define RX_CONFIG_RST (0x80000000) 231 232 #define reg_RX_CONTROL(base) __REG32(base, 0x00000324) 233 #define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) 234 #define GE_E0_RX_CONTROL_GO (0x00008000) 235 #define GE_E0_RX_CONTROL_EAI (0x20000000) 236 #define GE_E0_RX_CONTROL_ABT (0x40000000) 237 #define GE_E0_RX_CONTROL_EII (0x80000000) 238 239 #define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) 240 #define RX_EXTENDED_STATUS (0x0000032c) 241 #define RX_EXTENDED_STATUS_EOQ (0x0000000f) 242 #define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) 243 #define RX_EXTENDED_STATUS_EOF (0x00000f00) 244 #define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) 245 #define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) 246 247 #define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) 248 249 #define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) 250 #define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) 251 #define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) 252 #define RX_DIAGNOSTIC_ADDR_AI (0x80000000) 253 254 #define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) 255 256 #define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) 257 #define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) 258 #define RX_QUEUE_0_CONFIG_BSWP (0x00000400) 259 #define RX_QUEUE_0_CONFIG_WSWP (0x00000800) 260 #define RX_QUEUE_0_CONFIG_AM (0x00004000) 261 #define RX_QUEUE_0_CONFIG_EEI (0x00010000) 262 #define RX_QUEUE_0_CONFIG_ELI (0x00020000) 263 #define RX_QUEUE_0_CONFIG_ENI (0x00040000) 264 #define RX_QUEUE_0_CONFIG_ESI (0x00080000) 265 #define RX_QUEUE_0_CONFIG_EDI (0x00100000) 266 267 #define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) 268 #define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) 269 #define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) 270 #define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) 271 #define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) 272 273 #define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) 274 275 #define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) 276 #define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) 277 278 /* 279 * PHY register definitions 280 */ 281 /* the first 15 PHY registers are standard. */ 282 #define PHY_CTRL_REG 0 /* Control Register */ 283 #define PHY_STATUS_REG 1 /* Status Regiser */ 284 #define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ 285 #define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ 286 #define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ 287 #define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ 288 #define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ 289 #define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ 290 #define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ 291 #define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ 292 #define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ 293 #define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ 294 295 /* 296 * PHY Register bit masks. 297 */ 298 #define PHY_CTRL_RESET (1 << 15) 299 #define PHY_CTRL_LOOPBACK (1 << 14) 300 #define PHY_CTRL_SPEED0 (1 << 13) 301 #define PHY_CTRL_AN_EN (1 << 12) 302 #define PHY_CTRL_PWR_DN (1 << 11) 303 #define PHY_CTRL_ISOLATE (1 << 10) 304 #define PHY_CTRL_RESTART_AN (1 << 9) 305 #define PHY_CTRL_FULL_DUPLEX (1 << 8) 306 #define PHY_CTRL_CT_EN (1 << 7) 307 #define PHY_CTRL_SPEED1 (1 << 6) 308 309 #define PHY_STAT_100BASE_T4 (1 << 15) 310 #define PHY_STAT_100BASE_X_FD (1 << 14) 311 #define PHY_STAT_100BASE_X_HD (1 << 13) 312 #define PHY_STAT_10BASE_T_FD (1 << 12) 313 #define PHY_STAT_10BASE_T_HD (1 << 11) 314 #define PHY_STAT_100BASE_T2_FD (1 << 10) 315 #define PHY_STAT_100BASE_T2_HD (1 << 9) 316 #define PHY_STAT_EXT_STAT (1 << 8) 317 #define PHY_STAT_RESERVED (1 << 7) 318 #define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ 319 #define PHY_STAT_AN_COMPLETE (1 << 5) 320 #define PHY_STAT_REM_FAULT (1 << 4) 321 #define PHY_STAT_AN_CAP (1 << 3) 322 #define PHY_STAT_LINK_UP (1 << 2) 323 #define PHY_STAT_JABBER (1 << 1) 324 #define PHY_STAT_EXT_CAP (1 << 0) 325 326 #define TBI_CONTROL_2 0x11 327 #define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 328 #define TBI_CONTROL_2_ENABLE_WRAP 0x0002 329 #define TBI_CONTROL_2_G_MII_MODE 0x0010 330 #define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 331 #define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 332 #define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 333 #define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 334 #define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 335 #define TBI_CONTROL_2_SOFT_RESET 0x8000 336 337 /* marvel specific */ 338 #define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ 339 #define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ 340 #define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ 341 342 /* 343 * MARVELL 88E1111 PHY register bit masks 344 */ 345 /* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ 346 347 #define SPEC_STAT_SPEED_MASK (3 << 14) 348 #define SPEC_STAT_FULL_DUP (1 << 13) 349 #define SPEC_STAT_PAGE_RCVD (1 << 12) 350 #define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ 351 #define SPEC_STAT_LINK_UP (1 << 10) 352 #define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ 353 #define SPEC_STAT_MDIX (1 << 6) 354 #define SPEC_STAT_POLARITY (1 << 1) 355 #define SPEC_STAT_JABBER (1 << 0) 356 357 #define SPEED_1000 (2 << 14) 358 #define SPEED_100 (1 << 14) 359 #define SPEED_10 (0 << 14) 360 361 #define TBI_ADDR 0x1E /* Ten Bit Interface address */ 362 363 /* negotiated link parameters */ 364 #define LINK_SPEED_UNKNOWN 0 365 #define LINK_SPEED_10 1 366 #define LINK_SPEED_100 2 367 #define LINK_SPEED_1000 3 368 369 #define LINK_DUPLEX_UNKNOWN 0 370 #define LINK_DUPLEX_HALF 1 371 #define LINK_DUPLEX_FULL 2 372 373 static unsigned int phy_address[] = { 8, 9 }; 374 375 #define vuint32 volatile u32 376 377 /* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte) 378 * This structure is accessed by the ethernet DMA engine which means it 379 * MUST be in LITTLE ENDIAN format */ 380 struct dma_descriptor { 381 vuint32 start_addr0; /* buffer address, least significant bytes. */ 382 vuint32 start_addr1; /* buffer address, most significant bytes. */ 383 vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */ 384 vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */ 385 vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */ 386 vuint32 config_status; /* Configuration/Status. */ 387 vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */ 388 vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */ 389 }; 390 391 /* last next descriptor address flag */ 392 #define DMA_DESCR_LAST (1 << 31) 393 394 /* TX DMA descriptor config status bits */ 395 #define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ 396 #define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ 397 #define DMA_DESCR_TX_PFVLAN (1 << 2) 398 #define DMA_DESCR_TX_HUGE (1 << 3) 399 #define DMA_DESCR_TX_PAD (1 << 4) 400 #define DMA_DESCR_TX_CRC (1 << 5) 401 #define DMA_DESCR_TX_DESCR_INT (1 << 14) 402 #define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 403 #define DMA_DESCR_TX_ONE_COLLISION (1 << 20) 404 #define DMA_DESCR_TX_LATE_COLLISION (1 << 24) 405 #define DMA_DESCR_TX_UNDERRUN (1 << 25) 406 #define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) 407 #define DMA_DESCR_TX_OK (1 << 30) 408 #define DMA_DESCR_TX_OWNER (1 << 31) 409 410 /* RX DMA descriptor status bits */ 411 #define DMA_DESCR_RX_EOF (1 << 0) 412 #define DMA_DESCR_RX_SOF (1 << 1) 413 #define DMA_DESCR_RX_VTF (1 << 2) 414 #define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) 415 #define DMA_DESCR_RX_SHORT_FRAME (1 << 4) 416 #define DMA_DESCR_RX_HASH_MATCH (1 << 7) 417 #define DMA_DESCR_RX_BAD_FRAME (1 << 8) 418 #define DMA_DESCR_RX_OVERRUN (1 << 9) 419 #define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) 420 #define DMA_DESCR_RX_CRC_ERROR (1 << 12) 421 #define DMA_DESCR_RX_DESCR_INT (1 << 13) 422 #define DMA_DESCR_RX_OWNER (1 << 15) 423 424 #define RX_BUFFER_SIZE PKTSIZE 425 #define NUM_RX_DESC PKTBUFSRX 426 427 static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); 428 429 static struct dma_descriptor rx_descr_array[NUM_RX_DESC] 430 __attribute__ ((aligned(32))); 431 432 static struct dma_descriptor *rx_descr_current; 433 434 static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); 435 static int tsi108_eth_send (struct eth_device *dev, 436 volatile void *packet, int length); 437 static int tsi108_eth_recv (struct eth_device *dev); 438 static void tsi108_eth_halt (struct eth_device *dev); 439 static unsigned int read_phy (unsigned int base, 440 unsigned int phy_addr, unsigned int phy_reg); 441 static void write_phy (unsigned int base, 442 unsigned int phy_addr, 443 unsigned int phy_reg, unsigned int phy_data); 444 445 #if TSI108_ETH_DEBUG > 100 446 /* 447 * print phy debug infomation 448 */ 449 static void dump_phy_regs (unsigned int phy_addr) 450 { 451 int i; 452 453 printf ("PHY %d registers\n", phy_addr); 454 for (i = 0; i <= 30; i++) { 455 printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); 456 } 457 printf ("\n"); 458 459 } 460 #else 461 #define dump_phy_regs(base) do{}while(0) 462 #endif 463 464 #if TSI108_ETH_DEBUG > 100 465 /* 466 * print debug infomation 467 */ 468 static void tx_diag_regs (unsigned int base) 469 { 470 int i; 471 unsigned long dummy; 472 473 printf ("TX diagnostics registers\n"); 474 reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; 475 udelay (1000); 476 dummy = reg_TX_DIAGNOSTIC_DATA(base); 477 for (i = 0x00; i <= 0x05; i++) { 478 udelay (1000); 479 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); 480 } 481 reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; 482 udelay (1000); 483 dummy = reg_TX_DIAGNOSTIC_DATA(base); 484 for (i = 0x40; i <= 0x47; i++) { 485 udelay (1000); 486 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); 487 } 488 printf ("\n"); 489 490 } 491 #else 492 #define tx_diag_regs(base) do{}while(0) 493 #endif 494 495 #if TSI108_ETH_DEBUG > 100 496 /* 497 * print debug infomation 498 */ 499 static void rx_diag_regs (unsigned int base) 500 { 501 int i; 502 unsigned long dummy; 503 504 printf ("RX diagnostics registers\n"); 505 reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; 506 udelay (1000); 507 dummy = reg_RX_DIAGNOSTIC_DATA(base); 508 for (i = 0x00; i <= 0x05; i++) { 509 udelay (1000); 510 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); 511 } 512 reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; 513 udelay (1000); 514 dummy = reg_RX_DIAGNOSTIC_DATA(base); 515 for (i = 0x08; i <= 0x0a; i++) { 516 udelay (1000); 517 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); 518 } 519 printf ("\n"); 520 521 } 522 #else 523 #define rx_diag_regs(base) do{}while(0) 524 #endif 525 526 #if TSI108_ETH_DEBUG > 100 527 /* 528 * print debug infomation 529 */ 530 static void debug_mii_regs (unsigned int base) 531 { 532 printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); 533 printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); 534 printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); 535 printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); 536 printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); 537 printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); 538 printf ("\n"); 539 540 } 541 #else 542 #define debug_mii_regs(base) do{}while(0) 543 #endif 544 545 /* 546 * Wait until the phy bus is non-busy 547 */ 548 static void phy_wait (unsigned int base, unsigned int condition) 549 { 550 int timeout; 551 552 timeout = 0; 553 while (reg_MII_MGMT_INDICATORS(base) & condition) { 554 udelay (10); 555 if (++timeout > 10000) { 556 printf ("ERROR: timeout waiting for phy bus (%d)\n", 557 condition); 558 break; 559 } 560 } 561 } 562 563 /* 564 * read phy register 565 */ 566 static unsigned int read_phy (unsigned int base, 567 unsigned int phy_addr, unsigned int phy_reg) 568 { 569 unsigned int value; 570 571 phy_wait (base, MII_MGMT_INDICATORS_BUSY); 572 573 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; 574 575 /* Ensure that the Read Cycle bit is cleared prior to next read cycle */ 576 reg_MII_MGMT_COMMAND(base) = 0; 577 578 /* start the read */ 579 reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; 580 581 /* wait for the read to complete */ 582 phy_wait (base, 583 MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); 584 585 value = reg_MII_MGMT_STATUS(base); 586 587 reg_MII_MGMT_COMMAND(base) = 0; 588 589 return value; 590 } 591 592 /* 593 * write phy register 594 */ 595 static void write_phy (unsigned int base, 596 unsigned int phy_addr, 597 unsigned int phy_reg, unsigned int phy_data) 598 { 599 phy_wait (base, MII_MGMT_INDICATORS_BUSY); 600 601 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; 602 603 /* Ensure that the Read Cycle bit is cleared prior to next cycle */ 604 reg_MII_MGMT_COMMAND(base) = 0; 605 606 /* start the write */ 607 reg_MII_MGMT_CONTROL(base) = phy_data; 608 } 609 610 /* 611 * configure the marvell 88e1111 phy 612 */ 613 static int marvell_88e_phy_config (struct eth_device *dev, int *speed, 614 int *duplex) 615 { 616 unsigned long base; 617 unsigned long phy_addr; 618 unsigned int phy_status; 619 unsigned int phy_spec_status; 620 int timeout; 621 int phy_speed; 622 int phy_duplex; 623 unsigned int value; 624 625 phy_speed = LINK_SPEED_UNKNOWN; 626 phy_duplex = LINK_DUPLEX_UNKNOWN; 627 628 base = dev->iobase; 629 phy_addr = (unsigned long)dev->priv; 630 631 /* Take the PHY out of reset. */ 632 write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); 633 634 /* Wait for the reset process to complete. */ 635 udelay (10); 636 timeout = 0; 637 while ((phy_status = 638 read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { 639 udelay (10); 640 if (++timeout > 10000) { 641 printf ("ERROR: timeout waiting for phy reset\n"); 642 break; 643 } 644 } 645 646 /* TBI Configuration. */ 647 write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | 648 TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); 649 /* Wait for the link to be established. */ 650 timeout = 0; 651 do { 652 udelay (20000); 653 phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); 654 if (++timeout > 100) { 655 debug_lev(1, "ERROR: unable to establish link!!!\n"); 656 break; 657 } 658 } while ((phy_status & PHY_STAT_LINK_UP) == 0); 659 660 if ((phy_status & PHY_STAT_LINK_UP) == 0) 661 return 0; 662 663 value = 0; 664 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); 665 if (phy_spec_status & SPEC_STAT_RESOLVED) { 666 switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { 667 case SPEED_1000: 668 phy_speed = LINK_SPEED_1000; 669 value |= PHY_CTRL_SPEED1; 670 break; 671 case SPEED_100: 672 phy_speed = LINK_SPEED_100; 673 value |= PHY_CTRL_SPEED0; 674 break; 675 case SPEED_10: 676 phy_speed = LINK_SPEED_10; 677 break; 678 } 679 if (phy_spec_status & SPEC_STAT_FULL_DUP) { 680 phy_duplex = LINK_DUPLEX_FULL; 681 value |= PHY_CTRL_FULL_DUPLEX; 682 } else 683 phy_duplex = LINK_DUPLEX_HALF; 684 } 685 /* set TBI speed */ 686 write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); 687 write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); 688 689 #if TSI108_ETH_DEBUG > 0 690 printf ("%s link is up", dev->name); 691 phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); 692 if (phy_spec_status & SPEC_STAT_RESOLVED) { 693 switch (phy_speed) { 694 case LINK_SPEED_1000: 695 printf (", 1000 Mbps"); 696 break; 697 case LINK_SPEED_100: 698 printf (", 100 Mbps"); 699 break; 700 case LINK_SPEED_10: 701 printf (", 10 Mbps"); 702 break; 703 } 704 if (phy_duplex == LINK_DUPLEX_FULL) 705 printf (", Full duplex"); 706 else 707 printf (", Half duplex"); 708 } 709 printf ("\n"); 710 #endif 711 712 dump_phy_regs (TBI_ADDR); 713 if (speed) 714 *speed = phy_speed; 715 if (duplex) 716 *duplex = phy_duplex; 717 718 return 1; 719 } 720 721 /* 722 * External interface 723 * 724 * register the tsi108 ethernet controllers with the multi-ethernet system 725 */ 726 int tsi108_eth_initialize (bd_t * bis) 727 { 728 struct eth_device *dev; 729 int index; 730 731 for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { 732 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 733 734 sprintf (dev->name, "TSI108_eth%d", index); 735 736 dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); 737 dev->priv = (void *)(phy_address[index]); 738 dev->init = tsi108_eth_probe; 739 dev->halt = tsi108_eth_halt; 740 dev->send = tsi108_eth_send; 741 dev->recv = tsi108_eth_recv; 742 743 eth_register(dev); 744 } 745 return index; 746 } 747 748 /* 749 * probe for and initialize a single ethernet interface 750 */ 751 static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) 752 { 753 unsigned long base; 754 unsigned long value; 755 int index; 756 struct dma_descriptor *tx_descr; 757 struct dma_descriptor *rx_descr; 758 int speed; 759 int duplex; 760 761 base = dev->iobase; 762 763 reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; 764 765 /* Bring DMA/FIFO out of reset. */ 766 reg_TX_CONFIG(base) = 0x00000000; 767 reg_RX_CONFIG(base) = 0x00000000; 768 769 reg_TX_THRESHOLDS(base) = (192 << 16) | 192; 770 reg_RX_THRESHOLDS(base) = (192 << 16) | 112; 771 772 /* Bring MAC out of reset. */ 773 reg_MAC_CONFIG_1(base) = 0x00000000; 774 775 /* DMA MAC configuration. */ 776 reg_MAC_CONFIG_1(base) = 777 MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE; 778 779 reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; 780 reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; 781 782 /* Note: Early tsi108 manual did not have correct byte order 783 * for the station address.*/ 784 reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | 785 (dev->enetaddr[4] << 16) | 786 (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0); 787 788 reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | 789 (dev->enetaddr[0] << 16); 790 791 if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) 792 return -1; 793 794 value = 795 MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | 796 MAC_CONFIG_2_CRC_ENABLE; 797 if (speed == LINK_SPEED_1000) 798 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); 799 else { 800 value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); 801 reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; 802 } 803 if (duplex == LINK_DUPLEX_FULL) { 804 value |= MAC_CONFIG_2_FULL_DUPLEX; 805 reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; 806 } else 807 reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; 808 reg_MAC_CONFIG_2(base) = value; 809 810 reg_RX_CONFIG(base) = RX_CONFIG_SE; 811 reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; 812 reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; 813 814 /* initialize the RX DMA descriptors */ 815 rx_descr = &rx_descr_array[0]; 816 rx_descr_current = rx_descr; 817 for (index = 0; index < NUM_RX_DESC; index++) { 818 /* make sure the receive buffers are not in cache */ 819 invalidate_dcache_range((unsigned long)NetRxPackets[index], 820 (unsigned long)NetRxPackets[index] + 821 RX_BUFFER_SIZE); 822 rx_descr->start_addr0 = 823 cpu_to_le32((vuint32) NetRxPackets[index]); 824 rx_descr->start_addr1 = 0; 825 rx_descr->next_descr_addr0 = 826 cpu_to_le32((vuint32) (rx_descr + 1)); 827 rx_descr->next_descr_addr1 = 0; 828 rx_descr->vlan_byte_count = 0; 829 rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | 830 DMA_DESCR_RX_OWNER); 831 rx_descr++; 832 } 833 rx_descr--; 834 rx_descr->next_descr_addr0 = 0; 835 rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); 836 /* Push the descriptors to RAM so the ethernet DMA can see them */ 837 invalidate_dcache_range((unsigned long)rx_descr_array, 838 (unsigned long)rx_descr_array + 839 sizeof(rx_descr_array)); 840 841 /* enable RX queue */ 842 reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; 843 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; 844 /* enable receive DMA */ 845 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; 846 847 reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; 848 reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; 849 850 /* initialize the TX DMA descriptor */ 851 tx_descr = &tx_descriptor; 852 853 tx_descr->start_addr0 = 0; 854 tx_descr->start_addr1 = 0; 855 tx_descr->next_descr_addr0 = 0; 856 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); 857 tx_descr->vlan_byte_count = 0; 858 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK | 859 DMA_DESCR_TX_SOF | 860 DMA_DESCR_TX_EOF); 861 /* enable TX queue */ 862 reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; 863 864 return 0; 865 } 866 867 /* 868 * send a packet 869 */ 870 static int tsi108_eth_send (struct eth_device *dev, 871 volatile void *packet, int length) 872 { 873 unsigned long base; 874 int timeout; 875 struct dma_descriptor *tx_descr; 876 unsigned long status; 877 878 base = dev->iobase; 879 tx_descr = &tx_descriptor; 880 881 /* Wait until the last packet has been transmitted. */ 882 timeout = 0; 883 do { 884 /* make sure we see the changes made by the DMA engine */ 885 invalidate_dcache_range((unsigned long)tx_descr, 886 (unsigned long)tx_descr + 887 sizeof(struct dma_descriptor)); 888 889 if (timeout != 0) 890 udelay (15); 891 if (++timeout > 10000) { 892 tx_diag_regs(base); 893 debug_lev(1, 894 "ERROR: timeout waiting for last transmit packet to be sent\n"); 895 return 0; 896 } 897 } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER)); 898 899 status = le32_to_cpu(tx_descr->config_status); 900 if ((status & DMA_DESCR_TX_OK) == 0) { 901 #ifdef TX_PRINT_ERRORS 902 printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status, 903 status & DMA_DESCR_TX_OK ? "tx error, " : "", 904 status & DMA_DESCR_TX_RETRY_LIMIT ? 905 "retry limit reached, " : "", 906 status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "", 907 status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, " 908 : ""); 909 #endif 910 } 911 912 debug_lev (9, "sending packet %d\n", length); 913 tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); 914 tx_descr->start_addr1 = 0; 915 tx_descr->next_descr_addr0 = 0; 916 tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); 917 tx_descr->vlan_byte_count = cpu_to_le32(length); 918 tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER | 919 DMA_DESCR_TX_CRC | 920 DMA_DESCR_TX_PAD | 921 DMA_DESCR_TX_SOF | 922 DMA_DESCR_TX_EOF); 923 924 invalidate_dcache_range((unsigned long)tx_descr, 925 (unsigned long)tx_descr + 926 sizeof(struct dma_descriptor)); 927 928 invalidate_dcache_range((unsigned long)packet, 929 (unsigned long)packet + length); 930 931 reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; 932 reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; 933 934 return length; 935 } 936 937 /* 938 * Check for received packets and send them up the protocal stack 939 */ 940 static int tsi108_eth_recv (struct eth_device *dev) 941 { 942 struct dma_descriptor *rx_descr; 943 unsigned long base; 944 int length = 0; 945 unsigned long status; 946 volatile uchar *buffer; 947 948 base = dev->iobase; 949 950 /* make sure we see the changes made by the DMA engine */ 951 invalidate_dcache_range ((unsigned long)rx_descr_array, 952 (unsigned long)rx_descr_array + 953 sizeof(rx_descr_array)); 954 955 /* process all of the received packets */ 956 rx_descr = rx_descr_current; 957 while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) { 958 /* check for error */ 959 status = le32_to_cpu(rx_descr->config_status); 960 if (status & DMA_DESCR_RX_BAD_FRAME) { 961 #ifdef RX_PRINT_ERRORS 962 printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n", 963 status, 964 status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " 965 : "", 966 status & DMA_DESCR_RX_SHORT_FRAME ? "too short, " 967 : "", 968 status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " : 969 "", 970 status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "", 971 status & DMA_DESCR_RX_MAX_FRAME_LEN ? 972 "max length, " : "", 973 status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " : 974 ""); 975 #endif 976 } else { 977 length = 978 le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF; 979 980 /*** process packet ***/ 981 buffer = 982 (volatile uchar 983 *)(le32_to_cpu (rx_descr->start_addr0)); 984 NetReceive (buffer, length); 985 986 invalidate_dcache_range ((unsigned long)buffer, 987 (unsigned long)buffer + 988 RX_BUFFER_SIZE); 989 } 990 /* Give this buffer back to the DMA engine */ 991 rx_descr->vlan_byte_count = 0; 992 rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | 993 DMA_DESCR_RX_OWNER); 994 /* move descriptor pointer forward */ 995 rx_descr = 996 (struct dma_descriptor 997 *)(le32_to_cpu (rx_descr->next_descr_addr0)); 998 if (rx_descr == 0) 999 rx_descr = &rx_descr_array[0]; 1000 } 1001 /* remember where we are for next time */ 1002 rx_descr_current = rx_descr; 1003 1004 /* If the DMA engine has reached the end of the queue 1005 * start over at the begining */ 1006 if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { 1007 1008 reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; 1009 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; 1010 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; 1011 } 1012 1013 return length; 1014 } 1015 1016 /* 1017 * disable an ethernet interface 1018 */ 1019 static void tsi108_eth_halt (struct eth_device *dev) 1020 { 1021 unsigned long base; 1022 1023 base = dev->iobase; 1024 1025 /* Put DMA/FIFO into reset state. */ 1026 reg_TX_CONFIG(base) = TX_CONFIG_RST; 1027 reg_RX_CONFIG(base) = RX_CONFIG_RST; 1028 1029 /* Put MAC into reset state. */ 1030 reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; 1031 } 1032