1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2009 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <asm/errno.h> 21 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, 48 volatile void *packet, int length); 49 static int tsec_recv(struct eth_device *dev); 50 static int tsec_init(struct eth_device *dev, bd_t * bd); 51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 static struct phy_info *get_phy_info(struct eth_device *dev); 59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 62 && !defined(BITBANGMII) 63 static int tsec_miiphy_write(char *devname, unsigned char addr, 64 unsigned char reg, unsigned short value); 65 static int tsec_miiphy_read(char *devname, unsigned char addr, 66 unsigned char reg, unsigned short *value); 67 #endif 68 #ifdef CONFIG_MCAST_TFTP 69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 70 #endif 71 72 /* Default initializations for TSEC controllers. */ 73 74 static struct tsec_info_struct tsec_info[] = { 75 #ifdef CONFIG_TSEC1 76 STD_TSEC_INFO(1), /* TSEC1 */ 77 #endif 78 #ifdef CONFIG_TSEC2 79 STD_TSEC_INFO(2), /* TSEC2 */ 80 #endif 81 #ifdef CONFIG_MPC85XX_FEC 82 { 83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), 85 .devname = CONFIG_MPC85XX_FEC_NAME, 86 .phyaddr = FEC_PHY_ADDR, 87 .flags = FEC_FLAGS 88 }, /* FEC */ 89 #endif 90 #ifdef CONFIG_TSEC3 91 STD_TSEC_INFO(3), /* TSEC3 */ 92 #endif 93 #ifdef CONFIG_TSEC4 94 STD_TSEC_INFO(4), /* TSEC4 */ 95 #endif 96 }; 97 98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 99 { 100 int i; 101 102 for (i = 0; i < num; i++) 103 tsec_initialize(bis, &tsecs[i]); 104 105 return 0; 106 } 107 108 int tsec_standard_init(bd_t *bis) 109 { 110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 111 } 112 113 /* Initialize device structure. Returns success if PHY 114 * initialization succeeded (i.e. if it recognizes the PHY) 115 */ 116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 117 { 118 struct eth_device *dev; 119 int i; 120 struct tsec_private *priv; 121 122 dev = (struct eth_device *)malloc(sizeof *dev); 123 124 if (NULL == dev) 125 return 0; 126 127 memset(dev, 0, sizeof *dev); 128 129 priv = (struct tsec_private *)malloc(sizeof(*priv)); 130 131 if (NULL == priv) 132 return 0; 133 134 privlist[num_tsecs++] = priv; 135 priv->regs = tsec_info->regs; 136 priv->phyregs = tsec_info->miiregs; 137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 163 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 165 && !defined(BITBANGMII) 166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 167 #endif 168 169 /* Try to initialize PHY here, and return */ 170 return init_phy(dev); 171 } 172 173 /* Initializes data structures and registers for the controller, 174 * and brings the interface up. Returns the link status, meaning 175 * that it returns success if the link is up, failure otherwise. 176 * This allows u-boot to find the first active controller. 177 */ 178 static int tsec_init(struct eth_device *dev, bd_t * bd) 179 { 180 uint tempval; 181 char tmpbuf[MAC_ADDR_LEN]; 182 int i; 183 struct tsec_private *priv = (struct tsec_private *)dev->priv; 184 volatile tsec_t *regs = priv->regs; 185 186 /* Make sure the controller is stopped */ 187 tsec_halt(dev); 188 189 /* Init MACCFG2. Defaults to GMII */ 190 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 191 192 /* Init ECNTRL */ 193 regs->ecntrl = ECNTRL_INIT_SETTINGS; 194 195 /* Copy the station address into the address registers. 196 * Backwards, because little endian MACS are dumb */ 197 for (i = 0; i < MAC_ADDR_LEN; i++) { 198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 199 } 200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 201 tmpbuf[3]; 202 203 regs->macstnaddr1 = tempval; 204 205 tempval = *((uint *) (tmpbuf + 4)); 206 207 regs->macstnaddr2 = tempval; 208 209 /* reset the indices to zero */ 210 rxIdx = 0; 211 txIdx = 0; 212 213 /* Clear out (for the most part) the other registers */ 214 init_registers(regs); 215 216 /* Ready the device for tx/rx */ 217 startup_tsec(dev); 218 219 /* If there's no link, fail */ 220 return (priv->link ? 0 : -1); 221 } 222 223 /* Writes the given phy's reg with value, using the specified MDIO regs */ 224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, 225 uint reg, uint value) 226 { 227 int timeout = 1000000; 228 229 phyregs->miimadd = (addr << 8) | reg; 230 phyregs->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 238 /* Provide the default behavior of writing the PHY of this ethernet device */ 239 #define write_phy_reg(priv, regnum, value) \ 240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 241 242 /* Reads register regnum on the device's PHY through the 243 * specified registers. It lowers and raises the read 244 * command, and waits for the data to become valid (miimind 245 * notvalid bit cleared), and the bus to cease activity (miimind 246 * busy bit cleared), and then returns the value 247 */ 248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, 249 uint phyid, uint regnum) 250 { 251 uint value; 252 253 /* Put the address of the phy, and the register 254 * number into MIIMADD */ 255 phyregs->miimadd = (phyid << 8) | regnum; 256 257 /* Clear the command register, and wait */ 258 phyregs->miimcom = 0; 259 asm("sync"); 260 261 /* Initiate a read command, and wait */ 262 phyregs->miimcom = MIIM_READ_COMMAND; 263 asm("sync"); 264 265 /* Wait for the the indication that the read is done */ 266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 267 268 /* Grab the value read from the PHY */ 269 value = phyregs->miimstat; 270 271 return value; 272 } 273 274 /* #define to provide old read_phy_reg functionality without duplicating code */ 275 #define read_phy_reg(priv,regnum) \ 276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 277 278 #define TBIANA_SETTINGS ( \ 279 TBIANA_ASYMMETRIC_PAUSE \ 280 | TBIANA_SYMMETRIC_PAUSE \ 281 | TBIANA_FULL_DUPLEX \ 282 ) 283 284 /* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 285 #define TBICR_SETTINGS ( \ 286 TBICR_PHY_RESET \ 287 | TBICR_FULL_DUPLEX \ 288 | TBICR_SPEED1_SET \ 289 ) 290 291 /* Configure the TBI for SGMII operation */ 292 static void tsec_configure_serdes(struct tsec_private *priv) 293 { 294 /* Access TBI PHY registers at given TSEC register offset as opposed 295 * to the register offset used for external PHY accesses */ 296 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, 297 TBIANA_SETTINGS); 298 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, 299 TBICON_CLK_SELECT); 300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, 301 TBICR_SETTINGS); 302 } 303 304 /* Discover which PHY is attached to the device, and configure it 305 * properly. If the PHY is not recognized, then return 0 306 * (failure). Otherwise, return 1 307 */ 308 static int init_phy(struct eth_device *dev) 309 { 310 struct tsec_private *priv = (struct tsec_private *)dev->priv; 311 struct phy_info *curphy; 312 volatile tsec_t *regs = priv->regs; 313 314 /* Assign a Physical address to the TBI */ 315 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 316 asm("sync"); 317 318 /* Reset MII (due to new addresses) */ 319 priv->phyregs->miimcfg = MIIMCFG_RESET; 320 asm("sync"); 321 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 322 asm("sync"); 323 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 324 325 /* Get the cmd structure corresponding to the attached 326 * PHY */ 327 curphy = get_phy_info(dev); 328 329 if (curphy == NULL) { 330 priv->phyinfo = NULL; 331 printf("%s: No PHY found\n", dev->name); 332 333 return 0; 334 } 335 336 if (regs->ecntrl & ECNTRL_SGMII_MODE) 337 tsec_configure_serdes(priv); 338 339 priv->phyinfo = curphy; 340 341 phy_run_commands(priv, priv->phyinfo->config); 342 343 return 1; 344 } 345 346 /* 347 * Returns which value to write to the control register. 348 * For 10/100, the value is slightly different 349 */ 350 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 351 { 352 if (priv->flags & TSEC_GIGABIT) 353 return MIIM_CONTROL_INIT; 354 else 355 return MIIM_CR_INIT; 356 } 357 358 /* 359 * Wait for auto-negotiation to complete, then determine link 360 */ 361 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 362 { 363 /* 364 * Wait if the link is up, and autonegotiation is in progress 365 * (ie - we're capable and it's not done) 366 */ 367 mii_reg = read_phy_reg(priv, MIIM_STATUS); 368 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 369 int i = 0; 370 371 puts("Waiting for PHY auto negotiation to complete"); 372 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 373 /* 374 * Timeout reached ? 375 */ 376 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 377 puts(" TIMEOUT !\n"); 378 priv->link = 0; 379 return 0; 380 } 381 382 if (ctrlc()) { 383 puts("user interrupt!\n"); 384 priv->link = 0; 385 return -EINTR; 386 } 387 388 if ((i++ % 1000) == 0) { 389 putc('.'); 390 } 391 udelay(1000); /* 1 ms */ 392 mii_reg = read_phy_reg(priv, MIIM_STATUS); 393 } 394 puts(" done\n"); 395 396 /* Link status bit is latched low, read it again */ 397 mii_reg = read_phy_reg(priv, MIIM_STATUS); 398 399 udelay(500000); /* another 500 ms (results in faster booting) */ 400 } 401 402 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; 403 404 return 0; 405 } 406 407 /* Generic function which updates the speed and duplex. If 408 * autonegotiation is enabled, it uses the AND of the link 409 * partner's advertised capabilities and our advertised 410 * capabilities. If autonegotiation is disabled, we use the 411 * appropriate bits in the control register. 412 * 413 * Stolen from Linux's mii.c and phy_device.c 414 */ 415 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 416 { 417 /* We're using autonegotiation */ 418 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 419 uint lpa = 0; 420 uint gblpa = 0; 421 422 /* Check for gigabit capability */ 423 if (mii_reg & PHY_BMSR_EXT) { 424 /* We want a list of states supported by 425 * both PHYs in the link 426 */ 427 gblpa = read_phy_reg(priv, PHY_1000BTSR); 428 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 429 } 430 431 /* Set the baseline so we only have to set them 432 * if they're different 433 */ 434 priv->speed = 10; 435 priv->duplexity = 0; 436 437 /* Check the gigabit fields */ 438 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 439 priv->speed = 1000; 440 441 if (gblpa & PHY_1000BTSR_1000FD) 442 priv->duplexity = 1; 443 444 /* We're done! */ 445 return 0; 446 } 447 448 lpa = read_phy_reg(priv, PHY_ANAR); 449 lpa &= read_phy_reg(priv, PHY_ANLPAR); 450 451 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 452 priv->speed = 100; 453 454 if (lpa & PHY_ANLPAR_TXFD) 455 priv->duplexity = 1; 456 457 } else if (lpa & PHY_ANLPAR_10FD) 458 priv->duplexity = 1; 459 } else { 460 uint bmcr = read_phy_reg(priv, PHY_BMCR); 461 462 priv->speed = 10; 463 priv->duplexity = 0; 464 465 if (bmcr & PHY_BMCR_DPLX) 466 priv->duplexity = 1; 467 468 if (bmcr & PHY_BMCR_1000_MBPS) 469 priv->speed = 1000; 470 else if (bmcr & PHY_BMCR_100_MBPS) 471 priv->speed = 100; 472 } 473 474 return 0; 475 } 476 477 /* 478 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 479 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 480 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 481 * link. "Ethernet@Wirespeed" reduces advertised speed until link 482 * can be achieved. 483 */ 484 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) 485 { 486 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; 487 } 488 489 /* 490 * Parse the BCM54xx status register for speed and duplex information. 491 * The linux sungem_phy has this information, but in a table format. 492 */ 493 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 494 { 495 /* If there is no link, speed and duplex don't matter */ 496 if (!priv->link) 497 return 0; 498 499 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 500 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 501 case 1: 502 priv->duplexity = 0; 503 priv->speed = 10; 504 break; 505 case 2: 506 priv->duplexity = 1; 507 priv->speed = 10; 508 break; 509 case 3: 510 priv->duplexity = 0; 511 priv->speed = 100; 512 break; 513 case 5: 514 priv->duplexity = 1; 515 priv->speed = 100; 516 break; 517 case 6: 518 priv->duplexity = 0; 519 priv->speed = 1000; 520 break; 521 case 7: 522 priv->duplexity = 1; 523 priv->speed = 1000; 524 break; 525 default: 526 printf("Auto-neg error, defaulting to 10BT/HD\n"); 527 priv->duplexity = 0; 528 priv->speed = 10; 529 break; 530 } 531 532 return 0; 533 534 } 535 /* Parse the 88E1011's status register for speed and duplex 536 * information 537 */ 538 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 539 { 540 uint speed; 541 542 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 543 544 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 545 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 546 int i = 0; 547 548 puts("Waiting for PHY realtime link"); 549 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 550 /* Timeout reached ? */ 551 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 552 puts(" TIMEOUT !\n"); 553 priv->link = 0; 554 break; 555 } 556 557 if ((i++ % 1000) == 0) { 558 putc('.'); 559 } 560 udelay(1000); /* 1 ms */ 561 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 562 } 563 puts(" done\n"); 564 udelay(500000); /* another 500 ms (results in faster booting) */ 565 } else { 566 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 567 priv->link = 1; 568 else 569 priv->link = 0; 570 } 571 572 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 573 priv->duplexity = 1; 574 else 575 priv->duplexity = 0; 576 577 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 578 579 switch (speed) { 580 case MIIM_88E1011_PHYSTAT_GBIT: 581 priv->speed = 1000; 582 break; 583 case MIIM_88E1011_PHYSTAT_100: 584 priv->speed = 100; 585 break; 586 default: 587 priv->speed = 10; 588 } 589 590 return 0; 591 } 592 593 /* Parse the RTL8211B's status register for speed and duplex 594 * information 595 */ 596 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 597 { 598 uint speed; 599 600 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 601 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 602 int i = 0; 603 604 /* in case of timeout ->link is cleared */ 605 priv->link = 1; 606 puts("Waiting for PHY realtime link"); 607 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 608 /* Timeout reached ? */ 609 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 610 puts(" TIMEOUT !\n"); 611 priv->link = 0; 612 break; 613 } 614 615 if ((i++ % 1000) == 0) { 616 putc('.'); 617 } 618 udelay(1000); /* 1 ms */ 619 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 620 } 621 puts(" done\n"); 622 udelay(500000); /* another 500 ms (results in faster booting) */ 623 } else { 624 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 625 priv->link = 1; 626 else 627 priv->link = 0; 628 } 629 630 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 631 priv->duplexity = 1; 632 else 633 priv->duplexity = 0; 634 635 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 636 637 switch (speed) { 638 case MIIM_RTL8211B_PHYSTAT_GBIT: 639 priv->speed = 1000; 640 break; 641 case MIIM_RTL8211B_PHYSTAT_100: 642 priv->speed = 100; 643 break; 644 default: 645 priv->speed = 10; 646 } 647 648 return 0; 649 } 650 651 /* Parse the cis8201's status register for speed and duplex 652 * information 653 */ 654 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 655 { 656 uint speed; 657 658 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 659 priv->duplexity = 1; 660 else 661 priv->duplexity = 0; 662 663 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 664 switch (speed) { 665 case MIIM_CIS8201_AUXCONSTAT_GBIT: 666 priv->speed = 1000; 667 break; 668 case MIIM_CIS8201_AUXCONSTAT_100: 669 priv->speed = 100; 670 break; 671 default: 672 priv->speed = 10; 673 break; 674 } 675 676 return 0; 677 } 678 679 /* Parse the vsc8244's status register for speed and duplex 680 * information 681 */ 682 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 683 { 684 uint speed; 685 686 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 687 priv->duplexity = 1; 688 else 689 priv->duplexity = 0; 690 691 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 692 switch (speed) { 693 case MIIM_VSC8244_AUXCONSTAT_GBIT: 694 priv->speed = 1000; 695 break; 696 case MIIM_VSC8244_AUXCONSTAT_100: 697 priv->speed = 100; 698 break; 699 default: 700 priv->speed = 10; 701 break; 702 } 703 704 return 0; 705 } 706 707 /* Parse the DM9161's status register for speed and duplex 708 * information 709 */ 710 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 711 { 712 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 713 priv->speed = 100; 714 else 715 priv->speed = 10; 716 717 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 718 priv->duplexity = 1; 719 else 720 priv->duplexity = 0; 721 722 return 0; 723 } 724 725 /* 726 * Hack to write all 4 PHYs with the LED values 727 */ 728 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 729 { 730 uint phyid; 731 volatile tsec_mdio_t *regbase = priv->phyregs; 732 int timeout = 1000000; 733 734 for (phyid = 0; phyid < 4; phyid++) { 735 regbase->miimadd = (phyid << 8) | mii_reg; 736 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 737 asm("sync"); 738 739 timeout = 1000000; 740 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 741 } 742 743 return MIIM_CIS8204_SLEDCON_INIT; 744 } 745 746 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 747 { 748 if (priv->flags & TSEC_REDUCED) 749 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 750 else 751 return MIIM_CIS8204_EPHYCON_INIT; 752 } 753 754 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 755 { 756 uint mii_data = read_phy_reg(priv, mii_reg); 757 758 if (priv->flags & TSEC_REDUCED) 759 mii_data = (mii_data & 0xfff0) | 0x000b; 760 return mii_data; 761 } 762 763 /* Initialized required registers to appropriate values, zeroing 764 * those we don't care about (unless zero is bad, in which case, 765 * choose a more appropriate value) 766 */ 767 static void init_registers(volatile tsec_t * regs) 768 { 769 /* Clear IEVENT */ 770 regs->ievent = IEVENT_INIT_CLEAR; 771 772 regs->imask = IMASK_INIT_CLEAR; 773 774 regs->hash.iaddr0 = 0; 775 regs->hash.iaddr1 = 0; 776 regs->hash.iaddr2 = 0; 777 regs->hash.iaddr3 = 0; 778 regs->hash.iaddr4 = 0; 779 regs->hash.iaddr5 = 0; 780 regs->hash.iaddr6 = 0; 781 regs->hash.iaddr7 = 0; 782 783 regs->hash.gaddr0 = 0; 784 regs->hash.gaddr1 = 0; 785 regs->hash.gaddr2 = 0; 786 regs->hash.gaddr3 = 0; 787 regs->hash.gaddr4 = 0; 788 regs->hash.gaddr5 = 0; 789 regs->hash.gaddr6 = 0; 790 regs->hash.gaddr7 = 0; 791 792 regs->rctrl = 0x00000000; 793 794 /* Init RMON mib registers */ 795 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 796 797 regs->rmon.cam1 = 0xffffffff; 798 regs->rmon.cam2 = 0xffffffff; 799 800 regs->mrblr = MRBLR_INIT_SETTINGS; 801 802 regs->minflr = MINFLR_INIT_SETTINGS; 803 804 regs->attr = ATTR_INIT_SETTINGS; 805 regs->attreli = ATTRELI_INIT_SETTINGS; 806 807 } 808 809 /* Configure maccfg2 based on negotiated speed and duplex 810 * reported by PHY handling code 811 */ 812 static void adjust_link(struct eth_device *dev) 813 { 814 struct tsec_private *priv = (struct tsec_private *)dev->priv; 815 volatile tsec_t *regs = priv->regs; 816 817 if (priv->link) { 818 if (priv->duplexity != 0) 819 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 820 else 821 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 822 823 switch (priv->speed) { 824 case 1000: 825 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 826 | MACCFG2_GMII); 827 break; 828 case 100: 829 case 10: 830 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 831 | MACCFG2_MII); 832 833 /* Set R100 bit in all modes although 834 * it is only used in RGMII mode 835 */ 836 if (priv->speed == 100) 837 regs->ecntrl |= ECNTRL_R100; 838 else 839 regs->ecntrl &= ~(ECNTRL_R100); 840 break; 841 default: 842 printf("%s: Speed was bad\n", dev->name); 843 break; 844 } 845 846 printf("Speed: %d, %s duplex\n", priv->speed, 847 (priv->duplexity) ? "full" : "half"); 848 849 } else { 850 printf("%s: No link.\n", dev->name); 851 } 852 } 853 854 /* Set up the buffers and their descriptors, and bring up the 855 * interface 856 */ 857 static void startup_tsec(struct eth_device *dev) 858 { 859 int i; 860 struct tsec_private *priv = (struct tsec_private *)dev->priv; 861 volatile tsec_t *regs = priv->regs; 862 863 /* Point to the buffer descriptors */ 864 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 865 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 866 867 /* Initialize the Rx Buffer descriptors */ 868 for (i = 0; i < PKTBUFSRX; i++) { 869 rtx.rxbd[i].status = RXBD_EMPTY; 870 rtx.rxbd[i].length = 0; 871 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 872 } 873 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 874 875 /* Initialize the TX Buffer Descriptors */ 876 for (i = 0; i < TX_BUF_CNT; i++) { 877 rtx.txbd[i].status = 0; 878 rtx.txbd[i].length = 0; 879 rtx.txbd[i].bufPtr = 0; 880 } 881 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 882 883 /* Start up the PHY */ 884 if(priv->phyinfo) 885 phy_run_commands(priv, priv->phyinfo->startup); 886 887 adjust_link(dev); 888 889 /* Enable Transmit and Receive */ 890 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 891 892 /* Tell the DMA it is clear to go */ 893 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 894 regs->tstat = TSTAT_CLEAR_THALT; 895 regs->rstat = RSTAT_CLEAR_RHALT; 896 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 897 } 898 899 /* This returns the status bits of the device. The return value 900 * is never checked, and this is what the 8260 driver did, so we 901 * do the same. Presumably, this would be zero if there were no 902 * errors 903 */ 904 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 905 { 906 int i; 907 int result = 0; 908 struct tsec_private *priv = (struct tsec_private *)dev->priv; 909 volatile tsec_t *regs = priv->regs; 910 911 /* Find an empty buffer descriptor */ 912 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 913 if (i >= TOUT_LOOP) { 914 debug("%s: tsec: tx buffers full\n", dev->name); 915 return result; 916 } 917 } 918 919 rtx.txbd[txIdx].bufPtr = (uint) packet; 920 rtx.txbd[txIdx].length = length; 921 rtx.txbd[txIdx].status |= 922 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 923 924 /* Tell the DMA to go */ 925 regs->tstat = TSTAT_CLEAR_THALT; 926 927 /* Wait for buffer to be transmitted */ 928 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 929 if (i >= TOUT_LOOP) { 930 debug("%s: tsec: tx error\n", dev->name); 931 return result; 932 } 933 } 934 935 txIdx = (txIdx + 1) % TX_BUF_CNT; 936 result = rtx.txbd[txIdx].status & TXBD_STATS; 937 938 return result; 939 } 940 941 static int tsec_recv(struct eth_device *dev) 942 { 943 int length; 944 struct tsec_private *priv = (struct tsec_private *)dev->priv; 945 volatile tsec_t *regs = priv->regs; 946 947 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 948 949 length = rtx.rxbd[rxIdx].length; 950 951 /* Send the packet up if there were no errors */ 952 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 953 NetReceive(NetRxPackets[rxIdx], length - 4); 954 } else { 955 printf("Got error %x\n", 956 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 957 } 958 959 rtx.rxbd[rxIdx].length = 0; 960 961 /* Set the wrap bit if this is the last element in the list */ 962 rtx.rxbd[rxIdx].status = 963 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 964 965 rxIdx = (rxIdx + 1) % PKTBUFSRX; 966 } 967 968 if (regs->ievent & IEVENT_BSY) { 969 regs->ievent = IEVENT_BSY; 970 regs->rstat = RSTAT_CLEAR_RHALT; 971 } 972 973 return -1; 974 975 } 976 977 /* Stop the interface */ 978 static void tsec_halt(struct eth_device *dev) 979 { 980 struct tsec_private *priv = (struct tsec_private *)dev->priv; 981 volatile tsec_t *regs = priv->regs; 982 983 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 984 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 985 986 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 987 988 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 989 990 /* Shut down the PHY, as needed */ 991 if(priv->phyinfo) 992 phy_run_commands(priv, priv->phyinfo->shutdown); 993 } 994 995 static struct phy_info phy_info_M88E1149S = { 996 0x1410ca, 997 "Marvell 88E1149S", 998 4, 999 (struct phy_cmd[]) { /* config */ 1000 /* Reset and configure the PHY */ 1001 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1002 {0x1d, 0x1f, NULL}, 1003 {0x1e, 0x200c, NULL}, 1004 {0x1d, 0x5, NULL}, 1005 {0x1e, 0x0, NULL}, 1006 {0x1e, 0x100, NULL}, 1007 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1008 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1009 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1010 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1011 {miim_end,} 1012 }, 1013 (struct phy_cmd[]) { /* startup */ 1014 /* Status is read once to clear old link state */ 1015 {MIIM_STATUS, miim_read, NULL}, 1016 /* Auto-negotiate */ 1017 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1018 /* Read the status */ 1019 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1020 {miim_end,} 1021 }, 1022 (struct phy_cmd[]) { /* shutdown */ 1023 {miim_end,} 1024 }, 1025 }; 1026 1027 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1028 static struct phy_info phy_info_BCM5461S = { 1029 0x02060c1, /* 5461 ID */ 1030 "Broadcom BCM5461S", 1031 0, /* not clear to me what minor revisions we can shift away */ 1032 (struct phy_cmd[]) { /* config */ 1033 /* Reset and configure the PHY */ 1034 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1035 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1036 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1037 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1038 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1039 {miim_end,} 1040 }, 1041 (struct phy_cmd[]) { /* startup */ 1042 /* Status is read once to clear old link state */ 1043 {MIIM_STATUS, miim_read, NULL}, 1044 /* Auto-negotiate */ 1045 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1046 /* Read the status */ 1047 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1048 {miim_end,} 1049 }, 1050 (struct phy_cmd[]) { /* shutdown */ 1051 {miim_end,} 1052 }, 1053 }; 1054 1055 static struct phy_info phy_info_BCM5464S = { 1056 0x02060b1, /* 5464 ID */ 1057 "Broadcom BCM5464S", 1058 0, /* not clear to me what minor revisions we can shift away */ 1059 (struct phy_cmd[]) { /* config */ 1060 /* Reset and configure the PHY */ 1061 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1062 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1063 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1064 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1065 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1066 {miim_end,} 1067 }, 1068 (struct phy_cmd[]) { /* startup */ 1069 /* Status is read once to clear old link state */ 1070 {MIIM_STATUS, miim_read, NULL}, 1071 /* Auto-negotiate */ 1072 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1073 /* Read the status */ 1074 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1075 {miim_end,} 1076 }, 1077 (struct phy_cmd[]) { /* shutdown */ 1078 {miim_end,} 1079 }, 1080 }; 1081 1082 static struct phy_info phy_info_BCM5482S = { 1083 0x0143bcb, 1084 "Broadcom BCM5482S", 1085 4, 1086 (struct phy_cmd[]) { /* config */ 1087 /* Reset and configure the PHY */ 1088 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1089 /* Setup read from auxilary control shadow register 7 */ 1090 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, 1091 /* Read Misc Control register and or in Ethernet@Wirespeed */ 1092 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, 1093 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1094 {miim_end,} 1095 }, 1096 (struct phy_cmd[]) { /* startup */ 1097 /* Status is read once to clear old link state */ 1098 {MIIM_STATUS, miim_read, NULL}, 1099 /* Auto-negotiate */ 1100 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1101 /* Read the status */ 1102 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1103 {miim_end,} 1104 }, 1105 (struct phy_cmd[]) { /* shutdown */ 1106 {miim_end,} 1107 }, 1108 }; 1109 1110 static struct phy_info phy_info_M88E1011S = { 1111 0x01410c6, 1112 "Marvell 88E1011S", 1113 4, 1114 (struct phy_cmd[]) { /* config */ 1115 /* Reset and configure the PHY */ 1116 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1117 {0x1d, 0x1f, NULL}, 1118 {0x1e, 0x200c, NULL}, 1119 {0x1d, 0x5, NULL}, 1120 {0x1e, 0x0, NULL}, 1121 {0x1e, 0x100, NULL}, 1122 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1123 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1124 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1125 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1126 {miim_end,} 1127 }, 1128 (struct phy_cmd[]) { /* startup */ 1129 /* Status is read once to clear old link state */ 1130 {MIIM_STATUS, miim_read, NULL}, 1131 /* Auto-negotiate */ 1132 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1133 /* Read the status */ 1134 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1135 {miim_end,} 1136 }, 1137 (struct phy_cmd[]) { /* shutdown */ 1138 {miim_end,} 1139 }, 1140 }; 1141 1142 static struct phy_info phy_info_M88E1111S = { 1143 0x01410cc, 1144 "Marvell 88E1111S", 1145 4, 1146 (struct phy_cmd[]) { /* config */ 1147 /* Reset and configure the PHY */ 1148 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1149 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1150 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1151 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1152 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1153 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1154 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1155 {miim_end,} 1156 }, 1157 (struct phy_cmd[]) { /* startup */ 1158 /* Status is read once to clear old link state */ 1159 {MIIM_STATUS, miim_read, NULL}, 1160 /* Auto-negotiate */ 1161 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1162 /* Read the status */ 1163 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1164 {miim_end,} 1165 }, 1166 (struct phy_cmd[]) { /* shutdown */ 1167 {miim_end,} 1168 }, 1169 }; 1170 1171 static struct phy_info phy_info_M88E1118 = { 1172 0x01410e1, 1173 "Marvell 88E1118", 1174 4, 1175 (struct phy_cmd[]) { /* config */ 1176 /* Reset and configure the PHY */ 1177 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1178 {0x16, 0x0002, NULL}, /* Change Page Number */ 1179 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1180 {0x16, 0x0003, NULL}, /* Change Page Number */ 1181 {0x10, 0x021e, NULL}, /* Adjust LED control */ 1182 {0x16, 0x0000, NULL}, /* Change Page Number */ 1183 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1184 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1185 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1186 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1187 {miim_end,} 1188 }, 1189 (struct phy_cmd[]) { /* startup */ 1190 {0x16, 0x0000, NULL}, /* Change Page Number */ 1191 /* Status is read once to clear old link state */ 1192 {MIIM_STATUS, miim_read, NULL}, 1193 /* Auto-negotiate */ 1194 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1195 /* Read the status */ 1196 {MIIM_88E1011_PHY_STATUS, miim_read, 1197 &mii_parse_88E1011_psr}, 1198 {miim_end,} 1199 }, 1200 (struct phy_cmd[]) { /* shutdown */ 1201 {miim_end,} 1202 }, 1203 }; 1204 1205 /* 1206 * Since to access LED register we need do switch the page, we 1207 * do LED configuring in the miim_read-like function as follows 1208 */ 1209 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1210 { 1211 uint pg; 1212 1213 /* Switch the page to access the led register */ 1214 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1215 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1216 1217 /* Configure leds */ 1218 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1219 MIIM_88E1121_PHY_LED_DEF); 1220 1221 /* Restore the page pointer */ 1222 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1223 return 0; 1224 } 1225 1226 static struct phy_info phy_info_M88E1121R = { 1227 0x01410cb, 1228 "Marvell 88E1121R", 1229 4, 1230 (struct phy_cmd[]) { /* config */ 1231 /* Reset and configure the PHY */ 1232 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1233 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1234 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1235 /* Configure leds */ 1236 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, 1237 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1238 /* Disable IRQs and de-assert interrupt */ 1239 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1240 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1241 {miim_end,} 1242 }, 1243 (struct phy_cmd[]) { /* startup */ 1244 /* Status is read once to clear old link state */ 1245 {MIIM_STATUS, miim_read, NULL}, 1246 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1247 {MIIM_STATUS, miim_read, &mii_parse_link}, 1248 {miim_end,} 1249 }, 1250 (struct phy_cmd[]) { /* shutdown */ 1251 {miim_end,} 1252 }, 1253 }; 1254 1255 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1256 { 1257 uint mii_data = read_phy_reg(priv, mii_reg); 1258 1259 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1260 if (priv->flags & TSEC_REDUCED) 1261 return mii_data | 1262 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1263 else 1264 return mii_data; 1265 } 1266 1267 static struct phy_info phy_info_M88E1145 = { 1268 0x01410cd, 1269 "Marvell 88E1145", 1270 4, 1271 (struct phy_cmd[]) { /* config */ 1272 /* Reset the PHY */ 1273 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1274 1275 /* Errata E0, E1 */ 1276 {29, 0x001b, NULL}, 1277 {30, 0x418f, NULL}, 1278 {29, 0x0016, NULL}, 1279 {30, 0xa2da, NULL}, 1280 1281 /* Configure the PHY */ 1282 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1283 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1284 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, 1285 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1286 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1287 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1288 {miim_end,} 1289 }, 1290 (struct phy_cmd[]) { /* startup */ 1291 /* Status is read once to clear old link state */ 1292 {MIIM_STATUS, miim_read, NULL}, 1293 /* Auto-negotiate */ 1294 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1295 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1296 /* Read the Status */ 1297 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1298 {miim_end,} 1299 }, 1300 (struct phy_cmd[]) { /* shutdown */ 1301 {miim_end,} 1302 }, 1303 }; 1304 1305 static struct phy_info phy_info_cis8204 = { 1306 0x3f11, 1307 "Cicada Cis8204", 1308 6, 1309 (struct phy_cmd[]) { /* config */ 1310 /* Override PHY config settings */ 1311 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1312 /* Configure some basic stuff */ 1313 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1314 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1315 &mii_cis8204_fixled}, 1316 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1317 &mii_cis8204_setmode}, 1318 {miim_end,} 1319 }, 1320 (struct phy_cmd[]) { /* startup */ 1321 /* Read the Status (2x to make sure link is right) */ 1322 {MIIM_STATUS, miim_read, NULL}, 1323 /* Auto-negotiate */ 1324 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1325 /* Read the status */ 1326 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1327 {miim_end,} 1328 }, 1329 (struct phy_cmd[]) { /* shutdown */ 1330 {miim_end,} 1331 }, 1332 }; 1333 1334 /* Cicada 8201 */ 1335 static struct phy_info phy_info_cis8201 = { 1336 0xfc41, 1337 "CIS8201", 1338 4, 1339 (struct phy_cmd[]) { /* config */ 1340 /* Override PHY config settings */ 1341 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1342 /* Set up the interface mode */ 1343 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1344 /* Configure some basic stuff */ 1345 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1346 {miim_end,} 1347 }, 1348 (struct phy_cmd[]) { /* startup */ 1349 /* Read the Status (2x to make sure link is right) */ 1350 {MIIM_STATUS, miim_read, NULL}, 1351 /* Auto-negotiate */ 1352 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1353 /* Read the status */ 1354 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1355 {miim_end,} 1356 }, 1357 (struct phy_cmd[]) { /* shutdown */ 1358 {miim_end,} 1359 }, 1360 }; 1361 1362 static struct phy_info phy_info_VSC8211 = { 1363 0xfc4b, 1364 "Vitesse VSC8211", 1365 4, 1366 (struct phy_cmd[]) { /* config */ 1367 /* Override PHY config settings */ 1368 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1369 /* Set up the interface mode */ 1370 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1371 /* Configure some basic stuff */ 1372 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1373 {miim_end,} 1374 }, 1375 (struct phy_cmd[]) { /* startup */ 1376 /* Read the Status (2x to make sure link is right) */ 1377 {MIIM_STATUS, miim_read, NULL}, 1378 /* Auto-negotiate */ 1379 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1380 /* Read the status */ 1381 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1382 {miim_end,} 1383 }, 1384 (struct phy_cmd[]) { /* shutdown */ 1385 {miim_end,} 1386 }, 1387 }; 1388 1389 static struct phy_info phy_info_VSC8244 = { 1390 0x3f1b, 1391 "Vitesse VSC8244", 1392 6, 1393 (struct phy_cmd[]) { /* config */ 1394 /* Override PHY config settings */ 1395 /* Configure some basic stuff */ 1396 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1397 {miim_end,} 1398 }, 1399 (struct phy_cmd[]) { /* startup */ 1400 /* Read the Status (2x to make sure link is right) */ 1401 {MIIM_STATUS, miim_read, NULL}, 1402 /* Auto-negotiate */ 1403 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1404 /* Read the status */ 1405 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1406 {miim_end,} 1407 }, 1408 (struct phy_cmd[]) { /* shutdown */ 1409 {miim_end,} 1410 }, 1411 }; 1412 1413 static struct phy_info phy_info_VSC8641 = { 1414 0x7043, 1415 "Vitesse VSC8641", 1416 4, 1417 (struct phy_cmd[]) { /* config */ 1418 /* Configure some basic stuff */ 1419 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1420 {miim_end,} 1421 }, 1422 (struct phy_cmd[]) { /* startup */ 1423 /* Read the Status (2x to make sure link is right) */ 1424 {MIIM_STATUS, miim_read, NULL}, 1425 /* Auto-negotiate */ 1426 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1427 /* Read the status */ 1428 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1429 {miim_end,} 1430 }, 1431 (struct phy_cmd[]) { /* shutdown */ 1432 {miim_end,} 1433 }, 1434 }; 1435 1436 static struct phy_info phy_info_VSC8221 = { 1437 0xfc55, 1438 "Vitesse VSC8221", 1439 4, 1440 (struct phy_cmd[]) { /* config */ 1441 /* Configure some basic stuff */ 1442 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1443 {miim_end,} 1444 }, 1445 (struct phy_cmd[]) { /* startup */ 1446 /* Read the Status (2x to make sure link is right) */ 1447 {MIIM_STATUS, miim_read, NULL}, 1448 /* Auto-negotiate */ 1449 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1450 /* Read the status */ 1451 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1452 {miim_end,} 1453 }, 1454 (struct phy_cmd[]) { /* shutdown */ 1455 {miim_end,} 1456 }, 1457 }; 1458 1459 static struct phy_info phy_info_VSC8601 = { 1460 0x00007042, 1461 "Vitesse VSC8601", 1462 4, 1463 (struct phy_cmd[]) { /* config */ 1464 /* Override PHY config settings */ 1465 /* Configure some basic stuff */ 1466 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1467 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1468 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1469 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1470 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1471 #define VSC8101_SKEW \ 1472 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) 1473 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1474 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1475 #endif 1476 #endif 1477 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1478 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1479 {miim_end,} 1480 }, 1481 (struct phy_cmd[]) { /* startup */ 1482 /* Read the Status (2x to make sure link is right) */ 1483 {MIIM_STATUS, miim_read, NULL}, 1484 /* Auto-negotiate */ 1485 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1486 /* Read the status */ 1487 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1488 {miim_end,} 1489 }, 1490 (struct phy_cmd[]) { /* shutdown */ 1491 {miim_end,} 1492 }, 1493 }; 1494 1495 static struct phy_info phy_info_dm9161 = { 1496 0x0181b88, 1497 "Davicom DM9161E", 1498 4, 1499 (struct phy_cmd[]) { /* config */ 1500 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1501 /* Do not bypass the scrambler/descrambler */ 1502 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1503 /* Clear 10BTCSR to default */ 1504 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, 1505 /* Configure some basic stuff */ 1506 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1507 /* Restart Auto Negotiation */ 1508 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1509 {miim_end,} 1510 }, 1511 (struct phy_cmd[]) { /* startup */ 1512 /* Status is read once to clear old link state */ 1513 {MIIM_STATUS, miim_read, NULL}, 1514 /* Auto-negotiate */ 1515 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1516 /* Read the status */ 1517 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, 1518 {miim_end,} 1519 }, 1520 (struct phy_cmd[]) { /* shutdown */ 1521 {miim_end,} 1522 }, 1523 }; 1524 1525 /* a generic flavor. */ 1526 static struct phy_info phy_info_generic = { 1527 0, 1528 "Unknown/Generic PHY", 1529 32, 1530 (struct phy_cmd[]) { /* config */ 1531 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1532 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1533 {miim_end,} 1534 }, 1535 (struct phy_cmd[]) { /* startup */ 1536 {PHY_BMSR, miim_read, NULL}, 1537 {PHY_BMSR, miim_read, &mii_parse_sr}, 1538 {PHY_BMSR, miim_read, &mii_parse_link}, 1539 {miim_end,} 1540 }, 1541 (struct phy_cmd[]) { /* shutdown */ 1542 {miim_end,} 1543 } 1544 }; 1545 1546 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1547 { 1548 unsigned int speed; 1549 if (priv->link) { 1550 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1551 1552 switch (speed) { 1553 case MIIM_LXT971_SR2_10HDX: 1554 priv->speed = 10; 1555 priv->duplexity = 0; 1556 break; 1557 case MIIM_LXT971_SR2_10FDX: 1558 priv->speed = 10; 1559 priv->duplexity = 1; 1560 break; 1561 case MIIM_LXT971_SR2_100HDX: 1562 priv->speed = 100; 1563 priv->duplexity = 0; 1564 break; 1565 default: 1566 priv->speed = 100; 1567 priv->duplexity = 1; 1568 } 1569 } else { 1570 priv->speed = 0; 1571 priv->duplexity = 0; 1572 } 1573 1574 return 0; 1575 } 1576 1577 static struct phy_info phy_info_lxt971 = { 1578 0x0001378e, 1579 "LXT971", 1580 4, 1581 (struct phy_cmd[]) { /* config */ 1582 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1583 {miim_end,} 1584 }, 1585 (struct phy_cmd[]) { /* startup - enable interrupts */ 1586 /* { 0x12, 0x00f2, NULL }, */ 1587 {MIIM_STATUS, miim_read, NULL}, 1588 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1589 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1590 {miim_end,} 1591 }, 1592 (struct phy_cmd[]) { /* shutdown - disable interrupts */ 1593 {miim_end,} 1594 }, 1595 }; 1596 1597 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1598 * information 1599 */ 1600 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1601 { 1602 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1603 1604 case MIIM_DP83865_SPD_1000: 1605 priv->speed = 1000; 1606 break; 1607 1608 case MIIM_DP83865_SPD_100: 1609 priv->speed = 100; 1610 break; 1611 1612 default: 1613 priv->speed = 10; 1614 break; 1615 1616 } 1617 1618 if (mii_reg & MIIM_DP83865_DPX_FULL) 1619 priv->duplexity = 1; 1620 else 1621 priv->duplexity = 0; 1622 1623 return 0; 1624 } 1625 1626 static struct phy_info phy_info_dp83865 = { 1627 0x20005c7, 1628 "NatSemi DP83865", 1629 4, 1630 (struct phy_cmd[]) { /* config */ 1631 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1632 {miim_end,} 1633 }, 1634 (struct phy_cmd[]) { /* startup */ 1635 /* Status is read once to clear old link state */ 1636 {MIIM_STATUS, miim_read, NULL}, 1637 /* Auto-negotiate */ 1638 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1639 /* Read the link and auto-neg status */ 1640 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, 1641 {miim_end,} 1642 }, 1643 (struct phy_cmd[]) { /* shutdown */ 1644 {miim_end,} 1645 }, 1646 }; 1647 1648 static struct phy_info phy_info_rtl8211b = { 1649 0x001cc91, 1650 "RealTek RTL8211B", 1651 4, 1652 (struct phy_cmd[]) { /* config */ 1653 /* Reset and configure the PHY */ 1654 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1655 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1656 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1657 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1658 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1659 {miim_end,} 1660 }, 1661 (struct phy_cmd[]) { /* startup */ 1662 /* Status is read once to clear old link state */ 1663 {MIIM_STATUS, miim_read, NULL}, 1664 /* Auto-negotiate */ 1665 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1666 /* Read the status */ 1667 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1668 {miim_end,} 1669 }, 1670 (struct phy_cmd[]) { /* shutdown */ 1671 {miim_end,} 1672 }, 1673 }; 1674 1675 static struct phy_info *phy_info[] = { 1676 &phy_info_cis8204, 1677 &phy_info_cis8201, 1678 &phy_info_BCM5461S, 1679 &phy_info_BCM5464S, 1680 &phy_info_BCM5482S, 1681 &phy_info_M88E1011S, 1682 &phy_info_M88E1111S, 1683 &phy_info_M88E1118, 1684 &phy_info_M88E1121R, 1685 &phy_info_M88E1145, 1686 &phy_info_M88E1149S, 1687 &phy_info_dm9161, 1688 &phy_info_lxt971, 1689 &phy_info_VSC8211, 1690 &phy_info_VSC8244, 1691 &phy_info_VSC8601, 1692 &phy_info_VSC8641, 1693 &phy_info_VSC8221, 1694 &phy_info_dp83865, 1695 &phy_info_rtl8211b, 1696 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ 1697 NULL 1698 }; 1699 1700 /* Grab the identifier of the device's PHY, and search through 1701 * all of the known PHYs to see if one matches. If so, return 1702 * it, if not, return NULL 1703 */ 1704 static struct phy_info *get_phy_info(struct eth_device *dev) 1705 { 1706 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1707 uint phy_reg, phy_ID; 1708 int i; 1709 struct phy_info *theInfo = NULL; 1710 1711 /* Grab the bits from PHYIR1, and put them in the upper half */ 1712 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1713 phy_ID = (phy_reg & 0xffff) << 16; 1714 1715 /* Grab the bits from PHYIR2, and put them in the lower half */ 1716 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1717 phy_ID |= (phy_reg & 0xffff); 1718 1719 /* loop through all the known PHY types, and find one that */ 1720 /* matches the ID we read from the PHY. */ 1721 for (i = 0; phy_info[i]; i++) { 1722 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1723 theInfo = phy_info[i]; 1724 break; 1725 } 1726 } 1727 1728 if (theInfo == &phy_info_generic) { 1729 printf("%s: No support for PHY id %x; assuming generic\n", 1730 dev->name, phy_ID); 1731 } else { 1732 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1733 } 1734 1735 return theInfo; 1736 } 1737 1738 /* Execute the given series of commands on the given device's 1739 * PHY, running functions as necessary 1740 */ 1741 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1742 { 1743 int i; 1744 uint result; 1745 volatile tsec_mdio_t *phyregs = priv->phyregs; 1746 1747 phyregs->miimcfg = MIIMCFG_RESET; 1748 1749 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1750 1751 while (phyregs->miimind & MIIMIND_BUSY) ; 1752 1753 for (i = 0; cmd->mii_reg != miim_end; i++) { 1754 if (cmd->mii_data == miim_read) { 1755 result = read_phy_reg(priv, cmd->mii_reg); 1756 1757 if (cmd->funct != NULL) 1758 (*(cmd->funct)) (result, priv); 1759 1760 } else { 1761 if (cmd->funct != NULL) 1762 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1763 else 1764 result = cmd->mii_data; 1765 1766 write_phy_reg(priv, cmd->mii_reg, result); 1767 1768 } 1769 cmd++; 1770 } 1771 } 1772 1773 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1774 && !defined(BITBANGMII) 1775 1776 /* 1777 * Read a MII PHY register. 1778 * 1779 * Returns: 1780 * 0 on success 1781 */ 1782 static int tsec_miiphy_read(char *devname, unsigned char addr, 1783 unsigned char reg, unsigned short *value) 1784 { 1785 unsigned short ret; 1786 struct tsec_private *priv = privlist[0]; 1787 1788 if (NULL == priv) { 1789 printf("Can't read PHY at address %d\n", addr); 1790 return -1; 1791 } 1792 1793 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1794 *value = ret; 1795 1796 return 0; 1797 } 1798 1799 /* 1800 * Write a MII PHY register. 1801 * 1802 * Returns: 1803 * 0 on success 1804 */ 1805 static int tsec_miiphy_write(char *devname, unsigned char addr, 1806 unsigned char reg, unsigned short value) 1807 { 1808 struct tsec_private *priv = privlist[0]; 1809 1810 if (NULL == priv) { 1811 printf("Can't write PHY at address %d\n", addr); 1812 return -1; 1813 } 1814 1815 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1816 1817 return 0; 1818 } 1819 1820 #endif 1821 1822 #ifdef CONFIG_MCAST_TFTP 1823 1824 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1825 1826 /* Set the appropriate hash bit for the given addr */ 1827 1828 /* The algorithm works like so: 1829 * 1) Take the Destination Address (ie the multicast address), and 1830 * do a CRC on it (little endian), and reverse the bits of the 1831 * result. 1832 * 2) Use the 8 most significant bits as a hash into a 256-entry 1833 * table. The table is controlled through 8 32-bit registers: 1834 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1835 * gaddr7. This means that the 3 most significant bits in the 1836 * hash index which gaddr register to use, and the 5 other bits 1837 * indicate which bit (assuming an IBM numbering scheme, which 1838 * for PowerPC (tm) is usually the case) in the tregister holds 1839 * the entry. */ 1840 static int 1841 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1842 { 1843 struct tsec_private *priv = privlist[1]; 1844 volatile tsec_t *regs = priv->regs; 1845 volatile u32 *reg_array, value; 1846 u8 result, whichbit, whichreg; 1847 1848 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1849 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1850 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1851 value = (1 << (31-whichbit)); 1852 1853 reg_array = &(regs->hash.gaddr0); 1854 1855 if (set) { 1856 reg_array[whichreg] |= value; 1857 } else { 1858 reg_array[whichreg] &= ~value; 1859 } 1860 return 0; 1861 } 1862 #endif /* Multicast TFTP ? */ 1863