1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. 5 * (C) Copyright 2003, Motorola, Inc. 6 * author Andy Fleming 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <command.h> 16 #include <tsec.h> 17 #include <fsl_mdio.h> 18 #include <asm/errno.h> 19 #include <asm/processor.h> 20 #include <asm/io.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define TX_BUF_CNT 2 25 26 static uint rx_idx; /* index of the current RX buffer */ 27 static uint tx_idx; /* index of the current TX buffer */ 28 29 #ifdef __GNUC__ 30 static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); 31 static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); 32 33 #else 34 #error "rtx must be 64-bit aligned" 35 #endif 36 37 static int tsec_send(struct eth_device *dev, void *packet, int length); 38 39 /* Default initializations for TSEC controllers. */ 40 41 static struct tsec_info_struct tsec_info[] = { 42 #ifdef CONFIG_TSEC1 43 STD_TSEC_INFO(1), /* TSEC1 */ 44 #endif 45 #ifdef CONFIG_TSEC2 46 STD_TSEC_INFO(2), /* TSEC2 */ 47 #endif 48 #ifdef CONFIG_MPC85XX_FEC 49 { 50 .regs = TSEC_GET_REGS(2, 0x2000), 51 .devname = CONFIG_MPC85XX_FEC_NAME, 52 .phyaddr = FEC_PHY_ADDR, 53 .flags = FEC_FLAGS, 54 .mii_devname = DEFAULT_MII_NAME 55 }, /* FEC */ 56 #endif 57 #ifdef CONFIG_TSEC3 58 STD_TSEC_INFO(3), /* TSEC3 */ 59 #endif 60 #ifdef CONFIG_TSEC4 61 STD_TSEC_INFO(4), /* TSEC4 */ 62 #endif 63 }; 64 65 #define TBIANA_SETTINGS ( \ 66 TBIANA_ASYMMETRIC_PAUSE \ 67 | TBIANA_SYMMETRIC_PAUSE \ 68 | TBIANA_FULL_DUPLEX \ 69 ) 70 71 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 72 #ifndef CONFIG_TSEC_TBICR_SETTINGS 73 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 74 TBICR_PHY_RESET \ 75 | TBICR_ANEG_ENABLE \ 76 | TBICR_FULL_DUPLEX \ 77 | TBICR_SPEED1_SET \ 78 ) 79 #endif /* CONFIG_TSEC_TBICR_SETTINGS */ 80 81 /* Configure the TBI for SGMII operation */ 82 static void tsec_configure_serdes(struct tsec_private *priv) 83 { 84 /* 85 * Access TBI PHY registers at given TSEC register offset as opposed 86 * to the register offset used for external PHY accesses 87 */ 88 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 89 0, TBI_ANA, TBIANA_SETTINGS); 90 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 91 0, TBI_TBICON, TBICON_CLK_SELECT); 92 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 93 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); 94 } 95 96 #ifdef CONFIG_MCAST_TFTP 97 98 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 99 100 /* Set the appropriate hash bit for the given addr */ 101 102 /* 103 * The algorithm works like so: 104 * 1) Take the Destination Address (ie the multicast address), and 105 * do a CRC on it (little endian), and reverse the bits of the 106 * result. 107 * 2) Use the 8 most significant bits as a hash into a 256-entry 108 * table. The table is controlled through 8 32-bit registers: 109 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry 110 * 255. This means that the 3 most significant bits in the 111 * hash index which gaddr register to use, and the 5 other bits 112 * indicate which bit (assuming an IBM numbering scheme, which 113 * for PowerPC (tm) is usually the case) in the register holds 114 * the entry. 115 */ 116 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) 117 { 118 struct tsec_private *priv = (struct tsec_private *)dev->priv; 119 struct tsec __iomem *regs = priv->regs; 120 u32 result, value; 121 u8 whichbit, whichreg; 122 123 result = ether_crc(MAC_ADDR_LEN, mcast_mac); 124 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ 125 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */ 126 127 value = 1 << (31-whichbit); 128 129 if (set) 130 setbits_be32(®s->hash.gaddr0 + whichreg, value); 131 else 132 clrbits_be32(®s->hash.gaddr0 + whichreg, value); 133 134 return 0; 135 } 136 #endif /* Multicast TFTP ? */ 137 138 /* 139 * Initialized required registers to appropriate values, zeroing 140 * those we don't care about (unless zero is bad, in which case, 141 * choose a more appropriate value) 142 */ 143 static void init_registers(struct tsec __iomem *regs) 144 { 145 /* Clear IEVENT */ 146 out_be32(®s->ievent, IEVENT_INIT_CLEAR); 147 148 out_be32(®s->imask, IMASK_INIT_CLEAR); 149 150 out_be32(®s->hash.iaddr0, 0); 151 out_be32(®s->hash.iaddr1, 0); 152 out_be32(®s->hash.iaddr2, 0); 153 out_be32(®s->hash.iaddr3, 0); 154 out_be32(®s->hash.iaddr4, 0); 155 out_be32(®s->hash.iaddr5, 0); 156 out_be32(®s->hash.iaddr6, 0); 157 out_be32(®s->hash.iaddr7, 0); 158 159 out_be32(®s->hash.gaddr0, 0); 160 out_be32(®s->hash.gaddr1, 0); 161 out_be32(®s->hash.gaddr2, 0); 162 out_be32(®s->hash.gaddr3, 0); 163 out_be32(®s->hash.gaddr4, 0); 164 out_be32(®s->hash.gaddr5, 0); 165 out_be32(®s->hash.gaddr6, 0); 166 out_be32(®s->hash.gaddr7, 0); 167 168 out_be32(®s->rctrl, 0x00000000); 169 170 /* Init RMON mib registers */ 171 memset((void *)®s->rmon, 0, sizeof(regs->rmon)); 172 173 out_be32(®s->rmon.cam1, 0xffffffff); 174 out_be32(®s->rmon.cam2, 0xffffffff); 175 176 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); 177 178 out_be32(®s->minflr, MINFLR_INIT_SETTINGS); 179 180 out_be32(®s->attr, ATTR_INIT_SETTINGS); 181 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); 182 183 } 184 185 /* 186 * Configure maccfg2 based on negotiated speed and duplex 187 * reported by PHY handling code 188 */ 189 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) 190 { 191 struct tsec __iomem *regs = priv->regs; 192 u32 ecntrl, maccfg2; 193 194 if (!phydev->link) { 195 printf("%s: No link.\n", phydev->dev->name); 196 return; 197 } 198 199 /* clear all bits relative with interface mode */ 200 ecntrl = in_be32(®s->ecntrl); 201 ecntrl &= ~ECNTRL_R100; 202 203 maccfg2 = in_be32(®s->maccfg2); 204 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); 205 206 if (phydev->duplex) 207 maccfg2 |= MACCFG2_FULL_DUPLEX; 208 209 switch (phydev->speed) { 210 case 1000: 211 maccfg2 |= MACCFG2_GMII; 212 break; 213 case 100: 214 case 10: 215 maccfg2 |= MACCFG2_MII; 216 217 /* 218 * Set R100 bit in all modes although 219 * it is only used in RGMII mode 220 */ 221 if (phydev->speed == 100) 222 ecntrl |= ECNTRL_R100; 223 break; 224 default: 225 printf("%s: Speed was bad\n", phydev->dev->name); 226 break; 227 } 228 229 out_be32(®s->ecntrl, ecntrl); 230 out_be32(®s->maccfg2, maccfg2); 231 232 printf("Speed: %d, %s duplex%s\n", phydev->speed, 233 (phydev->duplex) ? "full" : "half", 234 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 235 } 236 237 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 238 /* 239 * When MACCFG1[Rx_EN] is enabled during system boot as part 240 * of the eTSEC port initialization sequence, 241 * the eTSEC Rx logic may not be properly initialized. 242 */ 243 void redundant_init(struct eth_device *dev) 244 { 245 struct tsec_private *priv = dev->priv; 246 struct tsec __iomem *regs = priv->regs; 247 uint t, count = 0; 248 int fail = 1; 249 static const u8 pkt[] = { 250 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, 251 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, 252 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, 253 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, 254 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, 255 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 256 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 257 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 258 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 259 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 260 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 261 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 262 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 263 0x71, 0x72}; 264 265 /* Enable promiscuous mode */ 266 setbits_be32(®s->rctrl, 0x8); 267 /* Enable loopback mode */ 268 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 269 /* Enable transmit and receive */ 270 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 271 272 /* Tell the DMA it is clear to go */ 273 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 274 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 275 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 276 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 277 278 do { 279 uint16_t status; 280 tsec_send(dev, (void *)pkt, sizeof(pkt)); 281 282 /* Wait for buffer to be received */ 283 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { 284 if (t >= 10 * TOUT_LOOP) { 285 printf("%s: tsec: rx error\n", dev->name); 286 break; 287 } 288 } 289 290 if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt))) 291 fail = 0; 292 293 out_be16(&rxbd[rx_idx].length, 0); 294 status = RXBD_EMPTY; 295 if ((rx_idx + 1) == PKTBUFSRX) 296 status |= RXBD_WRAP; 297 out_be16(&rxbd[rx_idx].status, status); 298 rx_idx = (rx_idx + 1) % PKTBUFSRX; 299 300 if (in_be32(®s->ievent) & IEVENT_BSY) { 301 out_be32(®s->ievent, IEVENT_BSY); 302 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 303 } 304 if (fail) { 305 printf("loopback recv packet error!\n"); 306 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); 307 udelay(1000); 308 setbits_be32(®s->maccfg1, MACCFG1_RX_EN); 309 } 310 } while ((count++ < 4) && (fail == 1)); 311 312 if (fail) 313 panic("eTSEC init fail!\n"); 314 /* Disable promiscuous mode */ 315 clrbits_be32(®s->rctrl, 0x8); 316 /* Disable loopback mode */ 317 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 318 } 319 #endif 320 321 /* 322 * Set up the buffers and their descriptors, and bring up the 323 * interface 324 */ 325 static void startup_tsec(struct eth_device *dev) 326 { 327 struct tsec_private *priv = (struct tsec_private *)dev->priv; 328 struct tsec __iomem *regs = priv->regs; 329 uint16_t status; 330 int i; 331 332 /* reset the indices to zero */ 333 rx_idx = 0; 334 tx_idx = 0; 335 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 336 uint svr; 337 #endif 338 339 /* Point to the buffer descriptors */ 340 out_be32(®s->tbase, (u32)&txbd[0]); 341 out_be32(®s->rbase, (u32)&rxbd[0]); 342 343 /* Initialize the Rx Buffer descriptors */ 344 for (i = 0; i < PKTBUFSRX; i++) { 345 out_be16(&rxbd[i].status, RXBD_EMPTY); 346 out_be16(&rxbd[i].length, 0); 347 out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]); 348 } 349 status = in_be16(&rxbd[PKTBUFSRX - 1].status); 350 out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); 351 352 /* Initialize the TX Buffer Descriptors */ 353 for (i = 0; i < TX_BUF_CNT; i++) { 354 out_be16(&txbd[i].status, 0); 355 out_be16(&txbd[i].length, 0); 356 out_be32(&txbd[i].bufptr, 0); 357 } 358 status = in_be16(&txbd[TX_BUF_CNT - 1].status); 359 out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); 360 361 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 362 svr = get_svr(); 363 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 364 redundant_init(dev); 365 #endif 366 /* Enable Transmit and Receive */ 367 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 368 369 /* Tell the DMA it is clear to go */ 370 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 371 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 372 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 373 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 374 } 375 376 /* 377 * This returns the status bits of the device. The return value 378 * is never checked, and this is what the 8260 driver did, so we 379 * do the same. Presumably, this would be zero if there were no 380 * errors 381 */ 382 static int tsec_send(struct eth_device *dev, void *packet, int length) 383 { 384 struct tsec_private *priv = (struct tsec_private *)dev->priv; 385 struct tsec __iomem *regs = priv->regs; 386 uint16_t status; 387 int result = 0; 388 int i; 389 390 /* Find an empty buffer descriptor */ 391 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { 392 if (i >= TOUT_LOOP) { 393 debug("%s: tsec: tx buffers full\n", dev->name); 394 return result; 395 } 396 } 397 398 out_be32(&txbd[tx_idx].bufptr, (u32)packet); 399 out_be16(&txbd[tx_idx].length, length); 400 status = in_be16(&txbd[tx_idx].status); 401 out_be16(&txbd[tx_idx].status, status | 402 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); 403 404 /* Tell the DMA to go */ 405 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 406 407 /* Wait for buffer to be transmitted */ 408 for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { 409 if (i >= TOUT_LOOP) { 410 debug("%s: tsec: tx error\n", dev->name); 411 return result; 412 } 413 } 414 415 tx_idx = (tx_idx + 1) % TX_BUF_CNT; 416 result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; 417 418 return result; 419 } 420 421 static int tsec_recv(struct eth_device *dev) 422 { 423 struct tsec_private *priv = (struct tsec_private *)dev->priv; 424 struct tsec __iomem *regs = priv->regs; 425 426 while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { 427 int length = in_be16(&rxbd[rx_idx].length); 428 uint16_t status = in_be16(&rxbd[rx_idx].status); 429 430 /* Send the packet up if there were no errors */ 431 if (!(status & RXBD_STATS)) 432 net_process_received_packet(net_rx_packets[rx_idx], 433 length - 4); 434 else 435 printf("Got error %x\n", (status & RXBD_STATS)); 436 437 out_be16(&rxbd[rx_idx].length, 0); 438 439 status = RXBD_EMPTY; 440 /* Set the wrap bit if this is the last element in the list */ 441 if ((rx_idx + 1) == PKTBUFSRX) 442 status |= RXBD_WRAP; 443 out_be16(&rxbd[rx_idx].status, status); 444 445 rx_idx = (rx_idx + 1) % PKTBUFSRX; 446 } 447 448 if (in_be32(®s->ievent) & IEVENT_BSY) { 449 out_be32(®s->ievent, IEVENT_BSY); 450 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 451 } 452 453 return -1; 454 } 455 456 /* Stop the interface */ 457 static void tsec_halt(struct eth_device *dev) 458 { 459 struct tsec_private *priv = (struct tsec_private *)dev->priv; 460 struct tsec __iomem *regs = priv->regs; 461 462 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 463 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 464 465 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) 466 != (IEVENT_GRSC | IEVENT_GTSC)) 467 ; 468 469 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); 470 471 /* Shut down the PHY, as needed */ 472 phy_shutdown(priv->phydev); 473 } 474 475 /* 476 * Initializes data structures and registers for the controller, 477 * and brings the interface up. Returns the link status, meaning 478 * that it returns success if the link is up, failure otherwise. 479 * This allows U-Boot to find the first active controller. 480 */ 481 static int tsec_init(struct eth_device *dev, bd_t * bd) 482 { 483 struct tsec_private *priv = (struct tsec_private *)dev->priv; 484 struct tsec __iomem *regs = priv->regs; 485 u32 tempval; 486 int ret; 487 488 /* Make sure the controller is stopped */ 489 tsec_halt(dev); 490 491 /* Init MACCFG2. Defaults to GMII */ 492 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); 493 494 /* Init ECNTRL */ 495 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); 496 497 /* 498 * Copy the station address into the address registers. 499 * For a station address of 0x12345678ABCD in transmission 500 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 501 * MACnADDR2 is set to 0x34120000. 502 */ 503 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | 504 (dev->enetaddr[3] << 8) | dev->enetaddr[2]; 505 506 out_be32(®s->macstnaddr1, tempval); 507 508 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); 509 510 out_be32(®s->macstnaddr2, tempval); 511 512 /* Clear out (for the most part) the other registers */ 513 init_registers(regs); 514 515 /* Ready the device for tx/rx */ 516 startup_tsec(dev); 517 518 /* Start up the PHY */ 519 ret = phy_startup(priv->phydev); 520 if (ret) { 521 printf("Could not initialize PHY %s\n", 522 priv->phydev->dev->name); 523 return ret; 524 } 525 526 adjust_link(priv, priv->phydev); 527 528 /* If there's no link, fail */ 529 return priv->phydev->link ? 0 : -1; 530 } 531 532 static phy_interface_t tsec_get_interface(struct tsec_private *priv) 533 { 534 struct tsec __iomem *regs = priv->regs; 535 u32 ecntrl; 536 537 ecntrl = in_be32(®s->ecntrl); 538 539 if (ecntrl & ECNTRL_SGMII_MODE) 540 return PHY_INTERFACE_MODE_SGMII; 541 542 if (ecntrl & ECNTRL_TBI_MODE) { 543 if (ecntrl & ECNTRL_REDUCED_MODE) 544 return PHY_INTERFACE_MODE_RTBI; 545 else 546 return PHY_INTERFACE_MODE_TBI; 547 } 548 549 if (ecntrl & ECNTRL_REDUCED_MODE) { 550 if (ecntrl & ECNTRL_REDUCED_MII_MODE) 551 return PHY_INTERFACE_MODE_RMII; 552 else { 553 phy_interface_t interface = priv->interface; 554 555 /* 556 * This isn't autodetected, so it must 557 * be set by the platform code. 558 */ 559 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || 560 (interface == PHY_INTERFACE_MODE_RGMII_TXID) || 561 (interface == PHY_INTERFACE_MODE_RGMII_RXID)) 562 return interface; 563 564 return PHY_INTERFACE_MODE_RGMII; 565 } 566 } 567 568 if (priv->flags & TSEC_GIGABIT) 569 return PHY_INTERFACE_MODE_GMII; 570 571 return PHY_INTERFACE_MODE_MII; 572 } 573 574 /* 575 * Discover which PHY is attached to the device, and configure it 576 * properly. If the PHY is not recognized, then return 0 577 * (failure). Otherwise, return 1 578 */ 579 static int init_phy(struct eth_device *dev) 580 { 581 struct tsec_private *priv = (struct tsec_private *)dev->priv; 582 struct phy_device *phydev; 583 struct tsec __iomem *regs = priv->regs; 584 u32 supported = (SUPPORTED_10baseT_Half | 585 SUPPORTED_10baseT_Full | 586 SUPPORTED_100baseT_Half | 587 SUPPORTED_100baseT_Full); 588 589 if (priv->flags & TSEC_GIGABIT) 590 supported |= SUPPORTED_1000baseT_Full; 591 592 /* Assign a Physical address to the TBI */ 593 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); 594 595 priv->interface = tsec_get_interface(priv); 596 597 if (priv->interface == PHY_INTERFACE_MODE_SGMII) 598 tsec_configure_serdes(priv); 599 600 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 601 if (!phydev) 602 return 0; 603 604 phydev->supported &= supported; 605 phydev->advertising = phydev->supported; 606 607 priv->phydev = phydev; 608 609 phy_config(phydev); 610 611 return 1; 612 } 613 614 /* 615 * Initialize device structure. Returns success if PHY 616 * initialization succeeded (i.e. if it recognizes the PHY) 617 */ 618 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) 619 { 620 struct eth_device *dev; 621 int i; 622 struct tsec_private *priv; 623 624 dev = (struct eth_device *)malloc(sizeof *dev); 625 626 if (NULL == dev) 627 return 0; 628 629 memset(dev, 0, sizeof *dev); 630 631 priv = (struct tsec_private *)malloc(sizeof(*priv)); 632 633 if (NULL == priv) 634 return 0; 635 636 priv->regs = tsec_info->regs; 637 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 638 639 priv->phyaddr = tsec_info->phyaddr; 640 priv->flags = tsec_info->flags; 641 642 sprintf(dev->name, tsec_info->devname); 643 priv->interface = tsec_info->interface; 644 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); 645 dev->iobase = 0; 646 dev->priv = priv; 647 dev->init = tsec_init; 648 dev->halt = tsec_halt; 649 dev->send = tsec_send; 650 dev->recv = tsec_recv; 651 #ifdef CONFIG_MCAST_TFTP 652 dev->mcast = tsec_mcast_addr; 653 #endif 654 655 /* Tell U-Boot to get the addr from the env */ 656 for (i = 0; i < 6; i++) 657 dev->enetaddr[i] = 0; 658 659 eth_register(dev); 660 661 /* Reset the MAC */ 662 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 663 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 664 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 665 666 /* Try to initialize PHY here, and return */ 667 return init_phy(dev); 668 } 669 670 /* 671 * Initialize all the TSEC devices 672 * 673 * Returns the number of TSEC devices that were initialized 674 */ 675 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 676 { 677 int i; 678 int ret, count = 0; 679 680 for (i = 0; i < num; i++) { 681 ret = tsec_initialize(bis, &tsecs[i]); 682 if (ret > 0) 683 count += ret; 684 } 685 686 return count; 687 } 688 689 int tsec_standard_init(bd_t *bis) 690 { 691 struct fsl_pq_mdio_info info; 692 693 info.regs = TSEC_GET_MDIO_REGS_BASE(1); 694 info.name = DEFAULT_MII_NAME; 695 696 fsl_pq_mdio_init(bis, &info); 697 698 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 699 } 700