1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2009 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <asm/errno.h> 21 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, 48 volatile void *packet, int length); 49 static int tsec_recv(struct eth_device *dev); 50 static int tsec_init(struct eth_device *dev, bd_t * bd); 51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 static struct phy_info *get_phy_info(struct eth_device *dev); 59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 62 && !defined(BITBANGMII) 63 static int tsec_miiphy_write(char *devname, unsigned char addr, 64 unsigned char reg, unsigned short value); 65 static int tsec_miiphy_read(char *devname, unsigned char addr, 66 unsigned char reg, unsigned short *value); 67 #endif 68 #ifdef CONFIG_MCAST_TFTP 69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 70 #endif 71 72 /* Default initializations for TSEC controllers. */ 73 74 static struct tsec_info_struct tsec_info[] = { 75 #ifdef CONFIG_TSEC1 76 STD_TSEC_INFO(1), /* TSEC1 */ 77 #endif 78 #ifdef CONFIG_TSEC2 79 STD_TSEC_INFO(2), /* TSEC2 */ 80 #endif 81 #ifdef CONFIG_MPC85XX_FEC 82 { 83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), 85 .devname = CONFIG_MPC85XX_FEC_NAME, 86 .phyaddr = FEC_PHY_ADDR, 87 .flags = FEC_FLAGS 88 }, /* FEC */ 89 #endif 90 #ifdef CONFIG_TSEC3 91 STD_TSEC_INFO(3), /* TSEC3 */ 92 #endif 93 #ifdef CONFIG_TSEC4 94 STD_TSEC_INFO(4), /* TSEC4 */ 95 #endif 96 }; 97 98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 99 { 100 int i; 101 102 for (i = 0; i < num; i++) 103 tsec_initialize(bis, &tsecs[i]); 104 105 return 0; 106 } 107 108 int tsec_standard_init(bd_t *bis) 109 { 110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 111 } 112 113 /* Initialize device structure. Returns success if PHY 114 * initialization succeeded (i.e. if it recognizes the PHY) 115 */ 116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 117 { 118 struct eth_device *dev; 119 int i; 120 struct tsec_private *priv; 121 122 dev = (struct eth_device *)malloc(sizeof *dev); 123 124 if (NULL == dev) 125 return 0; 126 127 memset(dev, 0, sizeof *dev); 128 129 priv = (struct tsec_private *)malloc(sizeof(*priv)); 130 131 if (NULL == priv) 132 return 0; 133 134 privlist[num_tsecs++] = priv; 135 priv->regs = tsec_info->regs; 136 priv->phyregs = tsec_info->miiregs; 137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 163 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 165 && !defined(BITBANGMII) 166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 167 #endif 168 169 /* Try to initialize PHY here, and return */ 170 return init_phy(dev); 171 } 172 173 /* Initializes data structures and registers for the controller, 174 * and brings the interface up. Returns the link status, meaning 175 * that it returns success if the link is up, failure otherwise. 176 * This allows u-boot to find the first active controller. 177 */ 178 static int tsec_init(struct eth_device *dev, bd_t * bd) 179 { 180 uint tempval; 181 char tmpbuf[MAC_ADDR_LEN]; 182 int i; 183 struct tsec_private *priv = (struct tsec_private *)dev->priv; 184 volatile tsec_t *regs = priv->regs; 185 186 /* Make sure the controller is stopped */ 187 tsec_halt(dev); 188 189 /* Init MACCFG2. Defaults to GMII */ 190 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 191 192 /* Init ECNTRL */ 193 regs->ecntrl = ECNTRL_INIT_SETTINGS; 194 195 /* Copy the station address into the address registers. 196 * Backwards, because little endian MACS are dumb */ 197 for (i = 0; i < MAC_ADDR_LEN; i++) { 198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 199 } 200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 201 tmpbuf[3]; 202 203 regs->macstnaddr1 = tempval; 204 205 tempval = *((uint *) (tmpbuf + 4)); 206 207 regs->macstnaddr2 = tempval; 208 209 /* reset the indices to zero */ 210 rxIdx = 0; 211 txIdx = 0; 212 213 /* Clear out (for the most part) the other registers */ 214 init_registers(regs); 215 216 /* Ready the device for tx/rx */ 217 startup_tsec(dev); 218 219 /* If there's no link, fail */ 220 return (priv->link ? 0 : -1); 221 } 222 223 /* Writes the given phy's reg with value, using the specified MDIO regs */ 224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, 225 uint reg, uint value) 226 { 227 int timeout = 1000000; 228 229 phyregs->miimadd = (addr << 8) | reg; 230 phyregs->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 238 /* Provide the default behavior of writing the PHY of this ethernet device */ 239 #define write_phy_reg(priv, regnum, value) \ 240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 241 242 /* Reads register regnum on the device's PHY through the 243 * specified registers. It lowers and raises the read 244 * command, and waits for the data to become valid (miimind 245 * notvalid bit cleared), and the bus to cease activity (miimind 246 * busy bit cleared), and then returns the value 247 */ 248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, 249 uint phyid, uint regnum) 250 { 251 uint value; 252 253 /* Put the address of the phy, and the register 254 * number into MIIMADD */ 255 phyregs->miimadd = (phyid << 8) | regnum; 256 257 /* Clear the command register, and wait */ 258 phyregs->miimcom = 0; 259 asm("sync"); 260 261 /* Initiate a read command, and wait */ 262 phyregs->miimcom = MIIM_READ_COMMAND; 263 asm("sync"); 264 265 /* Wait for the the indication that the read is done */ 266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 267 268 /* Grab the value read from the PHY */ 269 value = phyregs->miimstat; 270 271 return value; 272 } 273 274 /* #define to provide old read_phy_reg functionality without duplicating code */ 275 #define read_phy_reg(priv,regnum) \ 276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 277 278 #define TBIANA_SETTINGS ( \ 279 TBIANA_ASYMMETRIC_PAUSE \ 280 | TBIANA_SYMMETRIC_PAUSE \ 281 | TBIANA_FULL_DUPLEX \ 282 ) 283 284 /* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 285 #define TBICR_SETTINGS ( \ 286 TBICR_PHY_RESET \ 287 | TBICR_FULL_DUPLEX \ 288 | TBICR_SPEED1_SET \ 289 ) 290 291 /* Configure the TBI for SGMII operation */ 292 static void tsec_configure_serdes(struct tsec_private *priv) 293 { 294 /* Access TBI PHY registers at given TSEC register offset as opposed 295 * to the register offset used for external PHY accesses */ 296 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, 297 TBIANA_SETTINGS); 298 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, 299 TBICON_CLK_SELECT); 300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, 301 TBICR_SETTINGS); 302 } 303 304 /* Discover which PHY is attached to the device, and configure it 305 * properly. If the PHY is not recognized, then return 0 306 * (failure). Otherwise, return 1 307 */ 308 static int init_phy(struct eth_device *dev) 309 { 310 struct tsec_private *priv = (struct tsec_private *)dev->priv; 311 struct phy_info *curphy; 312 volatile tsec_t *regs = priv->regs; 313 314 /* Assign a Physical address to the TBI */ 315 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 316 asm("sync"); 317 318 /* Reset MII (due to new addresses) */ 319 priv->phyregs->miimcfg = MIIMCFG_RESET; 320 asm("sync"); 321 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 322 asm("sync"); 323 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 324 325 /* Get the cmd structure corresponding to the attached 326 * PHY */ 327 curphy = get_phy_info(dev); 328 329 if (curphy == NULL) { 330 priv->phyinfo = NULL; 331 printf("%s: No PHY found\n", dev->name); 332 333 return 0; 334 } 335 336 if (regs->ecntrl & ECNTRL_SGMII_MODE) 337 tsec_configure_serdes(priv); 338 339 priv->phyinfo = curphy; 340 341 phy_run_commands(priv, priv->phyinfo->config); 342 343 return 1; 344 } 345 346 /* 347 * Returns which value to write to the control register. 348 * For 10/100, the value is slightly different 349 */ 350 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 351 { 352 if (priv->flags & TSEC_GIGABIT) 353 return MIIM_CONTROL_INIT; 354 else 355 return MIIM_CR_INIT; 356 } 357 358 /* 359 * Wait for auto-negotiation to complete, then determine link 360 */ 361 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 362 { 363 /* 364 * Wait if the link is up, and autonegotiation is in progress 365 * (ie - we're capable and it's not done) 366 */ 367 mii_reg = read_phy_reg(priv, MIIM_STATUS); 368 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 369 int i = 0; 370 371 puts("Waiting for PHY auto negotiation to complete"); 372 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 373 /* 374 * Timeout reached ? 375 */ 376 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 377 puts(" TIMEOUT !\n"); 378 priv->link = 0; 379 return 0; 380 } 381 382 if (ctrlc()) { 383 puts("user interrupt!\n"); 384 priv->link = 0; 385 return -EINTR; 386 } 387 388 if ((i++ % 1000) == 0) { 389 putc('.'); 390 } 391 udelay(1000); /* 1 ms */ 392 mii_reg = read_phy_reg(priv, MIIM_STATUS); 393 } 394 puts(" done\n"); 395 396 /* Link status bit is latched low, read it again */ 397 mii_reg = read_phy_reg(priv, MIIM_STATUS); 398 399 udelay(500000); /* another 500 ms (results in faster booting) */ 400 } 401 402 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; 403 404 return 0; 405 } 406 407 /* Generic function which updates the speed and duplex. If 408 * autonegotiation is enabled, it uses the AND of the link 409 * partner's advertised capabilities and our advertised 410 * capabilities. If autonegotiation is disabled, we use the 411 * appropriate bits in the control register. 412 * 413 * Stolen from Linux's mii.c and phy_device.c 414 */ 415 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 416 { 417 /* We're using autonegotiation */ 418 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 419 uint lpa = 0; 420 uint gblpa = 0; 421 422 /* Check for gigabit capability */ 423 if (mii_reg & PHY_BMSR_EXT) { 424 /* We want a list of states supported by 425 * both PHYs in the link 426 */ 427 gblpa = read_phy_reg(priv, PHY_1000BTSR); 428 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 429 } 430 431 /* Set the baseline so we only have to set them 432 * if they're different 433 */ 434 priv->speed = 10; 435 priv->duplexity = 0; 436 437 /* Check the gigabit fields */ 438 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 439 priv->speed = 1000; 440 441 if (gblpa & PHY_1000BTSR_1000FD) 442 priv->duplexity = 1; 443 444 /* We're done! */ 445 return 0; 446 } 447 448 lpa = read_phy_reg(priv, PHY_ANAR); 449 lpa &= read_phy_reg(priv, PHY_ANLPAR); 450 451 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 452 priv->speed = 100; 453 454 if (lpa & PHY_ANLPAR_TXFD) 455 priv->duplexity = 1; 456 457 } else if (lpa & PHY_ANLPAR_10FD) 458 priv->duplexity = 1; 459 } else { 460 uint bmcr = read_phy_reg(priv, PHY_BMCR); 461 462 priv->speed = 10; 463 priv->duplexity = 0; 464 465 if (bmcr & PHY_BMCR_DPLX) 466 priv->duplexity = 1; 467 468 if (bmcr & PHY_BMCR_1000_MBPS) 469 priv->speed = 1000; 470 else if (bmcr & PHY_BMCR_100_MBPS) 471 priv->speed = 100; 472 } 473 474 return 0; 475 } 476 477 /* 478 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 479 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 480 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 481 * link. "Ethernet@Wirespeed" reduces advertised speed until link 482 * can be achieved. 483 */ 484 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) 485 { 486 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; 487 } 488 489 /* 490 * Parse the BCM54xx status register for speed and duplex information. 491 * The linux sungem_phy has this information, but in a table format. 492 */ 493 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 494 { 495 /* If there is no link, speed and duplex don't matter */ 496 if (!priv->link) 497 return 0; 498 499 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 500 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 501 case 1: 502 priv->duplexity = 0; 503 priv->speed = 10; 504 break; 505 case 2: 506 priv->duplexity = 1; 507 priv->speed = 10; 508 break; 509 case 3: 510 priv->duplexity = 0; 511 priv->speed = 100; 512 break; 513 case 5: 514 priv->duplexity = 1; 515 priv->speed = 100; 516 break; 517 case 6: 518 priv->duplexity = 0; 519 priv->speed = 1000; 520 break; 521 case 7: 522 priv->duplexity = 1; 523 priv->speed = 1000; 524 break; 525 default: 526 printf("Auto-neg error, defaulting to 10BT/HD\n"); 527 priv->duplexity = 0; 528 priv->speed = 10; 529 break; 530 } 531 532 return 0; 533 } 534 535 /* 536 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg 537 * 0x42 - "Operating Mode Status Register" 538 */ 539 static int BCM8482_is_serdes(struct tsec_private *priv) 540 { 541 u16 val; 542 int serdes = 0; 543 544 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42); 545 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 546 547 switch (val & 0x1f) { 548 case 0x0d: /* RGMII-to-100Base-FX */ 549 case 0x0e: /* RGMII-to-SGMII */ 550 case 0x0f: /* RGMII-to-SerDes */ 551 case 0x12: /* SGMII-to-SerDes */ 552 case 0x13: /* SGMII-to-100Base-FX */ 553 case 0x16: /* SerDes-to-Serdes */ 554 serdes = 1; 555 break; 556 case 0x6: /* RGMII-to-Copper */ 557 case 0x14: /* SGMII-to-Copper */ 558 case 0x17: /* SerDes-to-Copper */ 559 break; 560 default: 561 printf("ERROR, invalid PHY mode (0x%x\n)", val); 562 break; 563 } 564 565 return serdes; 566 } 567 568 /* 569 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating 570 * Mode Status Register" 571 */ 572 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv) 573 { 574 u16 val; 575 int i = 0; 576 577 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ 578 while (1) { 579 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, 580 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 581 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 582 583 if (val & 0x8000) 584 break; 585 586 if (i++ > 1000) { 587 priv->link = 0; 588 return 1; 589 } 590 591 udelay(1000); /* 1 ms */ 592 } 593 594 priv->link = 1; 595 switch ((val >> 13) & 0x3) { 596 case (0x00): 597 priv->speed = 10; 598 break; 599 case (0x01): 600 priv->speed = 100; 601 break; 602 case (0x02): 603 priv->speed = 1000; 604 break; 605 } 606 607 priv->duplexity = (val & 0x1000) == 0x1000; 608 609 return 0; 610 } 611 612 /* 613 * Figure out if BCM5482 is in serdes or copper mode and determine link 614 * configuration accordingly 615 */ 616 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) 617 { 618 if (BCM8482_is_serdes(priv)) { 619 mii_parse_BCM5482_serdes_sr(priv); 620 } else { 621 /* Wait for auto-negotiation to complete or fail */ 622 mii_parse_sr(mii_reg, priv); 623 624 /* Parse BCM54xx copper aux status register */ 625 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS); 626 mii_parse_BCM54xx_sr(mii_reg, priv); 627 } 628 629 return 0; 630 } 631 632 /* Parse the 88E1011's status register for speed and duplex 633 * information 634 */ 635 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 636 { 637 uint speed; 638 639 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 640 641 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 642 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 643 int i = 0; 644 645 puts("Waiting for PHY realtime link"); 646 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 647 /* Timeout reached ? */ 648 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 649 puts(" TIMEOUT !\n"); 650 priv->link = 0; 651 break; 652 } 653 654 if ((i++ % 1000) == 0) { 655 putc('.'); 656 } 657 udelay(1000); /* 1 ms */ 658 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 659 } 660 puts(" done\n"); 661 udelay(500000); /* another 500 ms (results in faster booting) */ 662 } else { 663 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 664 priv->link = 1; 665 else 666 priv->link = 0; 667 } 668 669 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 670 priv->duplexity = 1; 671 else 672 priv->duplexity = 0; 673 674 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 675 676 switch (speed) { 677 case MIIM_88E1011_PHYSTAT_GBIT: 678 priv->speed = 1000; 679 break; 680 case MIIM_88E1011_PHYSTAT_100: 681 priv->speed = 100; 682 break; 683 default: 684 priv->speed = 10; 685 } 686 687 return 0; 688 } 689 690 /* Parse the RTL8211B's status register for speed and duplex 691 * information 692 */ 693 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 694 { 695 uint speed; 696 697 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 698 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 699 int i = 0; 700 701 /* in case of timeout ->link is cleared */ 702 priv->link = 1; 703 puts("Waiting for PHY realtime link"); 704 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 705 /* Timeout reached ? */ 706 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 707 puts(" TIMEOUT !\n"); 708 priv->link = 0; 709 break; 710 } 711 712 if ((i++ % 1000) == 0) { 713 putc('.'); 714 } 715 udelay(1000); /* 1 ms */ 716 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 717 } 718 puts(" done\n"); 719 udelay(500000); /* another 500 ms (results in faster booting) */ 720 } else { 721 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 722 priv->link = 1; 723 else 724 priv->link = 0; 725 } 726 727 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 728 priv->duplexity = 1; 729 else 730 priv->duplexity = 0; 731 732 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 733 734 switch (speed) { 735 case MIIM_RTL8211B_PHYSTAT_GBIT: 736 priv->speed = 1000; 737 break; 738 case MIIM_RTL8211B_PHYSTAT_100: 739 priv->speed = 100; 740 break; 741 default: 742 priv->speed = 10; 743 } 744 745 return 0; 746 } 747 748 /* Parse the cis8201's status register for speed and duplex 749 * information 750 */ 751 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 752 { 753 uint speed; 754 755 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 756 priv->duplexity = 1; 757 else 758 priv->duplexity = 0; 759 760 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 761 switch (speed) { 762 case MIIM_CIS8201_AUXCONSTAT_GBIT: 763 priv->speed = 1000; 764 break; 765 case MIIM_CIS8201_AUXCONSTAT_100: 766 priv->speed = 100; 767 break; 768 default: 769 priv->speed = 10; 770 break; 771 } 772 773 return 0; 774 } 775 776 /* Parse the vsc8244's status register for speed and duplex 777 * information 778 */ 779 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 780 { 781 uint speed; 782 783 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 784 priv->duplexity = 1; 785 else 786 priv->duplexity = 0; 787 788 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 789 switch (speed) { 790 case MIIM_VSC8244_AUXCONSTAT_GBIT: 791 priv->speed = 1000; 792 break; 793 case MIIM_VSC8244_AUXCONSTAT_100: 794 priv->speed = 100; 795 break; 796 default: 797 priv->speed = 10; 798 break; 799 } 800 801 return 0; 802 } 803 804 /* Parse the DM9161's status register for speed and duplex 805 * information 806 */ 807 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 808 { 809 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 810 priv->speed = 100; 811 else 812 priv->speed = 10; 813 814 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 815 priv->duplexity = 1; 816 else 817 priv->duplexity = 0; 818 819 return 0; 820 } 821 822 /* 823 * Hack to write all 4 PHYs with the LED values 824 */ 825 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 826 { 827 uint phyid; 828 volatile tsec_mdio_t *regbase = priv->phyregs; 829 int timeout = 1000000; 830 831 for (phyid = 0; phyid < 4; phyid++) { 832 regbase->miimadd = (phyid << 8) | mii_reg; 833 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 834 asm("sync"); 835 836 timeout = 1000000; 837 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 838 } 839 840 return MIIM_CIS8204_SLEDCON_INIT; 841 } 842 843 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 844 { 845 if (priv->flags & TSEC_REDUCED) 846 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 847 else 848 return MIIM_CIS8204_EPHYCON_INIT; 849 } 850 851 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 852 { 853 uint mii_data = read_phy_reg(priv, mii_reg); 854 855 if (priv->flags & TSEC_REDUCED) 856 mii_data = (mii_data & 0xfff0) | 0x000b; 857 return mii_data; 858 } 859 860 /* Initialized required registers to appropriate values, zeroing 861 * those we don't care about (unless zero is bad, in which case, 862 * choose a more appropriate value) 863 */ 864 static void init_registers(volatile tsec_t * regs) 865 { 866 /* Clear IEVENT */ 867 regs->ievent = IEVENT_INIT_CLEAR; 868 869 regs->imask = IMASK_INIT_CLEAR; 870 871 regs->hash.iaddr0 = 0; 872 regs->hash.iaddr1 = 0; 873 regs->hash.iaddr2 = 0; 874 regs->hash.iaddr3 = 0; 875 regs->hash.iaddr4 = 0; 876 regs->hash.iaddr5 = 0; 877 regs->hash.iaddr6 = 0; 878 regs->hash.iaddr7 = 0; 879 880 regs->hash.gaddr0 = 0; 881 regs->hash.gaddr1 = 0; 882 regs->hash.gaddr2 = 0; 883 regs->hash.gaddr3 = 0; 884 regs->hash.gaddr4 = 0; 885 regs->hash.gaddr5 = 0; 886 regs->hash.gaddr6 = 0; 887 regs->hash.gaddr7 = 0; 888 889 regs->rctrl = 0x00000000; 890 891 /* Init RMON mib registers */ 892 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 893 894 regs->rmon.cam1 = 0xffffffff; 895 regs->rmon.cam2 = 0xffffffff; 896 897 regs->mrblr = MRBLR_INIT_SETTINGS; 898 899 regs->minflr = MINFLR_INIT_SETTINGS; 900 901 regs->attr = ATTR_INIT_SETTINGS; 902 regs->attreli = ATTRELI_INIT_SETTINGS; 903 904 } 905 906 /* Configure maccfg2 based on negotiated speed and duplex 907 * reported by PHY handling code 908 */ 909 static void adjust_link(struct eth_device *dev) 910 { 911 struct tsec_private *priv = (struct tsec_private *)dev->priv; 912 volatile tsec_t *regs = priv->regs; 913 914 if (priv->link) { 915 if (priv->duplexity != 0) 916 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 917 else 918 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 919 920 switch (priv->speed) { 921 case 1000: 922 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 923 | MACCFG2_GMII); 924 break; 925 case 100: 926 case 10: 927 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 928 | MACCFG2_MII); 929 930 /* Set R100 bit in all modes although 931 * it is only used in RGMII mode 932 */ 933 if (priv->speed == 100) 934 regs->ecntrl |= ECNTRL_R100; 935 else 936 regs->ecntrl &= ~(ECNTRL_R100); 937 break; 938 default: 939 printf("%s: Speed was bad\n", dev->name); 940 break; 941 } 942 943 printf("Speed: %d, %s duplex\n", priv->speed, 944 (priv->duplexity) ? "full" : "half"); 945 946 } else { 947 printf("%s: No link.\n", dev->name); 948 } 949 } 950 951 /* Set up the buffers and their descriptors, and bring up the 952 * interface 953 */ 954 static void startup_tsec(struct eth_device *dev) 955 { 956 int i; 957 struct tsec_private *priv = (struct tsec_private *)dev->priv; 958 volatile tsec_t *regs = priv->regs; 959 960 /* Point to the buffer descriptors */ 961 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 962 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 963 964 /* Initialize the Rx Buffer descriptors */ 965 for (i = 0; i < PKTBUFSRX; i++) { 966 rtx.rxbd[i].status = RXBD_EMPTY; 967 rtx.rxbd[i].length = 0; 968 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 969 } 970 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 971 972 /* Initialize the TX Buffer Descriptors */ 973 for (i = 0; i < TX_BUF_CNT; i++) { 974 rtx.txbd[i].status = 0; 975 rtx.txbd[i].length = 0; 976 rtx.txbd[i].bufPtr = 0; 977 } 978 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 979 980 /* Start up the PHY */ 981 if(priv->phyinfo) 982 phy_run_commands(priv, priv->phyinfo->startup); 983 984 adjust_link(dev); 985 986 /* Enable Transmit and Receive */ 987 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 988 989 /* Tell the DMA it is clear to go */ 990 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 991 regs->tstat = TSTAT_CLEAR_THALT; 992 regs->rstat = RSTAT_CLEAR_RHALT; 993 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 994 } 995 996 /* This returns the status bits of the device. The return value 997 * is never checked, and this is what the 8260 driver did, so we 998 * do the same. Presumably, this would be zero if there were no 999 * errors 1000 */ 1001 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 1002 { 1003 int i; 1004 int result = 0; 1005 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1006 volatile tsec_t *regs = priv->regs; 1007 1008 /* Find an empty buffer descriptor */ 1009 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1010 if (i >= TOUT_LOOP) { 1011 debug("%s: tsec: tx buffers full\n", dev->name); 1012 return result; 1013 } 1014 } 1015 1016 rtx.txbd[txIdx].bufPtr = (uint) packet; 1017 rtx.txbd[txIdx].length = length; 1018 rtx.txbd[txIdx].status |= 1019 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 1020 1021 /* Tell the DMA to go */ 1022 regs->tstat = TSTAT_CLEAR_THALT; 1023 1024 /* Wait for buffer to be transmitted */ 1025 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1026 if (i >= TOUT_LOOP) { 1027 debug("%s: tsec: tx error\n", dev->name); 1028 return result; 1029 } 1030 } 1031 1032 txIdx = (txIdx + 1) % TX_BUF_CNT; 1033 result = rtx.txbd[txIdx].status & TXBD_STATS; 1034 1035 return result; 1036 } 1037 1038 static int tsec_recv(struct eth_device *dev) 1039 { 1040 int length; 1041 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1042 volatile tsec_t *regs = priv->regs; 1043 1044 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 1045 1046 length = rtx.rxbd[rxIdx].length; 1047 1048 /* Send the packet up if there were no errors */ 1049 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 1050 NetReceive(NetRxPackets[rxIdx], length - 4); 1051 } else { 1052 printf("Got error %x\n", 1053 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 1054 } 1055 1056 rtx.rxbd[rxIdx].length = 0; 1057 1058 /* Set the wrap bit if this is the last element in the list */ 1059 rtx.rxbd[rxIdx].status = 1060 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 1061 1062 rxIdx = (rxIdx + 1) % PKTBUFSRX; 1063 } 1064 1065 if (regs->ievent & IEVENT_BSY) { 1066 regs->ievent = IEVENT_BSY; 1067 regs->rstat = RSTAT_CLEAR_RHALT; 1068 } 1069 1070 return -1; 1071 1072 } 1073 1074 /* Stop the interface */ 1075 static void tsec_halt(struct eth_device *dev) 1076 { 1077 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1078 volatile tsec_t *regs = priv->regs; 1079 1080 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1081 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 1082 1083 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 1084 1085 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 1086 1087 /* Shut down the PHY, as needed */ 1088 if(priv->phyinfo) 1089 phy_run_commands(priv, priv->phyinfo->shutdown); 1090 } 1091 1092 static struct phy_info phy_info_M88E1149S = { 1093 0x1410ca, 1094 "Marvell 88E1149S", 1095 4, 1096 (struct phy_cmd[]) { /* config */ 1097 /* Reset and configure the PHY */ 1098 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1099 {0x1d, 0x1f, NULL}, 1100 {0x1e, 0x200c, NULL}, 1101 {0x1d, 0x5, NULL}, 1102 {0x1e, 0x0, NULL}, 1103 {0x1e, 0x100, NULL}, 1104 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1105 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1106 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1107 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1108 {miim_end,} 1109 }, 1110 (struct phy_cmd[]) { /* startup */ 1111 /* Status is read once to clear old link state */ 1112 {MIIM_STATUS, miim_read, NULL}, 1113 /* Auto-negotiate */ 1114 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1115 /* Read the status */ 1116 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1117 {miim_end,} 1118 }, 1119 (struct phy_cmd[]) { /* shutdown */ 1120 {miim_end,} 1121 }, 1122 }; 1123 1124 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1125 static struct phy_info phy_info_BCM5461S = { 1126 0x02060c1, /* 5461 ID */ 1127 "Broadcom BCM5461S", 1128 0, /* not clear to me what minor revisions we can shift away */ 1129 (struct phy_cmd[]) { /* config */ 1130 /* Reset and configure the PHY */ 1131 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1132 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1133 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1134 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1135 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1136 {miim_end,} 1137 }, 1138 (struct phy_cmd[]) { /* startup */ 1139 /* Status is read once to clear old link state */ 1140 {MIIM_STATUS, miim_read, NULL}, 1141 /* Auto-negotiate */ 1142 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1143 /* Read the status */ 1144 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1145 {miim_end,} 1146 }, 1147 (struct phy_cmd[]) { /* shutdown */ 1148 {miim_end,} 1149 }, 1150 }; 1151 1152 static struct phy_info phy_info_BCM5464S = { 1153 0x02060b1, /* 5464 ID */ 1154 "Broadcom BCM5464S", 1155 0, /* not clear to me what minor revisions we can shift away */ 1156 (struct phy_cmd[]) { /* config */ 1157 /* Reset and configure the PHY */ 1158 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1159 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1160 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1161 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1162 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1163 {miim_end,} 1164 }, 1165 (struct phy_cmd[]) { /* startup */ 1166 /* Status is read once to clear old link state */ 1167 {MIIM_STATUS, miim_read, NULL}, 1168 /* Auto-negotiate */ 1169 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1170 /* Read the status */ 1171 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1172 {miim_end,} 1173 }, 1174 (struct phy_cmd[]) { /* shutdown */ 1175 {miim_end,} 1176 }, 1177 }; 1178 1179 static struct phy_info phy_info_BCM5482S = { 1180 0x0143bcb, 1181 "Broadcom BCM5482S", 1182 4, 1183 (struct phy_cmd[]) { /* config */ 1184 /* Reset and configure the PHY */ 1185 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1186 /* Setup read from auxilary control shadow register 7 */ 1187 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, 1188 /* Read Misc Control register and or in Ethernet@Wirespeed */ 1189 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, 1190 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1191 /* Initial config/enable of secondary SerDes interface */ 1192 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL}, 1193 /* Write intial value to secondary SerDes Contol */ 1194 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL}, 1195 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL}, 1196 /* Enable copper/fiber auto-detect */ 1197 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)}, 1198 {miim_end,} 1199 }, 1200 (struct phy_cmd[]) { /* startup */ 1201 /* Status is read once to clear old link state */ 1202 {MIIM_STATUS, miim_read, NULL}, 1203 /* Determine copper/fiber, auto-negotiate, and read the result */ 1204 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr}, 1205 {miim_end,} 1206 }, 1207 (struct phy_cmd[]) { /* shutdown */ 1208 {miim_end,} 1209 }, 1210 }; 1211 1212 static struct phy_info phy_info_M88E1011S = { 1213 0x01410c6, 1214 "Marvell 88E1011S", 1215 4, 1216 (struct phy_cmd[]) { /* config */ 1217 /* Reset and configure the PHY */ 1218 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1219 {0x1d, 0x1f, NULL}, 1220 {0x1e, 0x200c, NULL}, 1221 {0x1d, 0x5, NULL}, 1222 {0x1e, 0x0, NULL}, 1223 {0x1e, 0x100, NULL}, 1224 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1225 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1226 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1227 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1228 {miim_end,} 1229 }, 1230 (struct phy_cmd[]) { /* startup */ 1231 /* Status is read once to clear old link state */ 1232 {MIIM_STATUS, miim_read, NULL}, 1233 /* Auto-negotiate */ 1234 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1235 /* Read the status */ 1236 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1237 {miim_end,} 1238 }, 1239 (struct phy_cmd[]) { /* shutdown */ 1240 {miim_end,} 1241 }, 1242 }; 1243 1244 static struct phy_info phy_info_M88E1111S = { 1245 0x01410cc, 1246 "Marvell 88E1111S", 1247 4, 1248 (struct phy_cmd[]) { /* config */ 1249 /* Reset and configure the PHY */ 1250 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1251 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1252 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1253 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1254 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1255 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1256 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1257 {miim_end,} 1258 }, 1259 (struct phy_cmd[]) { /* startup */ 1260 /* Status is read once to clear old link state */ 1261 {MIIM_STATUS, miim_read, NULL}, 1262 /* Auto-negotiate */ 1263 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1264 /* Read the status */ 1265 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1266 {miim_end,} 1267 }, 1268 (struct phy_cmd[]) { /* shutdown */ 1269 {miim_end,} 1270 }, 1271 }; 1272 1273 static struct phy_info phy_info_M88E1118 = { 1274 0x01410e1, 1275 "Marvell 88E1118", 1276 4, 1277 (struct phy_cmd[]) { /* config */ 1278 /* Reset and configure the PHY */ 1279 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1280 {0x16, 0x0002, NULL}, /* Change Page Number */ 1281 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1282 {0x16, 0x0003, NULL}, /* Change Page Number */ 1283 {0x10, 0x021e, NULL}, /* Adjust LED control */ 1284 {0x16, 0x0000, NULL}, /* Change Page Number */ 1285 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1286 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1287 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1288 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1289 {miim_end,} 1290 }, 1291 (struct phy_cmd[]) { /* startup */ 1292 {0x16, 0x0000, NULL}, /* Change Page Number */ 1293 /* Status is read once to clear old link state */ 1294 {MIIM_STATUS, miim_read, NULL}, 1295 /* Auto-negotiate */ 1296 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1297 /* Read the status */ 1298 {MIIM_88E1011_PHY_STATUS, miim_read, 1299 &mii_parse_88E1011_psr}, 1300 {miim_end,} 1301 }, 1302 (struct phy_cmd[]) { /* shutdown */ 1303 {miim_end,} 1304 }, 1305 }; 1306 1307 /* 1308 * Since to access LED register we need do switch the page, we 1309 * do LED configuring in the miim_read-like function as follows 1310 */ 1311 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1312 { 1313 uint pg; 1314 1315 /* Switch the page to access the led register */ 1316 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1317 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1318 1319 /* Configure leds */ 1320 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1321 MIIM_88E1121_PHY_LED_DEF); 1322 1323 /* Restore the page pointer */ 1324 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1325 return 0; 1326 } 1327 1328 static struct phy_info phy_info_M88E1121R = { 1329 0x01410cb, 1330 "Marvell 88E1121R", 1331 4, 1332 (struct phy_cmd[]) { /* config */ 1333 /* Reset and configure the PHY */ 1334 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1335 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1336 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1337 /* Configure leds */ 1338 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, 1339 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1340 /* Disable IRQs and de-assert interrupt */ 1341 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1342 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1343 {miim_end,} 1344 }, 1345 (struct phy_cmd[]) { /* startup */ 1346 /* Status is read once to clear old link state */ 1347 {MIIM_STATUS, miim_read, NULL}, 1348 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1349 {MIIM_STATUS, miim_read, &mii_parse_link}, 1350 {miim_end,} 1351 }, 1352 (struct phy_cmd[]) { /* shutdown */ 1353 {miim_end,} 1354 }, 1355 }; 1356 1357 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1358 { 1359 uint mii_data = read_phy_reg(priv, mii_reg); 1360 1361 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1362 if (priv->flags & TSEC_REDUCED) 1363 return mii_data | 1364 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1365 else 1366 return mii_data; 1367 } 1368 1369 static struct phy_info phy_info_M88E1145 = { 1370 0x01410cd, 1371 "Marvell 88E1145", 1372 4, 1373 (struct phy_cmd[]) { /* config */ 1374 /* Reset the PHY */ 1375 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1376 1377 /* Errata E0, E1 */ 1378 {29, 0x001b, NULL}, 1379 {30, 0x418f, NULL}, 1380 {29, 0x0016, NULL}, 1381 {30, 0xa2da, NULL}, 1382 1383 /* Configure the PHY */ 1384 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1385 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1386 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, 1387 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1388 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1389 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1390 {miim_end,} 1391 }, 1392 (struct phy_cmd[]) { /* startup */ 1393 /* Status is read once to clear old link state */ 1394 {MIIM_STATUS, miim_read, NULL}, 1395 /* Auto-negotiate */ 1396 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1397 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1398 /* Read the Status */ 1399 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1400 {miim_end,} 1401 }, 1402 (struct phy_cmd[]) { /* shutdown */ 1403 {miim_end,} 1404 }, 1405 }; 1406 1407 static struct phy_info phy_info_cis8204 = { 1408 0x3f11, 1409 "Cicada Cis8204", 1410 6, 1411 (struct phy_cmd[]) { /* config */ 1412 /* Override PHY config settings */ 1413 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1414 /* Configure some basic stuff */ 1415 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1416 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1417 &mii_cis8204_fixled}, 1418 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1419 &mii_cis8204_setmode}, 1420 {miim_end,} 1421 }, 1422 (struct phy_cmd[]) { /* startup */ 1423 /* Read the Status (2x to make sure link is right) */ 1424 {MIIM_STATUS, miim_read, NULL}, 1425 /* Auto-negotiate */ 1426 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1427 /* Read the status */ 1428 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1429 {miim_end,} 1430 }, 1431 (struct phy_cmd[]) { /* shutdown */ 1432 {miim_end,} 1433 }, 1434 }; 1435 1436 /* Cicada 8201 */ 1437 static struct phy_info phy_info_cis8201 = { 1438 0xfc41, 1439 "CIS8201", 1440 4, 1441 (struct phy_cmd[]) { /* config */ 1442 /* Override PHY config settings */ 1443 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1444 /* Set up the interface mode */ 1445 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1446 /* Configure some basic stuff */ 1447 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1448 {miim_end,} 1449 }, 1450 (struct phy_cmd[]) { /* startup */ 1451 /* Read the Status (2x to make sure link is right) */ 1452 {MIIM_STATUS, miim_read, NULL}, 1453 /* Auto-negotiate */ 1454 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1455 /* Read the status */ 1456 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1457 {miim_end,} 1458 }, 1459 (struct phy_cmd[]) { /* shutdown */ 1460 {miim_end,} 1461 }, 1462 }; 1463 1464 static struct phy_info phy_info_VSC8211 = { 1465 0xfc4b, 1466 "Vitesse VSC8211", 1467 4, 1468 (struct phy_cmd[]) { /* config */ 1469 /* Override PHY config settings */ 1470 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1471 /* Set up the interface mode */ 1472 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1473 /* Configure some basic stuff */ 1474 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1475 {miim_end,} 1476 }, 1477 (struct phy_cmd[]) { /* startup */ 1478 /* Read the Status (2x to make sure link is right) */ 1479 {MIIM_STATUS, miim_read, NULL}, 1480 /* Auto-negotiate */ 1481 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1482 /* Read the status */ 1483 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1484 {miim_end,} 1485 }, 1486 (struct phy_cmd[]) { /* shutdown */ 1487 {miim_end,} 1488 }, 1489 }; 1490 1491 static struct phy_info phy_info_VSC8244 = { 1492 0x3f1b, 1493 "Vitesse VSC8244", 1494 6, 1495 (struct phy_cmd[]) { /* config */ 1496 /* Override PHY config settings */ 1497 /* Configure some basic stuff */ 1498 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1499 {miim_end,} 1500 }, 1501 (struct phy_cmd[]) { /* startup */ 1502 /* Read the Status (2x to make sure link is right) */ 1503 {MIIM_STATUS, miim_read, NULL}, 1504 /* Auto-negotiate */ 1505 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1506 /* Read the status */ 1507 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1508 {miim_end,} 1509 }, 1510 (struct phy_cmd[]) { /* shutdown */ 1511 {miim_end,} 1512 }, 1513 }; 1514 1515 static struct phy_info phy_info_VSC8641 = { 1516 0x7043, 1517 "Vitesse VSC8641", 1518 4, 1519 (struct phy_cmd[]) { /* config */ 1520 /* Configure some basic stuff */ 1521 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1522 {miim_end,} 1523 }, 1524 (struct phy_cmd[]) { /* startup */ 1525 /* Read the Status (2x to make sure link is right) */ 1526 {MIIM_STATUS, miim_read, NULL}, 1527 /* Auto-negotiate */ 1528 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1529 /* Read the status */ 1530 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1531 {miim_end,} 1532 }, 1533 (struct phy_cmd[]) { /* shutdown */ 1534 {miim_end,} 1535 }, 1536 }; 1537 1538 static struct phy_info phy_info_VSC8221 = { 1539 0xfc55, 1540 "Vitesse VSC8221", 1541 4, 1542 (struct phy_cmd[]) { /* config */ 1543 /* Configure some basic stuff */ 1544 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1545 {miim_end,} 1546 }, 1547 (struct phy_cmd[]) { /* startup */ 1548 /* Read the Status (2x to make sure link is right) */ 1549 {MIIM_STATUS, miim_read, NULL}, 1550 /* Auto-negotiate */ 1551 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1552 /* Read the status */ 1553 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1554 {miim_end,} 1555 }, 1556 (struct phy_cmd[]) { /* shutdown */ 1557 {miim_end,} 1558 }, 1559 }; 1560 1561 static struct phy_info phy_info_VSC8601 = { 1562 0x00007042, 1563 "Vitesse VSC8601", 1564 4, 1565 (struct phy_cmd[]) { /* config */ 1566 /* Override PHY config settings */ 1567 /* Configure some basic stuff */ 1568 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1569 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1570 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1571 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1572 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1573 #define VSC8101_SKEW \ 1574 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) 1575 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1576 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1577 #endif 1578 #endif 1579 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1580 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1581 {miim_end,} 1582 }, 1583 (struct phy_cmd[]) { /* startup */ 1584 /* Read the Status (2x to make sure link is right) */ 1585 {MIIM_STATUS, miim_read, NULL}, 1586 /* Auto-negotiate */ 1587 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1588 /* Read the status */ 1589 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1590 {miim_end,} 1591 }, 1592 (struct phy_cmd[]) { /* shutdown */ 1593 {miim_end,} 1594 }, 1595 }; 1596 1597 static struct phy_info phy_info_dm9161 = { 1598 0x0181b88, 1599 "Davicom DM9161E", 1600 4, 1601 (struct phy_cmd[]) { /* config */ 1602 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1603 /* Do not bypass the scrambler/descrambler */ 1604 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1605 /* Clear 10BTCSR to default */ 1606 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, 1607 /* Configure some basic stuff */ 1608 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1609 /* Restart Auto Negotiation */ 1610 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1611 {miim_end,} 1612 }, 1613 (struct phy_cmd[]) { /* startup */ 1614 /* Status is read once to clear old link state */ 1615 {MIIM_STATUS, miim_read, NULL}, 1616 /* Auto-negotiate */ 1617 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1618 /* Read the status */ 1619 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, 1620 {miim_end,} 1621 }, 1622 (struct phy_cmd[]) { /* shutdown */ 1623 {miim_end,} 1624 }, 1625 }; 1626 1627 /* a generic flavor. */ 1628 static struct phy_info phy_info_generic = { 1629 0, 1630 "Unknown/Generic PHY", 1631 32, 1632 (struct phy_cmd[]) { /* config */ 1633 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1634 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1635 {miim_end,} 1636 }, 1637 (struct phy_cmd[]) { /* startup */ 1638 {PHY_BMSR, miim_read, NULL}, 1639 {PHY_BMSR, miim_read, &mii_parse_sr}, 1640 {PHY_BMSR, miim_read, &mii_parse_link}, 1641 {miim_end,} 1642 }, 1643 (struct phy_cmd[]) { /* shutdown */ 1644 {miim_end,} 1645 } 1646 }; 1647 1648 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1649 { 1650 unsigned int speed; 1651 if (priv->link) { 1652 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1653 1654 switch (speed) { 1655 case MIIM_LXT971_SR2_10HDX: 1656 priv->speed = 10; 1657 priv->duplexity = 0; 1658 break; 1659 case MIIM_LXT971_SR2_10FDX: 1660 priv->speed = 10; 1661 priv->duplexity = 1; 1662 break; 1663 case MIIM_LXT971_SR2_100HDX: 1664 priv->speed = 100; 1665 priv->duplexity = 0; 1666 break; 1667 default: 1668 priv->speed = 100; 1669 priv->duplexity = 1; 1670 } 1671 } else { 1672 priv->speed = 0; 1673 priv->duplexity = 0; 1674 } 1675 1676 return 0; 1677 } 1678 1679 static struct phy_info phy_info_lxt971 = { 1680 0x0001378e, 1681 "LXT971", 1682 4, 1683 (struct phy_cmd[]) { /* config */ 1684 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1685 {miim_end,} 1686 }, 1687 (struct phy_cmd[]) { /* startup - enable interrupts */ 1688 /* { 0x12, 0x00f2, NULL }, */ 1689 {MIIM_STATUS, miim_read, NULL}, 1690 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1691 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1692 {miim_end,} 1693 }, 1694 (struct phy_cmd[]) { /* shutdown - disable interrupts */ 1695 {miim_end,} 1696 }, 1697 }; 1698 1699 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1700 * information 1701 */ 1702 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1703 { 1704 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1705 1706 case MIIM_DP83865_SPD_1000: 1707 priv->speed = 1000; 1708 break; 1709 1710 case MIIM_DP83865_SPD_100: 1711 priv->speed = 100; 1712 break; 1713 1714 default: 1715 priv->speed = 10; 1716 break; 1717 1718 } 1719 1720 if (mii_reg & MIIM_DP83865_DPX_FULL) 1721 priv->duplexity = 1; 1722 else 1723 priv->duplexity = 0; 1724 1725 return 0; 1726 } 1727 1728 static struct phy_info phy_info_dp83865 = { 1729 0x20005c7, 1730 "NatSemi DP83865", 1731 4, 1732 (struct phy_cmd[]) { /* config */ 1733 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1734 {miim_end,} 1735 }, 1736 (struct phy_cmd[]) { /* startup */ 1737 /* Status is read once to clear old link state */ 1738 {MIIM_STATUS, miim_read, NULL}, 1739 /* Auto-negotiate */ 1740 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1741 /* Read the link and auto-neg status */ 1742 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, 1743 {miim_end,} 1744 }, 1745 (struct phy_cmd[]) { /* shutdown */ 1746 {miim_end,} 1747 }, 1748 }; 1749 1750 static struct phy_info phy_info_rtl8211b = { 1751 0x001cc91, 1752 "RealTek RTL8211B", 1753 4, 1754 (struct phy_cmd[]) { /* config */ 1755 /* Reset and configure the PHY */ 1756 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1757 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1758 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1759 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1760 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1761 {miim_end,} 1762 }, 1763 (struct phy_cmd[]) { /* startup */ 1764 /* Status is read once to clear old link state */ 1765 {MIIM_STATUS, miim_read, NULL}, 1766 /* Auto-negotiate */ 1767 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1768 /* Read the status */ 1769 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1770 {miim_end,} 1771 }, 1772 (struct phy_cmd[]) { /* shutdown */ 1773 {miim_end,} 1774 }, 1775 }; 1776 1777 static struct phy_info *phy_info[] = { 1778 &phy_info_cis8204, 1779 &phy_info_cis8201, 1780 &phy_info_BCM5461S, 1781 &phy_info_BCM5464S, 1782 &phy_info_BCM5482S, 1783 &phy_info_M88E1011S, 1784 &phy_info_M88E1111S, 1785 &phy_info_M88E1118, 1786 &phy_info_M88E1121R, 1787 &phy_info_M88E1145, 1788 &phy_info_M88E1149S, 1789 &phy_info_dm9161, 1790 &phy_info_lxt971, 1791 &phy_info_VSC8211, 1792 &phy_info_VSC8244, 1793 &phy_info_VSC8601, 1794 &phy_info_VSC8641, 1795 &phy_info_VSC8221, 1796 &phy_info_dp83865, 1797 &phy_info_rtl8211b, 1798 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ 1799 NULL 1800 }; 1801 1802 /* Grab the identifier of the device's PHY, and search through 1803 * all of the known PHYs to see if one matches. If so, return 1804 * it, if not, return NULL 1805 */ 1806 static struct phy_info *get_phy_info(struct eth_device *dev) 1807 { 1808 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1809 uint phy_reg, phy_ID; 1810 int i; 1811 struct phy_info *theInfo = NULL; 1812 1813 /* Grab the bits from PHYIR1, and put them in the upper half */ 1814 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1815 phy_ID = (phy_reg & 0xffff) << 16; 1816 1817 /* Grab the bits from PHYIR2, and put them in the lower half */ 1818 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1819 phy_ID |= (phy_reg & 0xffff); 1820 1821 /* loop through all the known PHY types, and find one that */ 1822 /* matches the ID we read from the PHY. */ 1823 for (i = 0; phy_info[i]; i++) { 1824 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1825 theInfo = phy_info[i]; 1826 break; 1827 } 1828 } 1829 1830 if (theInfo == &phy_info_generic) { 1831 printf("%s: No support for PHY id %x; assuming generic\n", 1832 dev->name, phy_ID); 1833 } else { 1834 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1835 } 1836 1837 return theInfo; 1838 } 1839 1840 /* Execute the given series of commands on the given device's 1841 * PHY, running functions as necessary 1842 */ 1843 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1844 { 1845 int i; 1846 uint result; 1847 volatile tsec_mdio_t *phyregs = priv->phyregs; 1848 1849 phyregs->miimcfg = MIIMCFG_RESET; 1850 1851 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1852 1853 while (phyregs->miimind & MIIMIND_BUSY) ; 1854 1855 for (i = 0; cmd->mii_reg != miim_end; i++) { 1856 if (cmd->mii_data == miim_read) { 1857 result = read_phy_reg(priv, cmd->mii_reg); 1858 1859 if (cmd->funct != NULL) 1860 (*(cmd->funct)) (result, priv); 1861 1862 } else { 1863 if (cmd->funct != NULL) 1864 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1865 else 1866 result = cmd->mii_data; 1867 1868 write_phy_reg(priv, cmd->mii_reg, result); 1869 1870 } 1871 cmd++; 1872 } 1873 } 1874 1875 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1876 && !defined(BITBANGMII) 1877 1878 /* 1879 * Read a MII PHY register. 1880 * 1881 * Returns: 1882 * 0 on success 1883 */ 1884 static int tsec_miiphy_read(char *devname, unsigned char addr, 1885 unsigned char reg, unsigned short *value) 1886 { 1887 unsigned short ret; 1888 struct tsec_private *priv = privlist[0]; 1889 1890 if (NULL == priv) { 1891 printf("Can't read PHY at address %d\n", addr); 1892 return -1; 1893 } 1894 1895 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1896 *value = ret; 1897 1898 return 0; 1899 } 1900 1901 /* 1902 * Write a MII PHY register. 1903 * 1904 * Returns: 1905 * 0 on success 1906 */ 1907 static int tsec_miiphy_write(char *devname, unsigned char addr, 1908 unsigned char reg, unsigned short value) 1909 { 1910 struct tsec_private *priv = privlist[0]; 1911 1912 if (NULL == priv) { 1913 printf("Can't write PHY at address %d\n", addr); 1914 return -1; 1915 } 1916 1917 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1918 1919 return 0; 1920 } 1921 1922 #endif 1923 1924 #ifdef CONFIG_MCAST_TFTP 1925 1926 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1927 1928 /* Set the appropriate hash bit for the given addr */ 1929 1930 /* The algorithm works like so: 1931 * 1) Take the Destination Address (ie the multicast address), and 1932 * do a CRC on it (little endian), and reverse the bits of the 1933 * result. 1934 * 2) Use the 8 most significant bits as a hash into a 256-entry 1935 * table. The table is controlled through 8 32-bit registers: 1936 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1937 * gaddr7. This means that the 3 most significant bits in the 1938 * hash index which gaddr register to use, and the 5 other bits 1939 * indicate which bit (assuming an IBM numbering scheme, which 1940 * for PowerPC (tm) is usually the case) in the tregister holds 1941 * the entry. */ 1942 static int 1943 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1944 { 1945 struct tsec_private *priv = privlist[1]; 1946 volatile tsec_t *regs = priv->regs; 1947 volatile u32 *reg_array, value; 1948 u8 result, whichbit, whichreg; 1949 1950 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1951 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1952 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1953 value = (1 << (31-whichbit)); 1954 1955 reg_array = &(regs->hash.gaddr0); 1956 1957 if (set) { 1958 reg_array[whichreg] |= value; 1959 } else { 1960 reg_array[whichreg] &= ~value; 1961 } 1962 return 0; 1963 } 1964 #endif /* Multicast TFTP ? */ 1965