1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 20 #if defined(CONFIG_TSEC_ENET) 21 #include "tsec.h" 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 struct tsec_info_struct { 37 unsigned int phyaddr; 38 u32 flags; 39 unsigned int phyregidx; 40 }; 41 42 /* The tsec_info structure contains 3 values which the 43 * driver uses to determine how to operate a given ethernet 44 * device. The information needed is: 45 * phyaddr - The address of the PHY which is attached to 46 * the given device. 47 * 48 * flags - This variable indicates whether the device 49 * supports gigabit speed ethernet, and whether it should be 50 * in reduced mode. 51 * 52 * phyregidx - This variable specifies which ethernet device 53 * controls the MII Management registers which are connected 54 * to the PHY. For now, only TSEC1 (index 0) has 55 * access to the PHYs, so all of the entries have "0". 56 * 57 * The values specified in the table are taken from the board's 58 * config file in include/configs/. When implementing a new 59 * board with ethernet capability, it is necessary to define: 60 * TSECn_PHY_ADDR 61 * TSECn_PHYIDX 62 * 63 * for n = 1,2,3, etc. And for FEC: 64 * FEC_PHY_ADDR 65 * FEC_PHYIDX 66 */ 67 static struct tsec_info_struct tsec_info[] = { 68 #ifdef CONFIG_TSEC1 69 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, 70 #else 71 {0, 0, 0}, 72 #endif 73 #ifdef CONFIG_TSEC2 74 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, 75 #else 76 {0, 0, 0}, 77 #endif 78 #ifdef CONFIG_MPC85XX_FEC 79 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, 80 #else 81 #ifdef CONFIG_TSEC3 82 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, 83 #else 84 {0, 0, 0}, 85 #endif 86 #ifdef CONFIG_TSEC4 87 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, 88 #else 89 {0, 0, 0}, 90 #endif /* CONFIG_TSEC4 */ 91 #endif /* CONFIG_MPC85XX_FEC */ 92 }; 93 94 #define MAXCONTROLLERS (4) 95 96 static int relocated = 0; 97 98 static struct tsec_private *privlist[MAXCONTROLLERS]; 99 100 #ifdef __GNUC__ 101 static RTXBD rtx __attribute__ ((aligned(8))); 102 #else 103 #error "rtx must be 64-bit aligned" 104 #endif 105 106 static int tsec_send(struct eth_device *dev, 107 volatile void *packet, int length); 108 static int tsec_recv(struct eth_device *dev); 109 static int tsec_init(struct eth_device *dev, bd_t * bd); 110 static void tsec_halt(struct eth_device *dev); 111 static void init_registers(volatile tsec_t * regs); 112 static void startup_tsec(struct eth_device *dev); 113 static int init_phy(struct eth_device *dev); 114 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 115 uint read_phy_reg(struct tsec_private *priv, uint regnum); 116 struct phy_info *get_phy_info(struct eth_device *dev); 117 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 118 static void adjust_link(struct eth_device *dev); 119 static void relocate_cmds(void); 120 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 121 && !defined(BITBANGMII) 122 static int tsec_miiphy_write(char *devname, unsigned char addr, 123 unsigned char reg, unsigned short value); 124 static int tsec_miiphy_read(char *devname, unsigned char addr, 125 unsigned char reg, unsigned short *value); 126 #endif 127 #ifdef CONFIG_MCAST_TFTP 128 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 129 #endif 130 131 /* Initialize device structure. Returns success if PHY 132 * initialization succeeded (i.e. if it recognizes the PHY) 133 */ 134 int tsec_initialize(bd_t * bis, int index, char *devname) 135 { 136 struct eth_device *dev; 137 int i; 138 struct tsec_private *priv; 139 140 dev = (struct eth_device *)malloc(sizeof *dev); 141 142 if (NULL == dev) 143 return 0; 144 145 memset(dev, 0, sizeof *dev); 146 147 priv = (struct tsec_private *)malloc(sizeof(*priv)); 148 149 if (NULL == priv) 150 return 0; 151 152 privlist[index] = priv; 153 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); 154 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + 155 tsec_info[index].phyregidx * 156 TSEC_SIZE); 157 158 priv->phyaddr = tsec_info[index].phyaddr; 159 priv->flags = tsec_info[index].flags; 160 161 sprintf(dev->name, devname); 162 dev->iobase = 0; 163 dev->priv = priv; 164 dev->init = tsec_init; 165 dev->halt = tsec_halt; 166 dev->send = tsec_send; 167 dev->recv = tsec_recv; 168 #ifdef CONFIG_MCAST_TFTP 169 dev->mcast = tsec_mcast_addr; 170 #endif 171 172 /* Tell u-boot to get the addr from the env */ 173 for (i = 0; i < 6; i++) 174 dev->enetaddr[i] = 0; 175 176 eth_register(dev); 177 178 /* Reset the MAC */ 179 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 180 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 181 182 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 183 && !defined(BITBANGMII) 184 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 185 #endif 186 187 /* Try to initialize PHY here, and return */ 188 return init_phy(dev); 189 } 190 191 /* Initializes data structures and registers for the controller, 192 * and brings the interface up. Returns the link status, meaning 193 * that it returns success if the link is up, failure otherwise. 194 * This allows u-boot to find the first active controller. 195 */ 196 int tsec_init(struct eth_device *dev, bd_t * bd) 197 { 198 uint tempval; 199 char tmpbuf[MAC_ADDR_LEN]; 200 int i; 201 struct tsec_private *priv = (struct tsec_private *)dev->priv; 202 volatile tsec_t *regs = priv->regs; 203 204 /* Make sure the controller is stopped */ 205 tsec_halt(dev); 206 207 /* Init MACCFG2. Defaults to GMII */ 208 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 209 210 /* Init ECNTRL */ 211 regs->ecntrl = ECNTRL_INIT_SETTINGS; 212 213 /* Copy the station address into the address registers. 214 * Backwards, because little endian MACS are dumb */ 215 for (i = 0; i < MAC_ADDR_LEN; i++) { 216 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 217 } 218 regs->macstnaddr1 = *((uint *) (tmpbuf)); 219 220 tempval = *((uint *) (tmpbuf + 4)); 221 222 regs->macstnaddr2 = tempval; 223 224 /* reset the indices to zero */ 225 rxIdx = 0; 226 txIdx = 0; 227 228 /* Clear out (for the most part) the other registers */ 229 init_registers(regs); 230 231 /* Ready the device for tx/rx */ 232 startup_tsec(dev); 233 234 /* If there's no link, fail */ 235 return (priv->link ? 0 : -1); 236 237 } 238 239 /* Write value to the device's PHY through the registers 240 * specified in priv, modifying the register specified in regnum. 241 * It will wait for the write to be done (or for a timeout to 242 * expire) before exiting 243 */ 244 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 245 { 246 volatile tsec_t *regbase = priv->phyregs; 247 int timeout = 1000000; 248 249 regbase->miimadd = (phyid << 8) | regnum; 250 regbase->miimcon = value; 251 asm("sync"); 252 253 timeout = 1000000; 254 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 255 } 256 257 /* #define to provide old write_phy_reg functionality without duplicating code */ 258 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 259 260 /* Reads register regnum on the device's PHY through the 261 * registers specified in priv. It lowers and raises the read 262 * command, and waits for the data to become valid (miimind 263 * notvalid bit cleared), and the bus to cease activity (miimind 264 * busy bit cleared), and then returns the value 265 */ 266 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 267 { 268 uint value; 269 volatile tsec_t *regbase = priv->phyregs; 270 271 /* Put the address of the phy, and the register 272 * number into MIIMADD */ 273 regbase->miimadd = (phyid << 8) | regnum; 274 275 /* Clear the command register, and wait */ 276 regbase->miimcom = 0; 277 asm("sync"); 278 279 /* Initiate a read command, and wait */ 280 regbase->miimcom = MIIM_READ_COMMAND; 281 asm("sync"); 282 283 /* Wait for the the indication that the read is done */ 284 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 285 286 /* Grab the value read from the PHY */ 287 value = regbase->miimstat; 288 289 return value; 290 } 291 292 /* #define to provide old read_phy_reg functionality without duplicating code */ 293 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 294 295 /* Discover which PHY is attached to the device, and configure it 296 * properly. If the PHY is not recognized, then return 0 297 * (failure). Otherwise, return 1 298 */ 299 static int init_phy(struct eth_device *dev) 300 { 301 struct tsec_private *priv = (struct tsec_private *)dev->priv; 302 struct phy_info *curphy; 303 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 304 305 /* Assign a Physical address to the TBI */ 306 regs->tbipa = CFG_TBIPA_VALUE; 307 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 308 regs->tbipa = CFG_TBIPA_VALUE; 309 asm("sync"); 310 311 /* Reset MII (due to new addresses) */ 312 priv->phyregs->miimcfg = MIIMCFG_RESET; 313 asm("sync"); 314 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 315 asm("sync"); 316 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 317 318 if (0 == relocated) 319 relocate_cmds(); 320 321 /* Get the cmd structure corresponding to the attached 322 * PHY */ 323 curphy = get_phy_info(dev); 324 325 if (curphy == NULL) { 326 priv->phyinfo = NULL; 327 printf("%s: No PHY found\n", dev->name); 328 329 return 0; 330 } 331 332 priv->phyinfo = curphy; 333 334 phy_run_commands(priv, priv->phyinfo->config); 335 336 return 1; 337 } 338 339 /* 340 * Returns which value to write to the control register. 341 * For 10/100, the value is slightly different 342 */ 343 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 344 { 345 if (priv->flags & TSEC_GIGABIT) 346 return MIIM_CONTROL_INIT; 347 else 348 return MIIM_CR_INIT; 349 } 350 351 /* Parse the status register for link, and then do 352 * auto-negotiation 353 */ 354 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 355 { 356 /* 357 * Wait if the link is up, and autonegotiation is in progress 358 * (ie - we're capable and it's not done) 359 */ 360 mii_reg = read_phy_reg(priv, MIIM_STATUS); 361 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 362 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 363 int i = 0; 364 365 puts("Waiting for PHY auto negotiation to complete"); 366 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 367 /* 368 * Timeout reached ? 369 */ 370 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 371 puts(" TIMEOUT !\n"); 372 priv->link = 0; 373 return 0; 374 } 375 376 if ((i++ % 1000) == 0) { 377 putc('.'); 378 } 379 udelay(1000); /* 1 ms */ 380 mii_reg = read_phy_reg(priv, MIIM_STATUS); 381 } 382 puts(" done\n"); 383 priv->link = 1; 384 udelay(500000); /* another 500 ms (results in faster booting) */ 385 } else { 386 if (mii_reg & MIIM_STATUS_LINK) 387 priv->link = 1; 388 else 389 priv->link = 0; 390 } 391 392 return 0; 393 } 394 395 /* Generic function which updates the speed and duplex. If 396 * autonegotiation is enabled, it uses the AND of the link 397 * partner's advertised capabilities and our advertised 398 * capabilities. If autonegotiation is disabled, we use the 399 * appropriate bits in the control register. 400 * 401 * Stolen from Linux's mii.c and phy_device.c 402 */ 403 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 404 { 405 /* We're using autonegotiation */ 406 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 407 uint lpa = 0; 408 uint gblpa = 0; 409 410 /* Check for gigabit capability */ 411 if (mii_reg & PHY_BMSR_EXT) { 412 /* We want a list of states supported by 413 * both PHYs in the link 414 */ 415 gblpa = read_phy_reg(priv, PHY_1000BTSR); 416 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 417 } 418 419 /* Set the baseline so we only have to set them 420 * if they're different 421 */ 422 priv->speed = 10; 423 priv->duplexity = 0; 424 425 /* Check the gigabit fields */ 426 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 427 priv->speed = 1000; 428 429 if (gblpa & PHY_1000BTSR_1000FD) 430 priv->duplexity = 1; 431 432 /* We're done! */ 433 return 0; 434 } 435 436 lpa = read_phy_reg(priv, PHY_ANAR); 437 lpa &= read_phy_reg(priv, PHY_ANLPAR); 438 439 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 440 priv->speed = 100; 441 442 if (lpa & PHY_ANLPAR_TXFD) 443 priv->duplexity = 1; 444 445 } else if (lpa & PHY_ANLPAR_10FD) 446 priv->duplexity = 1; 447 } else { 448 uint bmcr = read_phy_reg(priv, PHY_BMCR); 449 450 priv->speed = 10; 451 priv->duplexity = 0; 452 453 if (bmcr & PHY_BMCR_DPLX) 454 priv->duplexity = 1; 455 456 if (bmcr & PHY_BMCR_1000_MBPS) 457 priv->speed = 1000; 458 else if (bmcr & PHY_BMCR_100_MBPS) 459 priv->speed = 100; 460 } 461 462 return 0; 463 } 464 465 /* 466 * Parse the BCM54xx status register for speed and duplex information. 467 * The linux sungem_phy has this information, but in a table format. 468 */ 469 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 470 { 471 472 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 473 474 case 1: 475 printf("Enet starting in 10BT/HD\n"); 476 priv->duplexity = 0; 477 priv->speed = 10; 478 break; 479 480 case 2: 481 printf("Enet starting in 10BT/FD\n"); 482 priv->duplexity = 1; 483 priv->speed = 10; 484 break; 485 486 case 3: 487 printf("Enet starting in 100BT/HD\n"); 488 priv->duplexity = 0; 489 priv->speed = 100; 490 break; 491 492 case 5: 493 printf("Enet starting in 100BT/FD\n"); 494 priv->duplexity = 1; 495 priv->speed = 100; 496 break; 497 498 case 6: 499 printf("Enet starting in 1000BT/HD\n"); 500 priv->duplexity = 0; 501 priv->speed = 1000; 502 break; 503 504 case 7: 505 printf("Enet starting in 1000BT/FD\n"); 506 priv->duplexity = 1; 507 priv->speed = 1000; 508 break; 509 510 default: 511 printf("Auto-neg error, defaulting to 10BT/HD\n"); 512 priv->duplexity = 0; 513 priv->speed = 10; 514 break; 515 } 516 517 return 0; 518 519 } 520 /* Parse the 88E1011's status register for speed and duplex 521 * information 522 */ 523 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 524 { 525 uint speed; 526 527 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 528 529 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 530 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 531 int i = 0; 532 533 puts("Waiting for PHY realtime link"); 534 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 535 /* Timeout reached ? */ 536 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 537 puts(" TIMEOUT !\n"); 538 priv->link = 0; 539 break; 540 } 541 542 if ((i++ % 1000) == 0) { 543 putc('.'); 544 } 545 udelay(1000); /* 1 ms */ 546 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 547 } 548 puts(" done\n"); 549 udelay(500000); /* another 500 ms (results in faster booting) */ 550 } else { 551 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 552 priv->link = 1; 553 else 554 priv->link = 0; 555 } 556 557 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 558 priv->duplexity = 1; 559 else 560 priv->duplexity = 0; 561 562 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 563 564 switch (speed) { 565 case MIIM_88E1011_PHYSTAT_GBIT: 566 priv->speed = 1000; 567 break; 568 case MIIM_88E1011_PHYSTAT_100: 569 priv->speed = 100; 570 break; 571 default: 572 priv->speed = 10; 573 } 574 575 return 0; 576 } 577 578 /* Parse the RTL8211B's status register for speed and duplex 579 * information 580 */ 581 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 582 { 583 uint speed; 584 585 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 586 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 587 int i = 0; 588 589 /* in case of timeout ->link is cleared */ 590 priv->link = 1; 591 puts("Waiting for PHY realtime link"); 592 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 593 /* Timeout reached ? */ 594 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 595 puts(" TIMEOUT !\n"); 596 priv->link = 0; 597 break; 598 } 599 600 if ((i++ % 1000) == 0) { 601 putc('.'); 602 } 603 udelay(1000); /* 1 ms */ 604 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 605 } 606 puts(" done\n"); 607 udelay(500000); /* another 500 ms (results in faster booting) */ 608 } else { 609 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 610 priv->link = 1; 611 else 612 priv->link = 0; 613 } 614 615 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 616 priv->duplexity = 1; 617 else 618 priv->duplexity = 0; 619 620 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 621 622 switch (speed) { 623 case MIIM_RTL8211B_PHYSTAT_GBIT: 624 priv->speed = 1000; 625 break; 626 case MIIM_RTL8211B_PHYSTAT_100: 627 priv->speed = 100; 628 break; 629 default: 630 priv->speed = 10; 631 } 632 633 return 0; 634 } 635 636 /* Parse the cis8201's status register for speed and duplex 637 * information 638 */ 639 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 640 { 641 uint speed; 642 643 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 644 priv->duplexity = 1; 645 else 646 priv->duplexity = 0; 647 648 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 649 switch (speed) { 650 case MIIM_CIS8201_AUXCONSTAT_GBIT: 651 priv->speed = 1000; 652 break; 653 case MIIM_CIS8201_AUXCONSTAT_100: 654 priv->speed = 100; 655 break; 656 default: 657 priv->speed = 10; 658 break; 659 } 660 661 return 0; 662 } 663 664 /* Parse the vsc8244's status register for speed and duplex 665 * information 666 */ 667 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 668 { 669 uint speed; 670 671 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 672 priv->duplexity = 1; 673 else 674 priv->duplexity = 0; 675 676 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 677 switch (speed) { 678 case MIIM_VSC8244_AUXCONSTAT_GBIT: 679 priv->speed = 1000; 680 break; 681 case MIIM_VSC8244_AUXCONSTAT_100: 682 priv->speed = 100; 683 break; 684 default: 685 priv->speed = 10; 686 break; 687 } 688 689 return 0; 690 } 691 692 /* Parse the DM9161's status register for speed and duplex 693 * information 694 */ 695 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 696 { 697 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 698 priv->speed = 100; 699 else 700 priv->speed = 10; 701 702 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 703 priv->duplexity = 1; 704 else 705 priv->duplexity = 0; 706 707 return 0; 708 } 709 710 /* 711 * Hack to write all 4 PHYs with the LED values 712 */ 713 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 714 { 715 uint phyid; 716 volatile tsec_t *regbase = priv->phyregs; 717 int timeout = 1000000; 718 719 for (phyid = 0; phyid < 4; phyid++) { 720 regbase->miimadd = (phyid << 8) | mii_reg; 721 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 722 asm("sync"); 723 724 timeout = 1000000; 725 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 726 } 727 728 return MIIM_CIS8204_SLEDCON_INIT; 729 } 730 731 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 732 { 733 if (priv->flags & TSEC_REDUCED) 734 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 735 else 736 return MIIM_CIS8204_EPHYCON_INIT; 737 } 738 739 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 740 { 741 uint mii_data = read_phy_reg(priv, mii_reg); 742 743 if (priv->flags & TSEC_REDUCED) 744 mii_data = (mii_data & 0xfff0) | 0x000b; 745 return mii_data; 746 } 747 748 /* Initialized required registers to appropriate values, zeroing 749 * those we don't care about (unless zero is bad, in which case, 750 * choose a more appropriate value) 751 */ 752 static void init_registers(volatile tsec_t * regs) 753 { 754 /* Clear IEVENT */ 755 regs->ievent = IEVENT_INIT_CLEAR; 756 757 regs->imask = IMASK_INIT_CLEAR; 758 759 regs->hash.iaddr0 = 0; 760 regs->hash.iaddr1 = 0; 761 regs->hash.iaddr2 = 0; 762 regs->hash.iaddr3 = 0; 763 regs->hash.iaddr4 = 0; 764 regs->hash.iaddr5 = 0; 765 regs->hash.iaddr6 = 0; 766 regs->hash.iaddr7 = 0; 767 768 regs->hash.gaddr0 = 0; 769 regs->hash.gaddr1 = 0; 770 regs->hash.gaddr2 = 0; 771 regs->hash.gaddr3 = 0; 772 regs->hash.gaddr4 = 0; 773 regs->hash.gaddr5 = 0; 774 regs->hash.gaddr6 = 0; 775 regs->hash.gaddr7 = 0; 776 777 regs->rctrl = 0x00000000; 778 779 /* Init RMON mib registers */ 780 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 781 782 regs->rmon.cam1 = 0xffffffff; 783 regs->rmon.cam2 = 0xffffffff; 784 785 regs->mrblr = MRBLR_INIT_SETTINGS; 786 787 regs->minflr = MINFLR_INIT_SETTINGS; 788 789 regs->attr = ATTR_INIT_SETTINGS; 790 regs->attreli = ATTRELI_INIT_SETTINGS; 791 792 } 793 794 /* Configure maccfg2 based on negotiated speed and duplex 795 * reported by PHY handling code 796 */ 797 static void adjust_link(struct eth_device *dev) 798 { 799 struct tsec_private *priv = (struct tsec_private *)dev->priv; 800 volatile tsec_t *regs = priv->regs; 801 802 if (priv->link) { 803 if (priv->duplexity != 0) 804 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 805 else 806 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 807 808 switch (priv->speed) { 809 case 1000: 810 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 811 | MACCFG2_GMII); 812 break; 813 case 100: 814 case 10: 815 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 816 | MACCFG2_MII); 817 818 /* Set R100 bit in all modes although 819 * it is only used in RGMII mode 820 */ 821 if (priv->speed == 100) 822 regs->ecntrl |= ECNTRL_R100; 823 else 824 regs->ecntrl &= ~(ECNTRL_R100); 825 break; 826 default: 827 printf("%s: Speed was bad\n", dev->name); 828 break; 829 } 830 831 printf("Speed: %d, %s duplex\n", priv->speed, 832 (priv->duplexity) ? "full" : "half"); 833 834 } else { 835 printf("%s: No link.\n", dev->name); 836 } 837 } 838 839 /* Set up the buffers and their descriptors, and bring up the 840 * interface 841 */ 842 static void startup_tsec(struct eth_device *dev) 843 { 844 int i; 845 struct tsec_private *priv = (struct tsec_private *)dev->priv; 846 volatile tsec_t *regs = priv->regs; 847 848 /* Point to the buffer descriptors */ 849 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 850 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 851 852 /* Initialize the Rx Buffer descriptors */ 853 for (i = 0; i < PKTBUFSRX; i++) { 854 rtx.rxbd[i].status = RXBD_EMPTY; 855 rtx.rxbd[i].length = 0; 856 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 857 } 858 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 859 860 /* Initialize the TX Buffer Descriptors */ 861 for (i = 0; i < TX_BUF_CNT; i++) { 862 rtx.txbd[i].status = 0; 863 rtx.txbd[i].length = 0; 864 rtx.txbd[i].bufPtr = 0; 865 } 866 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 867 868 /* Start up the PHY */ 869 if(priv->phyinfo) 870 phy_run_commands(priv, priv->phyinfo->startup); 871 872 adjust_link(dev); 873 874 /* Enable Transmit and Receive */ 875 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 876 877 /* Tell the DMA it is clear to go */ 878 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 879 regs->tstat = TSTAT_CLEAR_THALT; 880 regs->rstat = RSTAT_CLEAR_RHALT; 881 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 882 } 883 884 /* This returns the status bits of the device. The return value 885 * is never checked, and this is what the 8260 driver did, so we 886 * do the same. Presumably, this would be zero if there were no 887 * errors 888 */ 889 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 890 { 891 int i; 892 int result = 0; 893 struct tsec_private *priv = (struct tsec_private *)dev->priv; 894 volatile tsec_t *regs = priv->regs; 895 896 /* Find an empty buffer descriptor */ 897 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 898 if (i >= TOUT_LOOP) { 899 debug("%s: tsec: tx buffers full\n", dev->name); 900 return result; 901 } 902 } 903 904 rtx.txbd[txIdx].bufPtr = (uint) packet; 905 rtx.txbd[txIdx].length = length; 906 rtx.txbd[txIdx].status |= 907 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 908 909 /* Tell the DMA to go */ 910 regs->tstat = TSTAT_CLEAR_THALT; 911 912 /* Wait for buffer to be transmitted */ 913 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 914 if (i >= TOUT_LOOP) { 915 debug("%s: tsec: tx error\n", dev->name); 916 return result; 917 } 918 } 919 920 txIdx = (txIdx + 1) % TX_BUF_CNT; 921 result = rtx.txbd[txIdx].status & TXBD_STATS; 922 923 return result; 924 } 925 926 static int tsec_recv(struct eth_device *dev) 927 { 928 int length; 929 struct tsec_private *priv = (struct tsec_private *)dev->priv; 930 volatile tsec_t *regs = priv->regs; 931 932 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 933 934 length = rtx.rxbd[rxIdx].length; 935 936 /* Send the packet up if there were no errors */ 937 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 938 NetReceive(NetRxPackets[rxIdx], length - 4); 939 } else { 940 printf("Got error %x\n", 941 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 942 } 943 944 rtx.rxbd[rxIdx].length = 0; 945 946 /* Set the wrap bit if this is the last element in the list */ 947 rtx.rxbd[rxIdx].status = 948 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 949 950 rxIdx = (rxIdx + 1) % PKTBUFSRX; 951 } 952 953 if (regs->ievent & IEVENT_BSY) { 954 regs->ievent = IEVENT_BSY; 955 regs->rstat = RSTAT_CLEAR_RHALT; 956 } 957 958 return -1; 959 960 } 961 962 /* Stop the interface */ 963 static void tsec_halt(struct eth_device *dev) 964 { 965 struct tsec_private *priv = (struct tsec_private *)dev->priv; 966 volatile tsec_t *regs = priv->regs; 967 968 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 969 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 970 971 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 972 973 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 974 975 /* Shut down the PHY, as needed */ 976 if(priv->phyinfo) 977 phy_run_commands(priv, priv->phyinfo->shutdown); 978 } 979 980 struct phy_info phy_info_M88E1149S = { 981 0x1410ca, 982 "Marvell 88E1149S", 983 4, 984 (struct phy_cmd[]){ /* config */ 985 /* Reset and configure the PHY */ 986 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 987 {0x1d, 0x1f, NULL}, 988 {0x1e, 0x200c, NULL}, 989 {0x1d, 0x5, NULL}, 990 {0x1e, 0x0, NULL}, 991 {0x1e, 0x100, NULL}, 992 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 993 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 994 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 995 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 996 {miim_end,} 997 }, 998 (struct phy_cmd[]){ /* startup */ 999 /* Status is read once to clear old link state */ 1000 {MIIM_STATUS, miim_read, NULL}, 1001 /* Auto-negotiate */ 1002 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1003 /* Read the status */ 1004 {MIIM_88E1011_PHY_STATUS, miim_read, 1005 &mii_parse_88E1011_psr}, 1006 {miim_end,} 1007 }, 1008 (struct phy_cmd[]){ /* shutdown */ 1009 {miim_end,} 1010 }, 1011 }; 1012 1013 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1014 struct phy_info phy_info_BCM5461S = { 1015 0x02060c1, /* 5461 ID */ 1016 "Broadcom BCM5461S", 1017 0, /* not clear to me what minor revisions we can shift away */ 1018 (struct phy_cmd[]) { /* config */ 1019 /* Reset and configure the PHY */ 1020 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1021 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1022 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1023 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1024 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1025 {miim_end,} 1026 }, 1027 (struct phy_cmd[]) { /* startup */ 1028 /* Status is read once to clear old link state */ 1029 {MIIM_STATUS, miim_read, NULL}, 1030 /* Auto-negotiate */ 1031 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1032 /* Read the status */ 1033 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1034 {miim_end,} 1035 }, 1036 (struct phy_cmd[]) { /* shutdown */ 1037 {miim_end,} 1038 }, 1039 }; 1040 1041 struct phy_info phy_info_BCM5464S = { 1042 0x02060b1, /* 5464 ID */ 1043 "Broadcom BCM5464S", 1044 0, /* not clear to me what minor revisions we can shift away */ 1045 (struct phy_cmd[]) { /* config */ 1046 /* Reset and configure the PHY */ 1047 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1048 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1049 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1050 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1051 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1052 {miim_end,} 1053 }, 1054 (struct phy_cmd[]) { /* startup */ 1055 /* Status is read once to clear old link state */ 1056 {MIIM_STATUS, miim_read, NULL}, 1057 /* Auto-negotiate */ 1058 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1059 /* Read the status */ 1060 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1061 {miim_end,} 1062 }, 1063 (struct phy_cmd[]) { /* shutdown */ 1064 {miim_end,} 1065 }, 1066 }; 1067 1068 struct phy_info phy_info_M88E1011S = { 1069 0x01410c6, 1070 "Marvell 88E1011S", 1071 4, 1072 (struct phy_cmd[]){ /* config */ 1073 /* Reset and configure the PHY */ 1074 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1075 {0x1d, 0x1f, NULL}, 1076 {0x1e, 0x200c, NULL}, 1077 {0x1d, 0x5, NULL}, 1078 {0x1e, 0x0, NULL}, 1079 {0x1e, 0x100, NULL}, 1080 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1081 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1082 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1083 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1084 {miim_end,} 1085 }, 1086 (struct phy_cmd[]){ /* startup */ 1087 /* Status is read once to clear old link state */ 1088 {MIIM_STATUS, miim_read, NULL}, 1089 /* Auto-negotiate */ 1090 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1091 /* Read the status */ 1092 {MIIM_88E1011_PHY_STATUS, miim_read, 1093 &mii_parse_88E1011_psr}, 1094 {miim_end,} 1095 }, 1096 (struct phy_cmd[]){ /* shutdown */ 1097 {miim_end,} 1098 }, 1099 }; 1100 1101 struct phy_info phy_info_M88E1111S = { 1102 0x01410cc, 1103 "Marvell 88E1111S", 1104 4, 1105 (struct phy_cmd[]){ /* config */ 1106 /* Reset and configure the PHY */ 1107 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1108 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1109 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1110 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1111 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1112 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1113 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1114 {miim_end,} 1115 }, 1116 (struct phy_cmd[]){ /* startup */ 1117 /* Status is read once to clear old link state */ 1118 {MIIM_STATUS, miim_read, NULL}, 1119 /* Auto-negotiate */ 1120 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1121 /* Read the status */ 1122 {MIIM_88E1011_PHY_STATUS, miim_read, 1123 &mii_parse_88E1011_psr}, 1124 {miim_end,} 1125 }, 1126 (struct phy_cmd[]){ /* shutdown */ 1127 {miim_end,} 1128 }, 1129 }; 1130 1131 struct phy_info phy_info_M88E1118 = { 1132 0x01410e1, 1133 "Marvell 88E1118", 1134 4, 1135 (struct phy_cmd[]){ /* config */ 1136 /* Reset and configure the PHY */ 1137 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1138 {0x16, 0x0002, NULL}, /* Change Page Number */ 1139 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1140 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1141 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1142 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1143 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1144 {miim_end,} 1145 }, 1146 (struct phy_cmd[]){ /* startup */ 1147 {0x16, 0x0000, NULL}, /* Change Page Number */ 1148 /* Status is read once to clear old link state */ 1149 {MIIM_STATUS, miim_read, NULL}, 1150 /* Auto-negotiate */ 1151 /* Read the status */ 1152 {MIIM_88E1011_PHY_STATUS, miim_read, 1153 &mii_parse_88E1011_psr}, 1154 {miim_end,} 1155 }, 1156 (struct phy_cmd[]){ /* shutdown */ 1157 {miim_end,} 1158 }, 1159 }; 1160 1161 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1162 { 1163 uint mii_data = read_phy_reg(priv, mii_reg); 1164 1165 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1166 if (priv->flags & TSEC_REDUCED) 1167 return mii_data | 1168 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1169 else 1170 return mii_data; 1171 } 1172 1173 static struct phy_info phy_info_M88E1145 = { 1174 0x01410cd, 1175 "Marvell 88E1145", 1176 4, 1177 (struct phy_cmd[]){ /* config */ 1178 /* Reset the PHY */ 1179 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1180 1181 /* Errata E0, E1 */ 1182 {29, 0x001b, NULL}, 1183 {30, 0x418f, NULL}, 1184 {29, 0x0016, NULL}, 1185 {30, 0xa2da, NULL}, 1186 1187 /* Configure the PHY */ 1188 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1189 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1190 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1191 NULL}, 1192 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1193 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1194 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1195 {miim_end,} 1196 }, 1197 (struct phy_cmd[]){ /* startup */ 1198 /* Status is read once to clear old link state */ 1199 {MIIM_STATUS, miim_read, NULL}, 1200 /* Auto-negotiate */ 1201 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1202 {MIIM_88E1111_PHY_LED_CONTROL, 1203 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1204 /* Read the Status */ 1205 {MIIM_88E1011_PHY_STATUS, miim_read, 1206 &mii_parse_88E1011_psr}, 1207 {miim_end,} 1208 }, 1209 (struct phy_cmd[]){ /* shutdown */ 1210 {miim_end,} 1211 }, 1212 }; 1213 1214 struct phy_info phy_info_cis8204 = { 1215 0x3f11, 1216 "Cicada Cis8204", 1217 6, 1218 (struct phy_cmd[]){ /* config */ 1219 /* Override PHY config settings */ 1220 {MIIM_CIS8201_AUX_CONSTAT, 1221 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1222 /* Configure some basic stuff */ 1223 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1224 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1225 &mii_cis8204_fixled}, 1226 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1227 &mii_cis8204_setmode}, 1228 {miim_end,} 1229 }, 1230 (struct phy_cmd[]){ /* startup */ 1231 /* Read the Status (2x to make sure link is right) */ 1232 {MIIM_STATUS, miim_read, NULL}, 1233 /* Auto-negotiate */ 1234 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1235 /* Read the status */ 1236 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1237 &mii_parse_cis8201}, 1238 {miim_end,} 1239 }, 1240 (struct phy_cmd[]){ /* shutdown */ 1241 {miim_end,} 1242 }, 1243 }; 1244 1245 /* Cicada 8201 */ 1246 struct phy_info phy_info_cis8201 = { 1247 0xfc41, 1248 "CIS8201", 1249 4, 1250 (struct phy_cmd[]){ /* config */ 1251 /* Override PHY config settings */ 1252 {MIIM_CIS8201_AUX_CONSTAT, 1253 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1254 /* Set up the interface mode */ 1255 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1256 NULL}, 1257 /* Configure some basic stuff */ 1258 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1259 {miim_end,} 1260 }, 1261 (struct phy_cmd[]){ /* startup */ 1262 /* Read the Status (2x to make sure link is right) */ 1263 {MIIM_STATUS, miim_read, NULL}, 1264 /* Auto-negotiate */ 1265 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1266 /* Read the status */ 1267 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1268 &mii_parse_cis8201}, 1269 {miim_end,} 1270 }, 1271 (struct phy_cmd[]){ /* shutdown */ 1272 {miim_end,} 1273 }, 1274 }; 1275 struct phy_info phy_info_VSC8244 = { 1276 0x3f1b, 1277 "Vitesse VSC8244", 1278 6, 1279 (struct phy_cmd[]){ /* config */ 1280 /* Override PHY config settings */ 1281 /* Configure some basic stuff */ 1282 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1283 {miim_end,} 1284 }, 1285 (struct phy_cmd[]){ /* startup */ 1286 /* Read the Status (2x to make sure link is right) */ 1287 {MIIM_STATUS, miim_read, NULL}, 1288 /* Auto-negotiate */ 1289 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1290 /* Read the status */ 1291 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1292 &mii_parse_vsc8244}, 1293 {miim_end,} 1294 }, 1295 (struct phy_cmd[]){ /* shutdown */ 1296 {miim_end,} 1297 }, 1298 }; 1299 1300 struct phy_info phy_info_VSC8601 = { 1301 0x00007042, 1302 "Vitesse VSC8601", 1303 4, 1304 (struct phy_cmd[]){ /* config */ 1305 /* Override PHY config settings */ 1306 /* Configure some basic stuff */ 1307 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1308 #ifdef CFG_VSC8601_SKEWFIX 1309 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1310 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) 1311 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1312 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) 1313 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1314 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1315 #endif 1316 #endif 1317 {miim_end,} 1318 }, 1319 (struct phy_cmd[]){ /* startup */ 1320 /* Read the Status (2x to make sure link is right) */ 1321 {MIIM_STATUS, miim_read, NULL}, 1322 /* Auto-negotiate */ 1323 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1324 /* Read the status */ 1325 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1326 &mii_parse_vsc8244}, 1327 {miim_end,} 1328 }, 1329 (struct phy_cmd[]){ /* shutdown */ 1330 {miim_end,} 1331 }, 1332 }; 1333 1334 1335 struct phy_info phy_info_dm9161 = { 1336 0x0181b88, 1337 "Davicom DM9161E", 1338 4, 1339 (struct phy_cmd[]){ /* config */ 1340 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1341 /* Do not bypass the scrambler/descrambler */ 1342 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1343 /* Clear 10BTCSR to default */ 1344 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1345 NULL}, 1346 /* Configure some basic stuff */ 1347 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1348 /* Restart Auto Negotiation */ 1349 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1350 {miim_end,} 1351 }, 1352 (struct phy_cmd[]){ /* startup */ 1353 /* Status is read once to clear old link state */ 1354 {MIIM_STATUS, miim_read, NULL}, 1355 /* Auto-negotiate */ 1356 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1357 /* Read the status */ 1358 {MIIM_DM9161_SCSR, miim_read, 1359 &mii_parse_dm9161_scsr}, 1360 {miim_end,} 1361 }, 1362 (struct phy_cmd[]){ /* shutdown */ 1363 {miim_end,} 1364 }, 1365 }; 1366 /* a generic flavor. */ 1367 struct phy_info phy_info_generic = { 1368 0, 1369 "Unknown/Generic PHY", 1370 32, 1371 (struct phy_cmd[]) { /* config */ 1372 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1373 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1374 {miim_end,} 1375 }, 1376 (struct phy_cmd[]) { /* startup */ 1377 {PHY_BMSR, miim_read, NULL}, 1378 {PHY_BMSR, miim_read, &mii_parse_sr}, 1379 {PHY_BMSR, miim_read, &mii_parse_link}, 1380 {miim_end,} 1381 }, 1382 (struct phy_cmd[]) { /* shutdown */ 1383 {miim_end,} 1384 } 1385 }; 1386 1387 1388 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1389 { 1390 unsigned int speed; 1391 if (priv->link) { 1392 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1393 1394 switch (speed) { 1395 case MIIM_LXT971_SR2_10HDX: 1396 priv->speed = 10; 1397 priv->duplexity = 0; 1398 break; 1399 case MIIM_LXT971_SR2_10FDX: 1400 priv->speed = 10; 1401 priv->duplexity = 1; 1402 break; 1403 case MIIM_LXT971_SR2_100HDX: 1404 priv->speed = 100; 1405 priv->duplexity = 0; 1406 break; 1407 default: 1408 priv->speed = 100; 1409 priv->duplexity = 1; 1410 } 1411 } else { 1412 priv->speed = 0; 1413 priv->duplexity = 0; 1414 } 1415 1416 return 0; 1417 } 1418 1419 static struct phy_info phy_info_lxt971 = { 1420 0x0001378e, 1421 "LXT971", 1422 4, 1423 (struct phy_cmd[]){ /* config */ 1424 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1425 {miim_end,} 1426 }, 1427 (struct phy_cmd[]){ /* startup - enable interrupts */ 1428 /* { 0x12, 0x00f2, NULL }, */ 1429 {MIIM_STATUS, miim_read, NULL}, 1430 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1431 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1432 {miim_end,} 1433 }, 1434 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1435 {miim_end,} 1436 }, 1437 }; 1438 1439 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1440 * information 1441 */ 1442 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1443 { 1444 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1445 1446 case MIIM_DP83865_SPD_1000: 1447 priv->speed = 1000; 1448 break; 1449 1450 case MIIM_DP83865_SPD_100: 1451 priv->speed = 100; 1452 break; 1453 1454 default: 1455 priv->speed = 10; 1456 break; 1457 1458 } 1459 1460 if (mii_reg & MIIM_DP83865_DPX_FULL) 1461 priv->duplexity = 1; 1462 else 1463 priv->duplexity = 0; 1464 1465 return 0; 1466 } 1467 1468 struct phy_info phy_info_dp83865 = { 1469 0x20005c7, 1470 "NatSemi DP83865", 1471 4, 1472 (struct phy_cmd[]){ /* config */ 1473 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1474 {miim_end,} 1475 }, 1476 (struct phy_cmd[]){ /* startup */ 1477 /* Status is read once to clear old link state */ 1478 {MIIM_STATUS, miim_read, NULL}, 1479 /* Auto-negotiate */ 1480 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1481 /* Read the link and auto-neg status */ 1482 {MIIM_DP83865_LANR, miim_read, 1483 &mii_parse_dp83865_lanr}, 1484 {miim_end,} 1485 }, 1486 (struct phy_cmd[]){ /* shutdown */ 1487 {miim_end,} 1488 }, 1489 }; 1490 1491 struct phy_info phy_info_rtl8211b = { 1492 0x001cc91, 1493 "RealTek RTL8211B", 1494 4, 1495 (struct phy_cmd[]){ /* config */ 1496 /* Reset and configure the PHY */ 1497 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1498 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1499 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1500 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1501 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1502 {miim_end,} 1503 }, 1504 (struct phy_cmd[]){ /* startup */ 1505 /* Status is read once to clear old link state */ 1506 {MIIM_STATUS, miim_read, NULL}, 1507 /* Auto-negotiate */ 1508 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1509 /* Read the status */ 1510 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1511 {miim_end,} 1512 }, 1513 (struct phy_cmd[]){ /* shutdown */ 1514 {miim_end,} 1515 }, 1516 }; 1517 1518 struct phy_info *phy_info[] = { 1519 &phy_info_cis8204, 1520 &phy_info_cis8201, 1521 &phy_info_BCM5461S, 1522 &phy_info_BCM5464S, 1523 &phy_info_M88E1011S, 1524 &phy_info_M88E1111S, 1525 &phy_info_M88E1118, 1526 &phy_info_M88E1145, 1527 &phy_info_M88E1149S, 1528 &phy_info_dm9161, 1529 &phy_info_lxt971, 1530 &phy_info_VSC8244, 1531 &phy_info_VSC8601, 1532 &phy_info_dp83865, 1533 &phy_info_rtl8211b, 1534 &phy_info_generic, 1535 NULL 1536 }; 1537 1538 /* Grab the identifier of the device's PHY, and search through 1539 * all of the known PHYs to see if one matches. If so, return 1540 * it, if not, return NULL 1541 */ 1542 struct phy_info *get_phy_info(struct eth_device *dev) 1543 { 1544 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1545 uint phy_reg, phy_ID; 1546 int i; 1547 struct phy_info *theInfo = NULL; 1548 1549 /* Grab the bits from PHYIR1, and put them in the upper half */ 1550 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1551 phy_ID = (phy_reg & 0xffff) << 16; 1552 1553 /* Grab the bits from PHYIR2, and put them in the lower half */ 1554 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1555 phy_ID |= (phy_reg & 0xffff); 1556 1557 /* loop through all the known PHY types, and find one that */ 1558 /* matches the ID we read from the PHY. */ 1559 for (i = 0; phy_info[i]; i++) { 1560 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1561 theInfo = phy_info[i]; 1562 break; 1563 } 1564 } 1565 1566 if (theInfo == NULL) { 1567 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1568 return NULL; 1569 } else { 1570 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1571 } 1572 1573 return theInfo; 1574 } 1575 1576 /* Execute the given series of commands on the given device's 1577 * PHY, running functions as necessary 1578 */ 1579 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1580 { 1581 int i; 1582 uint result; 1583 volatile tsec_t *phyregs = priv->phyregs; 1584 1585 phyregs->miimcfg = MIIMCFG_RESET; 1586 1587 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1588 1589 while (phyregs->miimind & MIIMIND_BUSY) ; 1590 1591 for (i = 0; cmd->mii_reg != miim_end; i++) { 1592 if (cmd->mii_data == miim_read) { 1593 result = read_phy_reg(priv, cmd->mii_reg); 1594 1595 if (cmd->funct != NULL) 1596 (*(cmd->funct)) (result, priv); 1597 1598 } else { 1599 if (cmd->funct != NULL) 1600 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1601 else 1602 result = cmd->mii_data; 1603 1604 write_phy_reg(priv, cmd->mii_reg, result); 1605 1606 } 1607 cmd++; 1608 } 1609 } 1610 1611 /* Relocate the function pointers in the phy cmd lists */ 1612 static void relocate_cmds(void) 1613 { 1614 struct phy_cmd **cmdlistptr; 1615 struct phy_cmd *cmd; 1616 int i, j, k; 1617 1618 for (i = 0; phy_info[i]; i++) { 1619 /* First thing's first: relocate the pointers to the 1620 * PHY command structures (the structs were done) */ 1621 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1622 + gd->reloc_off); 1623 phy_info[i]->name += gd->reloc_off; 1624 phy_info[i]->config = 1625 (struct phy_cmd *)((uint) phy_info[i]->config 1626 + gd->reloc_off); 1627 phy_info[i]->startup = 1628 (struct phy_cmd *)((uint) phy_info[i]->startup 1629 + gd->reloc_off); 1630 phy_info[i]->shutdown = 1631 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1632 + gd->reloc_off); 1633 1634 cmdlistptr = &phy_info[i]->config; 1635 j = 0; 1636 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1637 k = 0; 1638 for (cmd = *cmdlistptr; 1639 cmd->mii_reg != miim_end; 1640 cmd++) { 1641 /* Only relocate non-NULL pointers */ 1642 if (cmd->funct) 1643 cmd->funct += gd->reloc_off; 1644 1645 k++; 1646 } 1647 j++; 1648 } 1649 } 1650 1651 relocated = 1; 1652 } 1653 1654 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1655 && !defined(BITBANGMII) 1656 1657 /* 1658 * Read a MII PHY register. 1659 * 1660 * Returns: 1661 * 0 on success 1662 */ 1663 static int tsec_miiphy_read(char *devname, unsigned char addr, 1664 unsigned char reg, unsigned short *value) 1665 { 1666 unsigned short ret; 1667 struct tsec_private *priv = privlist[0]; 1668 1669 if (NULL == priv) { 1670 printf("Can't read PHY at address %d\n", addr); 1671 return -1; 1672 } 1673 1674 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1675 *value = ret; 1676 1677 return 0; 1678 } 1679 1680 /* 1681 * Write a MII PHY register. 1682 * 1683 * Returns: 1684 * 0 on success 1685 */ 1686 static int tsec_miiphy_write(char *devname, unsigned char addr, 1687 unsigned char reg, unsigned short value) 1688 { 1689 struct tsec_private *priv = privlist[0]; 1690 1691 if (NULL == priv) { 1692 printf("Can't write PHY at address %d\n", addr); 1693 return -1; 1694 } 1695 1696 write_any_phy_reg(priv, addr, reg, value); 1697 1698 return 0; 1699 } 1700 1701 #endif 1702 1703 #ifdef CONFIG_MCAST_TFTP 1704 1705 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1706 1707 /* Set the appropriate hash bit for the given addr */ 1708 1709 /* The algorithm works like so: 1710 * 1) Take the Destination Address (ie the multicast address), and 1711 * do a CRC on it (little endian), and reverse the bits of the 1712 * result. 1713 * 2) Use the 8 most significant bits as a hash into a 256-entry 1714 * table. The table is controlled through 8 32-bit registers: 1715 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1716 * gaddr7. This means that the 3 most significant bits in the 1717 * hash index which gaddr register to use, and the 5 other bits 1718 * indicate which bit (assuming an IBM numbering scheme, which 1719 * for PowerPC (tm) is usually the case) in the tregister holds 1720 * the entry. */ 1721 static int 1722 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1723 { 1724 struct tsec_private *priv = privlist[1]; 1725 volatile tsec_t *regs = priv->regs; 1726 volatile u32 *reg_array, value; 1727 u8 result, whichbit, whichreg; 1728 1729 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1730 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1731 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1732 value = (1 << (31-whichbit)); 1733 1734 reg_array = &(regs->hash.gaddr0); 1735 1736 if (set) { 1737 reg_array[whichreg] |= value; 1738 } else { 1739 reg_array[whichreg] &= ~value; 1740 } 1741 return 0; 1742 } 1743 #endif /* Multicast TFTP ? */ 1744 1745 #endif /* CONFIG_TSEC_ENET */ 1746