1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp. 5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <netdev.h> 12 #include <asm/types.h> 13 14 #define SHETHER_NAME "sh_eth" 15 16 #if defined(CONFIG_SH) 17 /* Malloc returns addresses in the P1 area (cacheable). However we need to 18 use area P2 (non-cacheable) */ 19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 20 21 /* The ethernet controller needs to use physical addresses */ 22 #if defined(CONFIG_SH_32BIT) 23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 24 #else 25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 26 #endif 27 #elif defined(CONFIG_ARM) 28 #define inl readl 29 #define outl writel 30 #define ADDR_TO_PHY(addr) ((int)(addr)) 31 #define ADDR_TO_P2(addr) (addr) 32 #endif /* defined(CONFIG_SH) */ 33 34 /* base padding size is 16 */ 35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE 36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 54 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ 55 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 56 57 /* Tx descriptor. We always use 3 bytes of padding */ 58 struct tx_desc_s { 59 volatile u32 td0; 60 u32 td1; 61 u32 td2; /* Buffer start */ 62 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 63 }; 64 65 /* There is no limitation in the number of rx descriptors */ 66 #define NUM_RX_DESC 8 67 68 /* The size of the rx descriptor is determined by how much padding is used. 69 4, 20, or 52 bytes of padding can be used */ 70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 71 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ 72 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 73 /* aligned cache line size */ 74 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) 75 76 /* Rx descriptor. We always use 4 bytes of padding */ 77 struct rx_desc_s { 78 volatile u32 rd0; 79 volatile u32 rd1; 80 u32 rd2; /* Buffer start */ 81 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 82 }; 83 84 struct sh_eth_info { 85 struct tx_desc_s *tx_desc_malloc; 86 struct tx_desc_s *tx_desc_base; 87 struct tx_desc_s *tx_desc_cur; 88 struct rx_desc_s *rx_desc_malloc; 89 struct rx_desc_s *rx_desc_base; 90 struct rx_desc_s *rx_desc_cur; 91 u8 *rx_buf_malloc; 92 u8 *rx_buf_base; 93 u8 mac_addr[6]; 94 u8 phy_addr; 95 struct eth_device *dev; 96 struct phy_device *phydev; 97 }; 98 99 struct sh_eth_dev { 100 int port; 101 struct sh_eth_info port_info[MAX_PORT_NUM]; 102 }; 103 104 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 105 enum { 106 /* E-DMAC registers */ 107 EDSR = 0, 108 EDMR, 109 EDTRR, 110 EDRRR, 111 EESR, 112 EESIPR, 113 TDLAR, 114 TDFAR, 115 TDFXR, 116 TDFFR, 117 RDLAR, 118 RDFAR, 119 RDFXR, 120 RDFFR, 121 TRSCER, 122 RMFCR, 123 TFTR, 124 FDR, 125 RMCR, 126 EDOCR, 127 TFUCR, 128 RFOCR, 129 FCFTR, 130 RPADIR, 131 TRIMD, 132 RBWAR, 133 TBRAR, 134 135 /* Ether registers */ 136 ECMR, 137 ECSR, 138 ECSIPR, 139 PIR, 140 PSR, 141 RDMLR, 142 PIPR, 143 RFLR, 144 IPGR, 145 APR, 146 MPR, 147 PFTCR, 148 PFRCR, 149 RFCR, 150 RFCF, 151 TPAUSER, 152 TPAUSECR, 153 BCFR, 154 BCFRR, 155 GECMR, 156 BCULR, 157 MAHR, 158 MALR, 159 TROCR, 160 CDCR, 161 LCCR, 162 CNDCR, 163 CEFCR, 164 FRECR, 165 TSFRCR, 166 TLFRCR, 167 CERCR, 168 CEECR, 169 MAFCR, 170 RTRATE, 171 CSMR, 172 RMII_MII, 173 174 /* This value must be written at last. */ 175 SH_ETH_MAX_REGISTER_OFFSET, 176 }; 177 178 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 179 [EDSR] = 0x0000, 180 [EDMR] = 0x0400, 181 [EDTRR] = 0x0408, 182 [EDRRR] = 0x0410, 183 [EESR] = 0x0428, 184 [EESIPR] = 0x0430, 185 [TDLAR] = 0x0010, 186 [TDFAR] = 0x0014, 187 [TDFXR] = 0x0018, 188 [TDFFR] = 0x001c, 189 [RDLAR] = 0x0030, 190 [RDFAR] = 0x0034, 191 [RDFXR] = 0x0038, 192 [RDFFR] = 0x003c, 193 [TRSCER] = 0x0438, 194 [RMFCR] = 0x0440, 195 [TFTR] = 0x0448, 196 [FDR] = 0x0450, 197 [RMCR] = 0x0458, 198 [RPADIR] = 0x0460, 199 [FCFTR] = 0x0468, 200 [CSMR] = 0x04E4, 201 202 [ECMR] = 0x0500, 203 [ECSR] = 0x0510, 204 [ECSIPR] = 0x0518, 205 [PIR] = 0x0520, 206 [PSR] = 0x0528, 207 [PIPR] = 0x052c, 208 [RFLR] = 0x0508, 209 [APR] = 0x0554, 210 [MPR] = 0x0558, 211 [PFTCR] = 0x055c, 212 [PFRCR] = 0x0560, 213 [TPAUSER] = 0x0564, 214 [GECMR] = 0x05b0, 215 [BCULR] = 0x05b4, 216 [MAHR] = 0x05c0, 217 [MALR] = 0x05c8, 218 [TROCR] = 0x0700, 219 [CDCR] = 0x0708, 220 [LCCR] = 0x0710, 221 [CEFCR] = 0x0740, 222 [FRECR] = 0x0748, 223 [TSFRCR] = 0x0750, 224 [TLFRCR] = 0x0758, 225 [RFCR] = 0x0760, 226 [CERCR] = 0x0768, 227 [CEECR] = 0x0770, 228 [MAFCR] = 0x0778, 229 [RMII_MII] = 0x0790, 230 }; 231 232 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 233 [ECMR] = 0x0100, 234 [RFLR] = 0x0108, 235 [ECSR] = 0x0110, 236 [ECSIPR] = 0x0118, 237 [PIR] = 0x0120, 238 [PSR] = 0x0128, 239 [RDMLR] = 0x0140, 240 [IPGR] = 0x0150, 241 [APR] = 0x0154, 242 [MPR] = 0x0158, 243 [TPAUSER] = 0x0164, 244 [RFCF] = 0x0160, 245 [TPAUSECR] = 0x0168, 246 [BCFRR] = 0x016c, 247 [MAHR] = 0x01c0, 248 [MALR] = 0x01c8, 249 [TROCR] = 0x01d0, 250 [CDCR] = 0x01d4, 251 [LCCR] = 0x01d8, 252 [CNDCR] = 0x01dc, 253 [CEFCR] = 0x01e4, 254 [FRECR] = 0x01e8, 255 [TSFRCR] = 0x01ec, 256 [TLFRCR] = 0x01f0, 257 [RFCR] = 0x01f4, 258 [MAFCR] = 0x01f8, 259 [RTRATE] = 0x01fc, 260 261 [EDMR] = 0x0000, 262 [EDTRR] = 0x0008, 263 [EDRRR] = 0x0010, 264 [TDLAR] = 0x0018, 265 [RDLAR] = 0x0020, 266 [EESR] = 0x0028, 267 [EESIPR] = 0x0030, 268 [TRSCER] = 0x0038, 269 [RMFCR] = 0x0040, 270 [TFTR] = 0x0048, 271 [FDR] = 0x0050, 272 [RMCR] = 0x0058, 273 [TFUCR] = 0x0064, 274 [RFOCR] = 0x0068, 275 [FCFTR] = 0x0070, 276 [RPADIR] = 0x0078, 277 [TRIMD] = 0x007c, 278 [RBWAR] = 0x00c8, 279 [RDFAR] = 0x00cc, 280 [TBRAR] = 0x00d4, 281 [TDFAR] = 0x00d8, 282 }; 283 284 /* Register Address */ 285 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 286 #define SH_ETH_TYPE_GETHER 287 #define BASE_IO_ADDR 0xfee00000 288 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 289 #if defined(CONFIG_SH_ETHER_USE_GETHER) 290 #define SH_ETH_TYPE_GETHER 291 #define BASE_IO_ADDR 0xfee00000 292 #else 293 #define SH_ETH_TYPE_ETHER 294 #define BASE_IO_ADDR 0xfef00000 295 #endif 296 #elif defined(CONFIG_CPU_SH7724) 297 #define SH_ETH_TYPE_ETHER 298 #define BASE_IO_ADDR 0xA4600000 299 #elif defined(CONFIG_R8A7740) 300 #define SH_ETH_TYPE_GETHER 301 #define BASE_IO_ADDR 0xE9A00000 302 #endif 303 304 /* 305 * Register's bits 306 * Copy from Linux driver source code 307 */ 308 #if defined(SH_ETH_TYPE_GETHER) 309 /* EDSR */ 310 enum EDSR_BIT { 311 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 312 }; 313 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 314 #endif 315 316 /* EDMR */ 317 enum DMAC_M_BIT { 318 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 319 #if defined(SH_ETH_TYPE_GETHER) 320 EDMR_SRST = 0x03, /* Receive/Send reset */ 321 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 322 EDMR_EL = 0x40, /* Litte endian */ 323 #elif defined(SH_ETH_TYPE_ETHER) 324 EDMR_SRST = 0x01, 325 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 326 EDMR_EL = 0x40, /* Litte endian */ 327 #else 328 EDMR_SRST = 0x01, 329 #endif 330 }; 331 332 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 333 # define EMDR_DESC EDMR_DL1 334 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 335 # define EMDR_DESC EDMR_DL0 336 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ 337 # define EMDR_DESC 0 338 #endif 339 340 /* RFLR */ 341 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 342 343 /* EDTRR */ 344 enum DMAC_T_BIT { 345 #if defined(SH_ETH_TYPE_GETHER) 346 EDTRR_TRNS = 0x03, 347 #else 348 EDTRR_TRNS = 0x01, 349 #endif 350 }; 351 352 /* GECMR */ 353 enum GECMR_BIT { 354 #if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 355 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 356 #else 357 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 358 #endif 359 }; 360 361 /* EDRRR*/ 362 enum EDRRR_R_BIT { 363 EDRRR_R = 0x01, 364 }; 365 366 /* TPAUSER */ 367 enum TPAUSER_BIT { 368 TPAUSER_TPAUSE = 0x0000ffff, 369 TPAUSER_UNLIMITED = 0, 370 }; 371 372 /* BCFR */ 373 enum BCFR_BIT { 374 BCFR_RPAUSE = 0x0000ffff, 375 BCFR_UNLIMITED = 0, 376 }; 377 378 /* PIR */ 379 enum PIR_BIT { 380 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 381 }; 382 383 /* PSR */ 384 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 385 386 /* EESR */ 387 enum EESR_BIT { 388 389 #if defined(SH_ETH_TYPE_ETHER) 390 EESR_TWB = 0x40000000, 391 #else 392 EESR_TWB = 0xC0000000, 393 EESR_TC1 = 0x20000000, 394 EESR_TUC = 0x10000000, 395 EESR_ROC = 0x80000000, 396 #endif 397 EESR_TABT = 0x04000000, 398 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 399 #if defined(SH_ETH_TYPE_ETHER) 400 EESR_ADE = 0x00800000, 401 #endif 402 EESR_ECI = 0x00400000, 403 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 404 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 405 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 406 #if defined(SH_ETH_TYPE_ETHER) 407 EESR_CND = 0x00000800, 408 #endif 409 EESR_DLC = 0x00000400, 410 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 411 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 412 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 413 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 414 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 415 }; 416 417 418 #if defined(SH_ETH_TYPE_GETHER) 419 # define TX_CHECK (EESR_TC1 | EESR_FTC) 420 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 421 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 422 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 423 424 #else 425 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 426 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 427 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 428 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 429 #endif 430 431 /* EESIPR */ 432 enum DMAC_IM_BIT { 433 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 434 DMAC_M_RABT = 0x02000000, 435 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 436 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 437 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 438 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 439 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 440 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 441 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 442 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 443 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 444 DMAC_M_RINT1 = 0x00000001, 445 }; 446 447 /* Receive descriptor bit */ 448 enum RD_STS_BIT { 449 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 450 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 451 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 452 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 453 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 454 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 455 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 456 RD_RFS1 = 0x00000001, 457 }; 458 #define RDF1ST RD_RFP1 459 #define RDFEND RD_RFP0 460 #define RD_RFP (RD_RFP1|RD_RFP0) 461 462 /* RDFFR*/ 463 enum RDFFR_BIT { 464 RDFFR_RDLF = 0x01, 465 }; 466 467 /* FCFTR */ 468 enum FCFTR_BIT { 469 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 470 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 471 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 472 }; 473 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 474 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 475 476 /* Transfer descriptor bit */ 477 enum TD_STS_BIT { 478 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) 479 TD_TACT = 0x80000000, 480 #else 481 TD_TACT = 0x7fffffff, 482 #endif 483 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 484 TD_TFP0 = 0x10000000, 485 }; 486 #define TDF1ST TD_TFP1 487 #define TDFEND TD_TFP0 488 #define TD_TFP (TD_TFP1|TD_TFP0) 489 490 /* RMCR */ 491 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 492 /* ECMR */ 493 enum FELIC_MODE_BIT { 494 #if defined(SH_ETH_TYPE_GETHER) 495 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 496 ECMR_RZPF = 0x00100000, 497 #endif 498 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 499 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 500 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 501 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 502 ECMR_PRM = 0x00000001, 503 #ifdef CONFIG_CPU_SH7724 504 ECMR_RTM = 0x00000010, 505 #endif 506 507 }; 508 509 #if defined(SH_ETH_TYPE_GETHER) 510 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 511 ECMR_TXF | ECMR_MCT) 512 #elif defined(SH_ETH_TYPE_ETHER) 513 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 514 #else 515 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 516 #endif 517 518 /* ECSR */ 519 enum ECSR_STATUS_BIT { 520 #if defined(SH_ETH_TYPE_ETHER) 521 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 522 #endif 523 ECSR_LCHNG = 0x04, 524 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 525 }; 526 527 #if defined(SH_ETH_TYPE_GETHER) 528 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 529 #else 530 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 531 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 532 #endif 533 534 /* ECSIPR */ 535 enum ECSIPR_STATUS_MASK_BIT { 536 #if defined(SH_ETH_TYPE_ETHER) 537 ECSIPR_BRCRXIP = 0x20, 538 ECSIPR_PSRTOIP = 0x10, 539 #elif defined(SH_ETY_TYPE_GETHER) 540 ECSIPR_PSRTOIP = 0x10, 541 ECSIPR_PHYIP = 0x08, 542 #endif 543 ECSIPR_LCHNGIP = 0x04, 544 ECSIPR_MPDIP = 0x02, 545 ECSIPR_ICDIP = 0x01, 546 }; 547 548 #if defined(SH_ETH_TYPE_GETHER) 549 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 550 #else 551 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 552 ECSIPR_ICDIP | ECSIPR_MPDIP) 553 #endif 554 555 /* APR */ 556 enum APR_BIT { 557 APR_AP = 0x00000004, 558 }; 559 560 /* MPR */ 561 enum MPR_BIT { 562 MPR_MP = 0x00000006, 563 }; 564 565 /* TRSCER */ 566 enum DESC_I_BIT { 567 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 568 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 569 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 570 DESC_I_RINT1 = 0x0001, 571 }; 572 573 /* RPADIR */ 574 enum RPADIR_BIT { 575 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 576 RPADIR_PADR = 0x0003f, 577 }; 578 579 #if defined(SH_ETH_TYPE_GETHER) 580 # define RPADIR_INIT (0x00) 581 #else 582 # define RPADIR_INIT (RPADIR_PADS1) 583 #endif 584 585 /* FDR */ 586 enum FIFO_SIZE_BIT { 587 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 588 }; 589 590 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, 591 int enum_index) 592 { 593 #if defined(SH_ETH_TYPE_GETHER) 594 const u16 *reg_offset = sh_eth_offset_gigabit; 595 #elif defined(SH_ETH_TYPE_ETHER) 596 const u16 *reg_offset = sh_eth_offset_fast_sh4; 597 #else 598 #error 599 #endif 600 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; 601 } 602 603 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, 604 int enum_index) 605 { 606 outl(data, sh_eth_reg_addr(eth, enum_index)); 607 } 608 609 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, 610 int enum_index) 611 { 612 return inl(sh_eth_reg_addr(eth, enum_index)); 613 } 614