1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <netdev.h> 24 #include <asm/types.h> 25 26 #define SHETHER_NAME "sh_eth" 27 28 /* Malloc returns addresses in the P1 area (cacheable). However we need to 29 use area P2 (non-cacheable) */ 30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 31 32 /* The ethernet controller needs to use physical addresses */ 33 #if defined(CONFIG_SH_32BIT) 34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 35 #else 36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING 4 54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 55 56 /* Tx descriptor. We always use 3 bytes of padding */ 57 struct tx_desc_s { 58 volatile u32 td0; 59 u32 td1; 60 u32 td2; /* Buffer start */ 61 u32 padding; 62 }; 63 64 /* There is no limitation in the number of rx descriptors */ 65 #define NUM_RX_DESC 8 66 67 /* The size of the rx descriptor is determined by how much padding is used. 68 4, 20, or 52 bytes of padding can be used */ 69 #define RX_DESC_PADDING 4 70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u32 padding; 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_malloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_malloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_malloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 struct phy_device *phydev; 93 }; 94 95 struct sh_eth_dev { 96 int port; 97 struct sh_eth_info port_info[MAX_PORT_NUM]; 98 }; 99 100 /* Register Address */ 101 #ifdef CONFIG_CPU_SH7763 102 #define BASE_IO_ADDR 0xfee00000 103 104 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 105 106 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 107 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) 108 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 109 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) 110 111 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 112 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) 113 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 114 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) 115 116 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) 117 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) 118 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) 119 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) 120 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) 121 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) 122 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) 123 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) 124 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) 125 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) 126 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) 127 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) 128 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) 129 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) 130 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) 131 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) 132 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) 133 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) 134 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) 135 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) 136 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) 137 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) 138 139 #elif defined(CONFIG_CPU_SH7757) 140 #define BASE_IO_ADDR 0xfef00000 141 142 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 143 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) 144 145 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 146 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) 147 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 148 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) 149 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 150 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 151 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) 152 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) 153 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) 154 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) 155 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) 156 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) 157 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) 158 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) 159 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) 160 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) 161 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) 162 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) 163 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) 164 #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) 165 166 #elif defined(CONFIG_CPU_SH7724) 167 #define BASE_IO_ADDR 0xA4600000 168 169 #define TDLAR(port) (BASE_IO_ADDR + 0x0018) 170 #define RDLAR(port) (BASE_IO_ADDR + 0x0020) 171 172 #define EDMR(port) (BASE_IO_ADDR + 0x0000) 173 #define EDTRR(port) (BASE_IO_ADDR + 0x0008) 174 #define EDRRR(port) (BASE_IO_ADDR + 0x0010) 175 #define EESR(port) (BASE_IO_ADDR + 0x0028) 176 #define EESIPR(port) (BASE_IO_ADDR + 0x0030) 177 #define TRSCER(port) (BASE_IO_ADDR + 0x0038) 178 #define TFTR(port) (BASE_IO_ADDR + 0x0048) 179 #define FDR(port) (BASE_IO_ADDR + 0x0050) 180 #define RMCR(port) (BASE_IO_ADDR + 0x0058) 181 #define FCFTR(port) (BASE_IO_ADDR + 0x0070) 182 #define ECMR(port) (BASE_IO_ADDR + 0x0100) 183 #define RFLR(port) (BASE_IO_ADDR + 0x0108) 184 #define ECSIPR(port) (BASE_IO_ADDR + 0x0118) 185 #define PIR(port) (BASE_IO_ADDR + 0x0120) 186 #define APR(port) (BASE_IO_ADDR + 0x0154) 187 #define MPR(port) (BASE_IO_ADDR + 0x0158) 188 #define TPAUSER(port) (BASE_IO_ADDR + 0x0164) 189 #define MAHR(port) (BASE_IO_ADDR + 0x01c0) 190 #define MALR(port) (BASE_IO_ADDR + 0x01c8) 191 192 #elif defined(CONFIG_CPU_SH7734) 193 #define BASE_IO_ADDR 0xFEE00000 194 195 #define EDSR(port) (BASE_IO_ADDR) 196 197 #define TDLAR(port) (BASE_IO_ADDR + 0x0010) 198 #define TDFAR(port) (BASE_IO_ADDR + 0x0014) 199 #define TDFXR(port) (BASE_IO_ADDR + 0x0018) 200 #define TDFFR(port) (BASE_IO_ADDR + 0x001c) 201 #define RDLAR(port) (BASE_IO_ADDR + 0x0030) 202 #define RDFAR(port) (BASE_IO_ADDR + 0x0034) 203 #define RDFXR(port) (BASE_IO_ADDR + 0x0038) 204 #define RDFFR(port) (BASE_IO_ADDR + 0x003c) 205 206 #define EDMR(port) (BASE_IO_ADDR + 0x0400) 207 #define EDTRR(port) (BASE_IO_ADDR + 0x0408) 208 #define EDRRR(port) (BASE_IO_ADDR + 0x0410) 209 #define EESR(port) (BASE_IO_ADDR + 0x0428) 210 #define EESIPR(port) (BASE_IO_ADDR + 0x0430) 211 #define TRSCER(port) (BASE_IO_ADDR + 0x0438) 212 #define TFTR(port) (BASE_IO_ADDR + 0x0448) 213 #define FDR(port) (BASE_IO_ADDR + 0x0450) 214 #define RMCR(port) (BASE_IO_ADDR + 0x0458) 215 #define RPADIR(port) (BASE_IO_ADDR + 0x0460) 216 #define FCFTR(port) (BASE_IO_ADDR + 0x0468) 217 #define ECMR(port) (BASE_IO_ADDR + 0x0500) 218 #define RFLR(port) (BASE_IO_ADDR + 0x0508) 219 #define ECSIPR(port) (BASE_IO_ADDR + 0x0518) 220 #define PIR(port) (BASE_IO_ADDR + 0x0520) 221 #define PIPR(port) (BASE_IO_ADDR + 0x052c) 222 #define APR(port) (BASE_IO_ADDR + 0x0554) 223 #define MPR(port) (BASE_IO_ADDR + 0x0558) 224 #define TPAUSER(port) (BASE_IO_ADDR + 0x0564) 225 #define GECMR(port) (BASE_IO_ADDR + 0x05b0) 226 #define MAHR(port) (BASE_IO_ADDR + 0x05C0) 227 #define MALR(port) (BASE_IO_ADDR + 0x05C8) 228 229 #endif 230 231 /* 232 * Register's bits 233 * Copy from Linux driver source code 234 */ 235 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 236 /* EDSR */ 237 enum EDSR_BIT { 238 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 239 }; 240 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 241 #endif 242 243 /* EDMR */ 244 enum DMAC_M_BIT { 245 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 246 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 247 EDMR_SRST = 0x03, /* Receive/Send reset */ 248 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 249 EDMR_EL = 0x40, /* Litte endian */ 250 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724) 251 EDMR_SRST = 0x01, 252 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 253 EDMR_EL = 0x40, /* Litte endian */ 254 #else /* CONFIG_CPU_SH7763 */ 255 EDMR_SRST = 0x01, 256 #endif 257 }; 258 259 /* RFLR */ 260 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 261 262 /* EDTRR */ 263 enum DMAC_T_BIT { 264 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 265 EDTRR_TRNS = 0x03, 266 #else 267 EDTRR_TRNS = 0x01, 268 #endif 269 }; 270 271 /* GECMR */ 272 enum GECMR_BIT { 273 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 274 }; 275 276 /* EDRRR*/ 277 enum EDRRR_R_BIT { 278 EDRRR_R = 0x01, 279 }; 280 281 /* TPAUSER */ 282 enum TPAUSER_BIT { 283 TPAUSER_TPAUSE = 0x0000ffff, 284 TPAUSER_UNLIMITED = 0, 285 }; 286 287 /* BCFR */ 288 enum BCFR_BIT { 289 BCFR_RPAUSE = 0x0000ffff, 290 BCFR_UNLIMITED = 0, 291 }; 292 293 /* PIR */ 294 enum PIR_BIT { 295 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 296 }; 297 298 /* PSR */ 299 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 300 301 /* EESR */ 302 enum EESR_BIT { 303 304 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) 305 EESR_TWB = 0x40000000, 306 #else 307 EESR_TWB = 0xC0000000, 308 EESR_TC1 = 0x20000000, 309 EESR_TUC = 0x10000000, 310 EESR_ROC = 0x80000000, 311 #endif 312 EESR_TABT = 0x04000000, 313 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 314 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) 315 EESR_ADE = 0x00800000, 316 #endif 317 EESR_ECI = 0x00400000, 318 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 319 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 320 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 321 #if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757) 322 EESR_CND = 0x00000800, 323 #endif 324 EESR_DLC = 0x00000400, 325 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 326 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 327 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 328 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 329 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 330 }; 331 332 333 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 334 # define TX_CHECK (EESR_TC1 | EESR_FTC) 335 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 336 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 337 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 338 339 #else 340 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 341 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 342 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 343 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 344 #endif 345 346 /* EESIPR */ 347 enum DMAC_IM_BIT { 348 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 349 DMAC_M_RABT = 0x02000000, 350 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 351 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 352 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 353 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 354 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 355 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 356 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 357 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 358 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 359 DMAC_M_RINT1 = 0x00000001, 360 }; 361 362 /* Receive descriptor bit */ 363 enum RD_STS_BIT { 364 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 365 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 366 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 367 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 368 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 369 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 370 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 371 RD_RFS1 = 0x00000001, 372 }; 373 #define RDF1ST RD_RFP1 374 #define RDFEND RD_RFP0 375 #define RD_RFP (RD_RFP1|RD_RFP0) 376 377 /* RDFFR*/ 378 enum RDFFR_BIT { 379 RDFFR_RDLF = 0x01, 380 }; 381 382 /* FCFTR */ 383 enum FCFTR_BIT { 384 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 385 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 386 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 387 }; 388 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 389 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 390 391 /* Transfer descriptor bit */ 392 enum TD_STS_BIT { 393 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \ 394 || defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734) 395 TD_TACT = 0x80000000, 396 #else 397 TD_TACT = 0x7fffffff, 398 #endif 399 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 400 TD_TFP0 = 0x10000000, 401 }; 402 #define TDF1ST TD_TFP1 403 #define TDFEND TD_TFP0 404 #define TD_TFP (TD_TFP1|TD_TFP0) 405 406 /* RMCR */ 407 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 408 /* ECMR */ 409 enum FELIC_MODE_BIT { 410 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 411 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 412 ECMR_RZPF = 0x00100000, 413 #endif 414 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 415 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 416 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 417 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 418 ECMR_PRM = 0x00000001, 419 #ifdef CONFIG_CPU_SH7724 420 ECMR_RTM = 0x00000010, 421 #endif 422 423 }; 424 425 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 426 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 427 ECMR_TXF | ECMR_MCT) 428 #elif CONFIG_CPU_SH7757 429 #define ECMR_CHG_DM (ECMR_ZPF) 430 #elif CONFIG_CPU_SH7724 431 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 432 #else 433 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 434 #endif 435 436 /* ECSR */ 437 enum ECSR_STATUS_BIT { 438 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) 439 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 440 #endif 441 ECSR_LCHNG = 0x04, 442 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 443 }; 444 445 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 446 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 447 #else 448 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 449 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 450 #endif 451 452 /* ECSIPR */ 453 enum ECSIPR_STATUS_MASK_BIT { 454 #if defined(CONFIG_CPU_SH7724) 455 ECSIPR_PSRTOIP = 0x10, 456 ECSIPR_LCHNGIP = 0x04, 457 ECSIPR_ICDIP = 0x01, 458 #elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 459 ECSIPR_PSRTOIP = 0x10, 460 ECSIPR_PHYIP = 0x08, 461 ECSIPR_LCHNGIP = 0x04, 462 ECSIPR_MPDIP = 0x02, 463 ECSIPR_ICDIP = 0x01, 464 #endif 465 }; 466 467 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 468 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 469 #else 470 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 471 ECSIPR_ICDIP | ECSIPR_MPDIP) 472 #endif 473 474 /* APR */ 475 enum APR_BIT { 476 #ifdef CONFIG_CPU_SH7757 477 APR_AP = 0x00000001, 478 #else 479 APR_AP = 0x00000004, 480 #endif 481 }; 482 483 /* MPR */ 484 enum MPR_BIT { 485 #ifdef CONFIG_CPU_SH7757 486 MPR_MP = 0x00000001, 487 #else 488 MPR_MP = 0x00000006, 489 #endif 490 }; 491 492 /* TRSCER */ 493 enum DESC_I_BIT { 494 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 495 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 496 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 497 DESC_I_RINT1 = 0x0001, 498 }; 499 500 /* RPADIR */ 501 enum RPADIR_BIT { 502 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 503 RPADIR_PADR = 0x0003f, 504 }; 505 506 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 507 # define RPADIR_INIT (0x00) 508 #else 509 # define RPADIR_INIT (RPADIR_PADS1) 510 #endif 511 512 /* FDR */ 513 enum FIFO_SIZE_BIT { 514 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 515 }; 516