1 /* 2 * sh_eth.c - Driver for Renesas SH7763's ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <config.h> 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/errno.h> 29 #include <asm/io.h> 30 31 #include "sh_eth.h" 32 33 #ifndef CONFIG_SH_ETHER_USE_PORT 34 # error "Please define CONFIG_SH_ETHER_USE_PORT" 35 #endif 36 #ifndef CONFIG_SH_ETHER_PHY_ADDR 37 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 38 #endif 39 40 #define SH_ETH_PHY_DELAY 50000 41 42 /* 43 * Bits are written to the PHY serially using the 44 * PIR register, just like a bit banger. 45 */ 46 static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) 47 { 48 int i; 49 u32 pir; 50 51 /* Bit positions is 1 less than the number of bits */ 52 for (i = len - 1; i >= 0; i--) { 53 /* Write direction, bit to write, clock is low */ 54 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 55 outl(pir, PIR(port)); 56 udelay(1); 57 /* Write direction, bit to write, clock is high */ 58 pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); 59 outl(pir, PIR(port)); 60 udelay(1); 61 /* Write direction, bit to write, clock is low */ 62 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 63 outl(pir, PIR(port)); 64 udelay(1); 65 } 66 } 67 68 static void sh_eth_mii_bus_release(int port) 69 { 70 /* Read direction, clock is low */ 71 outl(0, PIR(port)); 72 udelay(1); 73 /* Read direction, clock is high */ 74 outl(1, PIR(port)); 75 udelay(1); 76 /* Read direction, clock is low */ 77 outl(0, PIR(port)); 78 udelay(1); 79 } 80 81 static void sh_eth_mii_ind_bus_release(int port) 82 { 83 /* Read direction, clock is low */ 84 outl(0, PIR(port)); 85 udelay(1); 86 } 87 88 static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len) 89 { 90 int i; 91 u32 pir; 92 93 *val = 0; 94 for (i = len - 1; i >= 0; i--) { 95 /* Read direction, clock is high */ 96 outl(1, PIR(port)); 97 udelay(1); 98 /* Read bit */ 99 pir = inl(PIR(port)); 100 *val |= (pir & 8) ? 1 << i : 0; 101 /* Read direction, clock is low */ 102 outl(0, PIR(port)); 103 udelay(1); 104 } 105 } 106 107 #define PHY_INIT 0xFFFFFFFF 108 #define PHY_READ 0x02 109 #define PHY_WRITE 0x01 110 /* 111 * To read a phy register, mii managements frames are sent to the phy. 112 * The frames look like this: 113 * pre (32 bits): 0xffff ffff 114 * st (2 bits): 01 115 * op (2bits): 10: read 01: write 116 * phyad (5 bits): xxxxx 117 * regad (5 bits): xxxxx 118 * ta (Bus release): 119 * data (16 bits): read data 120 */ 121 static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) 122 { 123 u32 val; 124 125 /* Sent mii management frame */ 126 /* pre */ 127 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 128 /* st (start of frame) */ 129 sh_eth_mii_write_phy_bits(port, 0x1, 2); 130 /* op (code) */ 131 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 132 /* phy address */ 133 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 134 /* Register to read */ 135 sh_eth_mii_write_phy_bits(port, reg, 5); 136 137 /* Bus release */ 138 sh_eth_mii_bus_release(port); 139 140 /* Read register */ 141 sh_eth_mii_read_phy_bits(port, &val, 16); 142 143 return val; 144 } 145 146 /* 147 * To write a phy register, mii managements frames are sent to the phy. 148 * The frames look like this: 149 * pre (32 bits): 0xffff ffff 150 * st (2 bits): 01 151 * op (2bits): 10: read 01: write 152 * phyad (5 bits): xxxxx 153 * regad (5 bits): xxxxx 154 * ta (2 bits): 10 155 * data (16 bits): write data 156 * idle (Independent bus release) 157 */ 158 static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) 159 { 160 /* Sent mii management frame */ 161 /* pre */ 162 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 163 /* st (start of frame) */ 164 sh_eth_mii_write_phy_bits(port, 0x1, 2); 165 /* op (code) */ 166 sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); 167 /* phy address */ 168 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 169 /* Register to read */ 170 sh_eth_mii_write_phy_bits(port, reg, 5); 171 /* ta */ 172 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 173 /* Write register data */ 174 sh_eth_mii_write_phy_bits(port, val, 16); 175 176 /* Independent bus release */ 177 sh_eth_mii_ind_bus_release(port); 178 } 179 180 int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) 181 { 182 struct sh_eth_dev *eth = dev->priv; 183 int port = eth->port, ret = 0, timeout; 184 struct sh_eth_info *port_info = ð->port_info[port]; 185 186 if (!packet || len > 0xffff) { 187 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 188 ret = -EINVAL; 189 goto err; 190 } 191 192 /* packet must be a 4 byte boundary */ 193 if ((int)packet & (4 - 1)) { 194 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 195 ret = -EFAULT; 196 goto err; 197 } 198 199 /* Update tx descriptor */ 200 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 201 port_info->tx_desc_cur->td1 = len << 16; 202 /* Must preserve the end of descriptor list indication */ 203 if (port_info->tx_desc_cur->td0 & TD_TDLE) 204 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 205 else 206 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 207 208 /* Restart the transmitter if disabled */ 209 if (!(inl(EDTRR(port)) & EDTRR_TRNS)) 210 outl(EDTRR_TRNS, EDTRR(port)); 211 212 /* Wait until packet is transmitted */ 213 timeout = 1000; 214 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 215 udelay(100); 216 217 if (timeout < 0) { 218 printf(SHETHER_NAME ": transmit timeout\n"); 219 ret = -ETIMEDOUT; 220 goto err; 221 } 222 223 port_info->tx_desc_cur++; 224 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 225 port_info->tx_desc_cur = port_info->tx_desc_base; 226 227 return ret; 228 err: 229 return ret; 230 } 231 232 int sh_eth_recv(struct eth_device *dev) 233 { 234 struct sh_eth_dev *eth = dev->priv; 235 int port = eth->port, len = 0; 236 struct sh_eth_info *port_info = ð->port_info[port]; 237 volatile u8 *packet; 238 239 /* Check if the rx descriptor is ready */ 240 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 241 /* Check for errors */ 242 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 243 len = port_info->rx_desc_cur->rd1 & 0xffff; 244 packet = (volatile u8 *) 245 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 246 NetReceive(packet, len); 247 } 248 249 /* Make current descriptor available again */ 250 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 251 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 252 else 253 port_info->rx_desc_cur->rd0 = RD_RACT; 254 255 /* Point to the next descriptor */ 256 port_info->rx_desc_cur++; 257 if (port_info->rx_desc_cur >= 258 port_info->rx_desc_base + NUM_RX_DESC) 259 port_info->rx_desc_cur = port_info->rx_desc_base; 260 } 261 262 /* Restart the receiver if disabled */ 263 if (!(inl(EDRRR(port)) & EDRRR_R)) 264 outl(EDRRR_R, EDRRR(port)); 265 266 return len; 267 } 268 269 #define EDMR_INIT_CNT 1000 270 static int sh_eth_reset(struct sh_eth_dev *eth) 271 { 272 int port = eth->port; 273 int ret = 0, i; 274 275 /* Start e-dmac transmitter and receiver */ 276 outl(EDSR_ENALL, EDSR(port)); 277 278 /* Perform a software reset and wait for it to complete */ 279 outl(EDMR_SRST, EDMR(port)); 280 for (i = 0; i < EDMR_INIT_CNT; i++) { 281 if (!(inl(EDMR(port)) & EDMR_SRST)) 282 break; 283 udelay(1000); 284 } 285 286 if (i == EDMR_INIT_CNT) { 287 printf(SHETHER_NAME ": Software reset timeout\n"); 288 ret = -EIO; 289 } 290 291 return ret; 292 } 293 294 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 295 { 296 int port = eth->port, i, ret = 0; 297 u32 tmp_addr; 298 struct sh_eth_info *port_info = ð->port_info[port]; 299 struct tx_desc_s *cur_tx_desc; 300 301 /* 302 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 303 */ 304 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 305 sizeof(struct tx_desc_s) + 306 TX_DESC_SIZE - 1); 307 if (!port_info->tx_desc_malloc) { 308 printf(SHETHER_NAME ": malloc failed\n"); 309 ret = -ENOMEM; 310 goto err; 311 } 312 313 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 314 ~(TX_DESC_SIZE - 1)); 315 /* Make sure we use a P2 address (non-cacheable) */ 316 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 317 port_info->tx_desc_cur = port_info->tx_desc_base; 318 319 /* Initialize all descriptors */ 320 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 321 cur_tx_desc++, i++) { 322 cur_tx_desc->td0 = 0x00; 323 cur_tx_desc->td1 = 0x00; 324 cur_tx_desc->td2 = 0x00; 325 } 326 327 /* Mark the end of the descriptors */ 328 cur_tx_desc--; 329 cur_tx_desc->td0 |= TD_TDLE; 330 331 /* Point the controller to the tx descriptor list. Must use physical 332 addresses */ 333 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); 334 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); 335 outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); 336 outl(0x01, TDFFR(port));/* Last discriptor bit */ 337 338 err: 339 return ret; 340 } 341 342 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 343 { 344 int port = eth->port, i , ret = 0; 345 struct sh_eth_info *port_info = ð->port_info[port]; 346 struct rx_desc_s *cur_rx_desc; 347 u32 tmp_addr; 348 u8 *rx_buf; 349 350 /* 351 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 352 */ 353 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 354 sizeof(struct rx_desc_s) + 355 RX_DESC_SIZE - 1); 356 if (!port_info->rx_desc_malloc) { 357 printf(SHETHER_NAME ": malloc failed\n"); 358 ret = -ENOMEM; 359 goto err; 360 } 361 362 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 363 ~(RX_DESC_SIZE - 1)); 364 /* Make sure we use a P2 address (non-cacheable) */ 365 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 366 367 port_info->rx_desc_cur = port_info->rx_desc_base; 368 369 /* 370 * Allocate rx data buffers. They must be 32 bytes aligned and in 371 * P2 area 372 */ 373 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 374 if (!port_info->rx_buf_malloc) { 375 printf(SHETHER_NAME ": malloc failed\n"); 376 ret = -ENOMEM; 377 goto err_buf_malloc; 378 } 379 380 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 381 ~(32 - 1)); 382 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 383 384 /* Initialize all descriptors */ 385 for (cur_rx_desc = port_info->rx_desc_base, 386 rx_buf = port_info->rx_buf_base, i = 0; 387 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 388 cur_rx_desc->rd0 = RD_RACT; 389 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 390 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 391 } 392 393 /* Mark the end of the descriptors */ 394 cur_rx_desc--; 395 cur_rx_desc->rd0 |= RD_RDLE; 396 397 /* Point the controller to the rx descriptor list */ 398 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); 399 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); 400 outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); 401 outl(RDFFR_RDLF, RDFFR(port)); 402 403 return ret; 404 405 err_buf_malloc: 406 free(port_info->rx_desc_malloc); 407 port_info->rx_desc_malloc = NULL; 408 409 err: 410 return ret; 411 } 412 413 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 414 { 415 int port = eth->port; 416 struct sh_eth_info *port_info = ð->port_info[port]; 417 418 if (port_info->tx_desc_malloc) { 419 free(port_info->tx_desc_malloc); 420 port_info->tx_desc_malloc = NULL; 421 } 422 } 423 424 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 425 { 426 int port = eth->port; 427 struct sh_eth_info *port_info = ð->port_info[port]; 428 429 if (port_info->rx_desc_malloc) { 430 free(port_info->rx_desc_malloc); 431 port_info->rx_desc_malloc = NULL; 432 } 433 434 if (port_info->rx_buf_malloc) { 435 free(port_info->rx_buf_malloc); 436 port_info->rx_buf_malloc = NULL; 437 } 438 } 439 440 static int sh_eth_desc_init(struct sh_eth_dev *eth) 441 { 442 int ret = 0; 443 444 ret = sh_eth_tx_desc_init(eth); 445 if (ret) 446 goto err_tx_init; 447 448 ret = sh_eth_rx_desc_init(eth); 449 if (ret) 450 goto err_rx_init; 451 452 return ret; 453 err_rx_init: 454 sh_eth_tx_desc_free(eth); 455 456 err_tx_init: 457 return ret; 458 } 459 460 static int sh_eth_phy_config(struct sh_eth_dev *eth) 461 { 462 int port = eth->port, timeout, ret = 0; 463 struct sh_eth_info *port_info = ð->port_info[port]; 464 u32 val; 465 466 /* Reset phy */ 467 sh_eth_mii_write_phy_reg 468 (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); 469 timeout = 10; 470 while (timeout--) { 471 val = sh_eth_mii_read_phy_reg(port, 472 port_info->phy_addr, PHY_CTRL); 473 if (!(val & PHY_C_RESET)) 474 break; 475 udelay(SH_ETH_PHY_DELAY); 476 } 477 478 if (timeout < 0) { 479 printf(SHETHER_NAME ": phy reset timeout\n"); 480 ret = -EIO; 481 goto err_tout; 482 } 483 484 /* Advertise 100/10 baseT full/half duplex */ 485 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, 486 (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); 487 /* Autonegotiation, normal operation, full duplex, enable tx */ 488 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, 489 (PHY_C_ANEGEN|PHY_C_RANEG)); 490 /* Wait for autonegotiation to complete */ 491 timeout = 100; 492 while (timeout--) { 493 val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 494 if (val & PHY_S_ANEGC) 495 break; 496 497 udelay(SH_ETH_PHY_DELAY); 498 } 499 500 if (timeout < 0) { 501 printf(SHETHER_NAME ": phy auto-negotiation failed\n"); 502 ret = -ETIMEDOUT; 503 goto err_tout; 504 } 505 506 return ret; 507 508 err_tout: 509 return ret; 510 } 511 512 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 513 { 514 int port = eth->port, ret = 0; 515 u32 val, phy_status; 516 struct sh_eth_info *port_info = ð->port_info[port]; 517 518 /* Configure e-dmac registers */ 519 outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); 520 outl(0, EESIPR(port)); 521 outl(0, TRSCER(port)); 522 outl(0, TFTR(port)); 523 outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); 524 outl(RMCR_RST, RMCR(port)); 525 outl(0, RPADIR(port)); 526 outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); 527 528 /* Configure e-mac registers */ 529 outl(0, ECSIPR(port)); 530 531 /* Set Mac address */ 532 val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 | 533 bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3]; 534 outl(val, MAHR(port)); 535 536 val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5]; 537 outl(val, MALR(port)); 538 539 outl(RFLR_RFL_MIN, RFLR(port)); 540 outl(0, PIPR(port)); 541 outl(APR_AP, APR(port)); 542 outl(MPR_MP, MPR(port)); 543 outl(TPAUSER_TPAUSE, TPAUSER(port)); 544 545 /* Configure phy */ 546 ret = sh_eth_phy_config(eth); 547 if (ret) { 548 printf(SHETHER_NAME ":i phy config timeout\n"); 549 goto err_phy_cfg; 550 } 551 /* Read phy status to finish configuring the e-mac */ 552 phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 553 554 /* Set the transfer speed */ 555 if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { 556 printf(SHETHER_NAME ": 100Base/"); 557 outl(GECMR_100B, GECMR(port)); 558 } else { 559 printf(SHETHER_NAME ": 10Base/"); 560 outl(GECMR_10B, GECMR(port)); 561 } 562 563 /* Check if full duplex mode is supported by the phy */ 564 if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { 565 printf("Full\n"); 566 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); 567 } else { 568 printf("Half\n"); 569 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); 570 } 571 572 return ret; 573 574 err_phy_cfg: 575 return ret; 576 } 577 578 static void sh_eth_start(struct sh_eth_dev *eth) 579 { 580 /* 581 * Enable the e-dmac receiver only. The transmitter will be enabled when 582 * we have something to transmit 583 */ 584 outl(EDRRR_R, EDRRR(eth->port)); 585 } 586 587 static void sh_eth_stop(struct sh_eth_dev *eth) 588 { 589 outl(~EDRRR_R, EDRRR(eth->port)); 590 } 591 592 static int sh_eth_get_mac(bd_t *bd) 593 { 594 char *s, *e; 595 596 s = getenv("ethaddr"); 597 if (s != NULL) { 598 int i; 599 for (i = 0; i < 6; ++i) { 600 bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; 601 if (s) 602 s = (*e) ? e + 1 : e; 603 } 604 } else { 605 puts("Please set MAC address\n"); 606 } 607 return 0; 608 } 609 610 int sh_eth_init(struct eth_device *dev, bd_t *bd) 611 { 612 int ret = 0; 613 struct sh_eth_dev *eth = dev->priv; 614 615 ret = sh_eth_reset(eth); 616 if (ret) 617 goto err; 618 619 ret = sh_eth_desc_init(eth); 620 if (ret) 621 goto err; 622 623 ret = sh_eth_config(eth, bd); 624 if (ret) 625 goto err_config; 626 627 sh_eth_start(eth); 628 629 return ret; 630 631 err_config: 632 sh_eth_tx_desc_free(eth); 633 sh_eth_rx_desc_free(eth); 634 635 err: 636 return ret; 637 } 638 639 void sh_eth_halt(struct eth_device *dev) 640 { 641 struct sh_eth_dev *eth = dev->priv; 642 643 sh_eth_reset(eth); 644 sh_eth_stop(eth); 645 } 646 647 int sh_eth_initialize(bd_t *bd) 648 { 649 int ret = 0; 650 struct sh_eth_dev *eth = NULL; 651 struct eth_device *dev = NULL; 652 653 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 654 if (!eth) { 655 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 656 ret = -ENOMEM; 657 goto err; 658 } 659 660 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 661 if (!dev) { 662 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 663 ret = -ENOMEM; 664 goto err; 665 } 666 memset(dev, 0, sizeof(struct eth_device)); 667 memset(eth, 0, sizeof(struct sh_eth_dev)); 668 669 eth->port = CONFIG_SH_ETHER_USE_PORT; 670 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 671 672 dev->priv = (void *)eth; 673 dev->iobase = 0; 674 dev->init = sh_eth_init; 675 dev->halt = sh_eth_halt; 676 dev->send = sh_eth_send; 677 dev->recv = sh_eth_recv; 678 eth->port_info[eth->port].dev = dev; 679 680 sprintf(dev->name, SHETHER_NAME); 681 682 /* Register Device to EtherNet subsystem */ 683 eth_register(dev); 684 685 sh_eth_get_mac(bd); 686 687 return ret; 688 689 err: 690 if (dev) 691 free(dev); 692 693 if (eth) 694 free(eth); 695 696 printf(SHETHER_NAME ": Failed\n"); 697 return ret; 698 } 699